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a4f08dbb | 1 | /* SPDX-License-Identifier: MIT */ |
dd08ebf6 | 2 | /* |
a4f08dbb | 3 | * Copyright © 2023 Intel Corporation |
dd08ebf6 MB |
4 | */ |
5 | ||
6 | #ifndef _UAPI_XE_DRM_H_ | |
7 | #define _UAPI_XE_DRM_H_ | |
8 | ||
9 | #include "drm.h" | |
10 | ||
11 | #if defined(__cplusplus) | |
12 | extern "C" { | |
13 | #endif | |
14 | ||
76ca3a22 RV |
15 | /* |
16 | * Please note that modifications to all structs defined here are | |
dd08ebf6 | 17 | * subject to backwards-compatibility constraints. |
76ca3a22 RV |
18 | * Sections in this file are organized as follows: |
19 | * 1. IOCTL definition | |
20 | * 2. Extension definition and helper structs | |
21 | * 3. IOCTL's Query structs in the order of the Query's entries. | |
22 | * 4. The rest of IOCTL structs in the order of IOCTL declaration. | |
dd08ebf6 MB |
23 | */ |
24 | ||
33c6fda6 FD |
25 | /** |
26 | * DOC: Xe Device Block Diagram | |
27 | * | |
28 | * The diagram below represents a high-level simplification of a discrete | |
29 | * GPU supported by the Xe driver. It shows some device components which | |
30 | * are necessary to understand this API, as well as how their relations | |
31 | * to each other. This diagram does not represent real hardware:: | |
32 | * | |
33 | * ┌──────────────────────────────────────────────────────────────────┐ | |
34 | * │ ┌──────────────────────────────────────────────────┐ ┌─────────┐ │ | |
35 | * │ │ ┌───────────────────────┐ ┌─────┐ │ │ ┌─────┐ │ │ | |
36 | * │ │ │ VRAM0 ├───┤ ... │ │ │ │VRAM1│ │ │ | |
37 | * │ │ └───────────┬───────────┘ └─GT1─┘ │ │ └──┬──┘ │ │ | |
38 | * │ │ ┌──────────────────┴───────────────────────────┐ │ │ ┌──┴──┐ │ │ | |
39 | * │ │ │ ┌─────────────────────┐ ┌─────────────────┐ │ │ │ │ │ │ │ | |
40 | * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ | |
41 | * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │RCS0 │ │BCS0 │ │ │ │ │ │ │ │ │ | |
42 | * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ | |
43 | * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ | |
44 | * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │VCS0 │ │VCS1 │ │ │ │ │ │ │ │ │ | |
45 | * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ | |
46 | * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ | |
47 | * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │VECS0│ │VECS1│ │ │ │ │ │ ... │ │ │ | |
48 | * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ | |
49 | * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ | |
50 | * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │CCS0 │ │CCS1 │ │ │ │ │ │ │ │ │ | |
51 | * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ | |
52 | * │ │ │ └─────────DSS─────────┘ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ | |
53 | * │ │ │ │ │CCS2 │ │CCS3 │ │ │ │ │ │ │ │ │ | |
54 | * │ │ │ ┌─────┐ ┌─────┐ ┌─────┐ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ | |
55 | * │ │ │ │ ... │ │ ... │ │ ... │ │ │ │ │ │ │ │ │ │ | |
56 | * │ │ │ └─DSS─┘ └─DSS─┘ └─DSS─┘ └─────Engines─────┘ │ │ │ │ │ │ │ | |
57 | * │ │ └───────────────────────────GT0────────────────┘ │ │ └─GT2─┘ │ │ | |
58 | * │ └────────────────────────────Tile0─────────────────┘ └─ Tile1──┘ │ | |
59 | * └─────────────────────────────Device0───────┬──────────────────────┘ | |
60 | * │ | |
61 | * ───────────────────────┴────────── PCI bus | |
62 | */ | |
63 | ||
4b437893 RV |
64 | /** |
65 | * DOC: Xe uAPI Overview | |
66 | * | |
67 | * This section aims to describe the Xe's IOCTL entries, its structs, and other | |
68 | * Xe related uAPI such as uevents and PMU (Platform Monitoring Unit) related | |
69 | * entries and usage. | |
70 | * | |
71 | * List of supported IOCTLs: | |
72 | * - &DRM_IOCTL_XE_DEVICE_QUERY | |
73 | * - &DRM_IOCTL_XE_GEM_CREATE | |
74 | * - &DRM_IOCTL_XE_GEM_MMAP_OFFSET | |
75 | * - &DRM_IOCTL_XE_VM_CREATE | |
76 | * - &DRM_IOCTL_XE_VM_DESTROY | |
77 | * - &DRM_IOCTL_XE_VM_BIND | |
78 | * - &DRM_IOCTL_XE_EXEC_QUEUE_CREATE | |
79 | * - &DRM_IOCTL_XE_EXEC_QUEUE_DESTROY | |
80 | * - &DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY | |
81 | * - &DRM_IOCTL_XE_EXEC | |
82 | * - &DRM_IOCTL_XE_WAIT_USER_FENCE | |
83 | */ | |
84 | ||
76ca3a22 RV |
85 | /* |
86 | * xe specific ioctls. | |
4f027e30 | 87 | * |
76ca3a22 RV |
88 | * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie |
89 | * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset | |
90 | * against DRM_COMMAND_BASE and should be between [0x0, 0x60). | |
4f027e30 | 91 | */ |
76ca3a22 RV |
92 | #define DRM_XE_DEVICE_QUERY 0x00 |
93 | #define DRM_XE_GEM_CREATE 0x01 | |
94 | #define DRM_XE_GEM_MMAP_OFFSET 0x02 | |
95 | #define DRM_XE_VM_CREATE 0x03 | |
96 | #define DRM_XE_VM_DESTROY 0x04 | |
97 | #define DRM_XE_VM_BIND 0x05 | |
98 | #define DRM_XE_EXEC_QUEUE_CREATE 0x06 | |
99 | #define DRM_XE_EXEC_QUEUE_DESTROY 0x07 | |
100 | #define DRM_XE_EXEC_QUEUE_GET_PROPERTY 0x08 | |
101 | #define DRM_XE_EXEC 0x09 | |
102 | #define DRM_XE_WAIT_USER_FENCE 0x0a | |
103 | /* Must be kept compact -- no holes */ | |
104 | ||
105 | #define DRM_IOCTL_XE_DEVICE_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_DEVICE_QUERY, struct drm_xe_device_query) | |
106 | #define DRM_IOCTL_XE_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_CREATE, struct drm_xe_gem_create) | |
107 | #define DRM_IOCTL_XE_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_MMAP_OFFSET, struct drm_xe_gem_mmap_offset) | |
108 | #define DRM_IOCTL_XE_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_CREATE, struct drm_xe_vm_create) | |
109 | #define DRM_IOCTL_XE_VM_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_DESTROY, struct drm_xe_vm_destroy) | |
110 | #define DRM_IOCTL_XE_VM_BIND DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_BIND, struct drm_xe_vm_bind) | |
111 | #define DRM_IOCTL_XE_EXEC_QUEUE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_CREATE, struct drm_xe_exec_queue_create) | |
112 | #define DRM_IOCTL_XE_EXEC_QUEUE_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_DESTROY, struct drm_xe_exec_queue_destroy) | |
113 | #define DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_GET_PROPERTY, struct drm_xe_exec_queue_get_property) | |
114 | #define DRM_IOCTL_XE_EXEC DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC, struct drm_xe_exec) | |
115 | #define DRM_IOCTL_XE_WAIT_USER_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_WAIT_USER_FENCE, struct drm_xe_wait_user_fence) | |
4f027e30 | 116 | |
dd08ebf6 | 117 | /** |
4b437893 RV |
118 | * DOC: Xe IOCTL Extensions |
119 | * | |
120 | * Before detailing the IOCTLs and its structs, it is important to highlight | |
121 | * that every IOCTL in Xe is extensible. | |
dd08ebf6 MB |
122 | * |
123 | * Many interfaces need to grow over time. In most cases we can simply | |
124 | * extend the struct and have userspace pass in more data. Another option, | |
125 | * as demonstrated by Vulkan's approach to providing extensions for forward | |
126 | * and backward compatibility, is to use a list of optional structs to | |
127 | * provide those extra details. | |
128 | * | |
129 | * The key advantage to using an extension chain is that it allows us to | |
130 | * redefine the interface more easily than an ever growing struct of | |
131 | * increasing complexity, and for large parts of that interface to be | |
132 | * entirely optional. The downside is more pointer chasing; chasing across | |
133 | * the __user boundary with pointers encapsulated inside u64. | |
134 | * | |
135 | * Example chaining: | |
136 | * | |
137 | * .. code-block:: C | |
138 | * | |
7e9337c2 | 139 | * struct drm_xe_user_extension ext3 { |
dd08ebf6 MB |
140 | * .next_extension = 0, // end |
141 | * .name = ..., | |
142 | * }; | |
7e9337c2 | 143 | * struct drm_xe_user_extension ext2 { |
dd08ebf6 MB |
144 | * .next_extension = (uintptr_t)&ext3, |
145 | * .name = ..., | |
146 | * }; | |
7e9337c2 | 147 | * struct drm_xe_user_extension ext1 { |
dd08ebf6 MB |
148 | * .next_extension = (uintptr_t)&ext2, |
149 | * .name = ..., | |
150 | * }; | |
151 | * | |
7e9337c2 | 152 | * Typically the struct drm_xe_user_extension would be embedded in some uAPI |
dd08ebf6 MB |
153 | * struct, and in this case we would feed it the head of the chain(i.e ext1), |
154 | * which would then apply all of the above extensions. | |
4b437893 RV |
155 | */ |
156 | ||
157 | /** | |
158 | * struct drm_xe_user_extension - Base class for defining a chain of extensions | |
dd08ebf6 | 159 | */ |
7e9337c2 | 160 | struct drm_xe_user_extension { |
dd08ebf6 MB |
161 | /** |
162 | * @next_extension: | |
163 | * | |
7e9337c2 | 164 | * Pointer to the next struct drm_xe_user_extension, or zero if the end. |
dd08ebf6 MB |
165 | */ |
166 | __u64 next_extension; | |
4f082f2c | 167 | |
dd08ebf6 MB |
168 | /** |
169 | * @name: Name of the extension. | |
170 | * | |
171 | * Note that the name here is just some integer. | |
172 | * | |
173 | * Also note that the name space for this is not global for the whole | |
174 | * driver, but rather its scope/meaning is limited to the specific piece | |
7e9337c2 | 175 | * of uAPI which has embedded the struct drm_xe_user_extension. |
dd08ebf6 MB |
176 | */ |
177 | __u32 name; | |
4f082f2c | 178 | |
dd08ebf6 | 179 | /** |
e2bd81af | 180 | * @pad: MBZ |
dd08ebf6 MB |
181 | * |
182 | * All undefined bits must be zero. | |
183 | */ | |
184 | __u32 pad; | |
185 | }; | |
186 | ||
76ca3a22 | 187 | /** |
4b437893 RV |
188 | * struct drm_xe_ext_set_property - Generic set property extension |
189 | * | |
190 | * A generic struct that allows any of the Xe's IOCTL to be extended | |
191 | * with a set_property operation. | |
dd08ebf6 | 192 | */ |
76ca3a22 RV |
193 | struct drm_xe_ext_set_property { |
194 | /** @base: base user extension */ | |
195 | struct drm_xe_user_extension base; | |
ddfa2d6a | 196 | |
76ca3a22 RV |
197 | /** @property: property to set */ |
198 | __u32 property; | |
199 | ||
200 | /** @pad: MBZ */ | |
201 | __u32 pad; | |
202 | ||
203 | /** @value: property value */ | |
204 | __u64 value; | |
205 | ||
206 | /** @reserved: Reserved */ | |
207 | __u64 reserved[2]; | |
208 | }; | |
dd08ebf6 | 209 | |
2bec3071 JRS |
210 | /** |
211 | * struct drm_xe_engine_class_instance - instance of an engine class | |
212 | * | |
60a6a849 FD |
213 | * It is returned as part of the @drm_xe_engine, but it also is used as |
214 | * the input of engine selection for both @drm_xe_exec_queue_create and | |
215 | * @drm_xe_query_engine_cycles | |
801989b0 FD |
216 | * |
217 | * The @engine_class can be: | |
218 | * - %DRM_XE_ENGINE_CLASS_RENDER | |
219 | * - %DRM_XE_ENGINE_CLASS_COPY | |
220 | * - %DRM_XE_ENGINE_CLASS_VIDEO_DECODE | |
221 | * - %DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE | |
222 | * - %DRM_XE_ENGINE_CLASS_COMPUTE | |
223 | * - %DRM_XE_ENGINE_CLASS_VM_BIND - Kernel only classes (not actual | |
224 | * hardware engine class). Used for creating ordered queues of VM | |
225 | * bind operations. | |
2bec3071 | 226 | */ |
7793d00d UNR |
227 | struct drm_xe_engine_class_instance { |
228 | #define DRM_XE_ENGINE_CLASS_RENDER 0 | |
229 | #define DRM_XE_ENGINE_CLASS_COPY 1 | |
230 | #define DRM_XE_ENGINE_CLASS_VIDEO_DECODE 2 | |
231 | #define DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 3 | |
232 | #define DRM_XE_ENGINE_CLASS_COMPUTE 4 | |
d3d76739 | 233 | #define DRM_XE_ENGINE_CLASS_VM_BIND 5 |
2bec3071 | 234 | /** @engine_class: engine class id */ |
7793d00d | 235 | __u16 engine_class; |
2bec3071 | 236 | /** @engine_instance: engine instance id */ |
7793d00d | 237 | __u16 engine_instance; |
2bec3071 | 238 | /** @gt_id: Unique ID of this GT within the PCI Device */ |
7793d00d | 239 | __u16 gt_id; |
5ca2c4b8 FD |
240 | /** @pad: MBZ */ |
241 | __u16 pad; | |
7793d00d UNR |
242 | }; |
243 | ||
2bec3071 | 244 | /** |
60a6a849 | 245 | * struct drm_xe_engine - describe hardware engine |
2bec3071 | 246 | */ |
60a6a849 | 247 | struct drm_xe_engine { |
2bec3071 JRS |
248 | /** @instance: The @drm_xe_engine_class_instance */ |
249 | struct drm_xe_engine_class_instance instance; | |
250 | ||
251 | /** @reserved: Reserved */ | |
252 | __u64 reserved[3]; | |
253 | }; | |
254 | ||
60a6a849 FD |
255 | /** |
256 | * struct drm_xe_query_engines - describe engines | |
257 | * | |
258 | * If a query is made with a struct @drm_xe_device_query where .query | |
259 | * is equal to %DRM_XE_DEVICE_QUERY_ENGINES, then the reply uses an array of | |
260 | * struct @drm_xe_query_engines in .data. | |
261 | */ | |
262 | struct drm_xe_query_engines { | |
263 | /** @num_engines: number of engines returned in @engines */ | |
264 | __u32 num_engines; | |
265 | /** @pad: MBZ */ | |
266 | __u32 pad; | |
267 | /** @engines: The returned engines for this device */ | |
268 | struct drm_xe_engine engines[]; | |
269 | }; | |
270 | ||
a9c4a069 MA |
271 | /** |
272 | * enum drm_xe_memory_class - Supported memory classes. | |
273 | */ | |
274 | enum drm_xe_memory_class { | |
d5dc73db FD |
275 | /** @DRM_XE_MEM_REGION_CLASS_SYSMEM: Represents system memory. */ |
276 | DRM_XE_MEM_REGION_CLASS_SYSMEM = 0, | |
a9c4a069 | 277 | /** |
d5dc73db | 278 | * @DRM_XE_MEM_REGION_CLASS_VRAM: On discrete platforms, this |
a9c4a069 MA |
279 | * represents the memory that is local to the device, which we |
280 | * call VRAM. Not valid on integrated platforms. | |
281 | */ | |
d5dc73db | 282 | DRM_XE_MEM_REGION_CLASS_VRAM |
a9c4a069 MA |
283 | }; |
284 | ||
285 | /** | |
4bc9dd98 | 286 | * struct drm_xe_mem_region - Describes some region as known to |
a9c4a069 MA |
287 | * the driver. |
288 | */ | |
4bc9dd98 | 289 | struct drm_xe_mem_region { |
a9c4a069 MA |
290 | /** |
291 | * @mem_class: The memory class describing this region. | |
292 | * | |
293 | * See enum drm_xe_memory_class for supported values. | |
294 | */ | |
295 | __u16 mem_class; | |
296 | /** | |
535881a8 RV |
297 | * @instance: The unique ID for this region, which serves as the |
298 | * index in the placement bitmask used as argument for | |
299 | * &DRM_IOCTL_XE_GEM_CREATE | |
a9c4a069 MA |
300 | */ |
301 | __u16 instance; | |
a9c4a069 MA |
302 | /** |
303 | * @min_page_size: Min page-size in bytes for this region. | |
304 | * | |
305 | * When the kernel allocates memory for this region, the | |
306 | * underlying pages will be at least @min_page_size in size. | |
4e03b584 MCC |
307 | * Buffer objects with an allowable placement in this region must be |
308 | * created with a size aligned to this value. | |
309 | * GPU virtual address mappings of (parts of) buffer objects that | |
310 | * may be placed in this region must also have their GPU virtual | |
311 | * address and range aligned to this value. | |
312 | * Affected IOCTLS will return %-EINVAL if alignment restrictions are | |
313 | * not met. | |
a9c4a069 MA |
314 | */ |
315 | __u32 min_page_size; | |
a9c4a069 MA |
316 | /** |
317 | * @total_size: The usable size in bytes for this region. | |
318 | */ | |
319 | __u64 total_size; | |
320 | /** | |
321 | * @used: Estimate of the memory used in bytes for this region. | |
322 | * | |
323 | * Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable | |
324 | * accounting. Without this the value here will always equal | |
325 | * zero. | |
326 | */ | |
327 | __u64 used; | |
cd928fce MA |
328 | /** |
329 | * @cpu_visible_size: How much of this region can be CPU | |
330 | * accessed, in bytes. | |
331 | * | |
332 | * This will always be <= @total_size, and the remainder (if | |
333 | * any) will not be CPU accessible. If the CPU accessible part | |
334 | * is smaller than @total_size then this is referred to as a | |
335 | * small BAR system. | |
336 | * | |
337 | * On systems without small BAR (full BAR), the probed_size will | |
338 | * always equal the @total_size, since all of it will be CPU | |
339 | * accessible. | |
340 | * | |
d5dc73db | 341 | * Note this is only tracked for DRM_XE_MEM_REGION_CLASS_VRAM |
cd928fce MA |
342 | * regions (for other types the value here will always equal |
343 | * zero). | |
344 | */ | |
345 | __u64 cpu_visible_size; | |
346 | /** | |
347 | * @cpu_visible_used: Estimate of CPU visible memory used, in | |
348 | * bytes. | |
349 | * | |
350 | * Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable | |
351 | * accounting. Without this the value here will always equal | |
352 | * zero. Note this is only currently tracked for | |
d5dc73db | 353 | * DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value |
cd928fce MA |
354 | * here will always be zero). |
355 | */ | |
356 | __u64 cpu_visible_used; | |
4b437893 | 357 | /** @reserved: Reserved */ |
cd928fce | 358 | __u64 reserved[6]; |
a9c4a069 | 359 | }; |
dd08ebf6 | 360 | |
ffd6620f | 361 | /** |
b02606d3 | 362 | * struct drm_xe_query_mem_regions - describe memory regions |
ffd6620f FD |
363 | * |
364 | * If a query is made with a struct drm_xe_device_query where .query | |
b02606d3 RV |
365 | * is equal to DRM_XE_DEVICE_QUERY_MEM_REGIONS, then the reply uses |
366 | * struct drm_xe_query_mem_regions in .data. | |
ffd6620f | 367 | */ |
b02606d3 | 368 | struct drm_xe_query_mem_regions { |
4bc9dd98 FD |
369 | /** @num_mem_regions: number of memory regions returned in @mem_regions */ |
370 | __u32 num_mem_regions; | |
ffd6620f | 371 | /** @pad: MBZ */ |
dd08ebf6 | 372 | __u32 pad; |
4bc9dd98 FD |
373 | /** @mem_regions: The returned memory regions for this device */ |
374 | struct drm_xe_mem_region mem_regions[]; | |
dd08ebf6 MB |
375 | }; |
376 | ||
ffd6620f FD |
377 | /** |
378 | * struct drm_xe_query_config - describe the device configuration | |
379 | * | |
380 | * If a query is made with a struct drm_xe_device_query where .query | |
381 | * is equal to DRM_XE_DEVICE_QUERY_CONFIG, then the reply uses | |
382 | * struct drm_xe_query_config in .data. | |
4195e5e5 | 383 | * |
801989b0 FD |
384 | * The index in @info can be: |
385 | * - %DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID - Device ID (lower 16 bits) | |
386 | * and the device revision (next 8 bits) | |
387 | * - %DRM_XE_QUERY_CONFIG_FLAGS - Flags describing the device | |
388 | * configuration, see list below | |
389 | * | |
390 | * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM - Flag is set if the device | |
391 | * has usable VRAM | |
392 | * - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory alignment | |
393 | * required by this device, typically SZ_4K or SZ_64K | |
394 | * - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual address | |
395 | * - %DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY - Value of the highest | |
396 | * available exec queue priority | |
ffd6620f | 397 | */ |
dd08ebf6 | 398 | struct drm_xe_query_config { |
ffd6620f | 399 | /** @num_params: number of parameters returned in info */ |
dd08ebf6 | 400 | __u32 num_params; |
ffd6620f FD |
401 | |
402 | /** @pad: MBZ */ | |
dd08ebf6 | 403 | __u32 pad; |
ffd6620f | 404 | |
d5dc73db FD |
405 | #define DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0 |
406 | #define DRM_XE_QUERY_CONFIG_FLAGS 1 | |
9ad74351 | 407 | #define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0) |
d5dc73db FD |
408 | #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2 |
409 | #define DRM_XE_QUERY_CONFIG_VA_BITS 3 | |
410 | #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4 | |
ffd6620f | 411 | /** @info: array of elements containing the config info */ |
dd08ebf6 MB |
412 | __u64 info[]; |
413 | }; | |
414 | ||
25f656f5 | 415 | /** |
71c625aa | 416 | * struct drm_xe_gt - describe an individual GT. |
25f656f5 | 417 | * |
e16b4837 | 418 | * To be used with drm_xe_query_gt_list, which will return a list with all the |
25f656f5 RV |
419 | * existing GT individual descriptions. |
420 | * Graphics Technology (GT) is a subset of a GPU/tile that is responsible for | |
421 | * implementing graphics and/or media operations. | |
801989b0 FD |
422 | * |
423 | * The index in @type can be: | |
424 | * - %DRM_XE_QUERY_GT_TYPE_MAIN | |
425 | * - %DRM_XE_QUERY_GT_TYPE_MEDIA | |
25f656f5 | 426 | */ |
71c625aa | 427 | struct drm_xe_gt { |
d5dc73db FD |
428 | #define DRM_XE_QUERY_GT_TYPE_MAIN 0 |
429 | #define DRM_XE_QUERY_GT_TYPE_MEDIA 1 | |
1a912c90 | 430 | /** @type: GT type: Main or Media */ |
25f656f5 | 431 | __u16 type; |
c3fca107 RV |
432 | /** @tile_id: Tile ID where this GT lives (Information only) */ |
433 | __u16 tile_id; | |
2519450a RV |
434 | /** @gt_id: Unique ID of this GT within the PCI Device */ |
435 | __u16 gt_id; | |
7a56bd0c RV |
436 | /** @pad: MBZ */ |
437 | __u16 pad[3]; | |
4016d6bf RV |
438 | /** @reference_clock: A clock frequency for timestamp */ |
439 | __u32 reference_clock; | |
25f656f5 | 440 | /** |
45c30d80 | 441 | * @near_mem_regions: Bit mask of instances from |
b02606d3 | 442 | * drm_xe_query_mem_regions that are nearest to the current engines |
45c30d80 | 443 | * of this GT. |
535881a8 RV |
444 | * Each index in this mask refers directly to the struct |
445 | * drm_xe_query_mem_regions' instance, no assumptions should | |
446 | * be made about order. The type of each region is described | |
447 | * by struct drm_xe_query_mem_regions' mem_class. | |
25f656f5 | 448 | */ |
45c30d80 | 449 | __u64 near_mem_regions; |
25f656f5 | 450 | /** |
45c30d80 | 451 | * @far_mem_regions: Bit mask of instances from |
b02606d3 | 452 | * drm_xe_query_mem_regions that are far from the engines of this GT. |
45c30d80 RV |
453 | * In general, they have extra indirections when compared to the |
454 | * @near_mem_regions. For a discrete device this could mean system | |
455 | * memory and memory living in a different tile. | |
535881a8 RV |
456 | * Each index in this mask refers directly to the struct |
457 | * drm_xe_query_mem_regions' instance, no assumptions should | |
458 | * be made about order. The type of each region is described | |
459 | * by struct drm_xe_query_mem_regions' mem_class. | |
25f656f5 | 460 | */ |
45c30d80 | 461 | __u64 far_mem_regions; |
8e61e319 MR |
462 | /** @ip_ver_major: Graphics/media IP major version on GMD_ID platforms */ |
463 | __u16 ip_ver_major; | |
464 | /** @ip_ver_minor: Graphics/media IP minor version on GMD_ID platforms */ | |
465 | __u16 ip_ver_minor; | |
466 | /** @ip_ver_rev: Graphics/media IP revision version on GMD_ID platforms */ | |
467 | __u16 ip_ver_rev; | |
468 | /** @pad2: MBZ */ | |
469 | __u16 pad2; | |
25f656f5 | 470 | /** @reserved: Reserved */ |
8e61e319 | 471 | __u64 reserved[7]; |
25f656f5 RV |
472 | }; |
473 | ||
ffd6620f | 474 | /** |
e16b4837 | 475 | * struct drm_xe_query_gt_list - A list with GT description items. |
ffd6620f FD |
476 | * |
477 | * If a query is made with a struct drm_xe_device_query where .query | |
e16b4837 RV |
478 | * is equal to DRM_XE_DEVICE_QUERY_GT_LIST, then the reply uses struct |
479 | * drm_xe_query_gt_list in .data. | |
ffd6620f | 480 | */ |
e16b4837 RV |
481 | struct drm_xe_query_gt_list { |
482 | /** @num_gt: number of GT items returned in gt_list */ | |
dd08ebf6 | 483 | __u32 num_gt; |
ffd6620f | 484 | /** @pad: MBZ */ |
dd08ebf6 | 485 | __u32 pad; |
e16b4837 | 486 | /** @gt_list: The GT list returned for this device */ |
71c625aa | 487 | struct drm_xe_gt gt_list[]; |
dd08ebf6 MB |
488 | }; |
489 | ||
ffd6620f FD |
490 | /** |
491 | * struct drm_xe_query_topology_mask - describe the topology mask of a GT | |
492 | * | |
1bc56a93 FD |
493 | * This is the hardware topology which reflects the internal physical |
494 | * structure of the GPU. | |
495 | * | |
ffd6620f FD |
496 | * If a query is made with a struct drm_xe_device_query where .query |
497 | * is equal to DRM_XE_DEVICE_QUERY_GT_TOPOLOGY, then the reply uses | |
498 | * struct drm_xe_query_topology_mask in .data. | |
801989b0 FD |
499 | * |
500 | * The @type can be: | |
501 | * - %DRM_XE_TOPO_DSS_GEOMETRY - To query the mask of Dual Sub Slices | |
502 | * (DSS) available for geometry operations. For example a query response | |
503 | * containing the following in mask: | |
504 | * ``DSS_GEOMETRY ff ff ff ff 00 00 00 00`` | |
505 | * means 32 DSS are available for geometry. | |
506 | * - %DRM_XE_TOPO_DSS_COMPUTE - To query the mask of Dual Sub Slices | |
507 | * (DSS) available for compute operations. For example a query response | |
508 | * containing the following in mask: | |
509 | * ``DSS_COMPUTE ff ff ff ff 00 00 00 00`` | |
510 | * means 32 DSS are available for compute. | |
511 | * - %DRM_XE_TOPO_EU_PER_DSS - To query the mask of Execution Units (EU) | |
512 | * available per Dual Sub Slices (DSS). For example a query response | |
513 | * containing the following in mask: | |
514 | * ``EU_PER_DSS ff ff 00 00 00 00 00 00`` | |
515 | * means each DSS has 16 EU. | |
ffd6620f | 516 | */ |
dd08ebf6 MB |
517 | struct drm_xe_query_topology_mask { |
518 | /** @gt_id: GT ID the mask is associated with */ | |
519 | __u16 gt_id; | |
520 | ||
ca83f9d2 FD |
521 | #define DRM_XE_TOPO_DSS_GEOMETRY 1 |
522 | #define DRM_XE_TOPO_DSS_COMPUTE 2 | |
523 | #define DRM_XE_TOPO_EU_PER_DSS 4 | |
4f082f2c FD |
524 | /** @type: type of mask */ |
525 | __u16 type; | |
dd08ebf6 MB |
526 | |
527 | /** @num_bytes: number of bytes in requested mask */ | |
528 | __u32 num_bytes; | |
529 | ||
530 | /** @mask: little-endian mask of @num_bytes */ | |
531 | __u8 mask[]; | |
532 | }; | |
533 | ||
76ca3a22 RV |
534 | /** |
535 | * struct drm_xe_query_engine_cycles - correlate CPU and GPU timestamps | |
536 | * | |
537 | * If a query is made with a struct drm_xe_device_query where .query is equal to | |
538 | * DRM_XE_DEVICE_QUERY_ENGINE_CYCLES, then the reply uses struct drm_xe_query_engine_cycles | |
539 | * in .data. struct drm_xe_query_engine_cycles is allocated by the user and | |
540 | * .data points to this allocated structure. | |
541 | * | |
542 | * The query returns the engine cycles, which along with GT's @reference_clock, | |
543 | * can be used to calculate the engine timestamp. In addition the | |
544 | * query returns a set of cpu timestamps that indicate when the command | |
545 | * streamer cycle count was captured. | |
546 | */ | |
547 | struct drm_xe_query_engine_cycles { | |
548 | /** | |
549 | * @eci: This is input by the user and is the engine for which command | |
550 | * streamer cycles is queried. | |
551 | */ | |
552 | struct drm_xe_engine_class_instance eci; | |
553 | ||
554 | /** | |
555 | * @clockid: This is input by the user and is the reference clock id for | |
556 | * CPU timestamp. For definition, see clock_gettime(2) and | |
557 | * perf_event_open(2). Supported clock ids are CLOCK_MONOTONIC, | |
558 | * CLOCK_MONOTONIC_RAW, CLOCK_REALTIME, CLOCK_BOOTTIME, CLOCK_TAI. | |
559 | */ | |
560 | __s32 clockid; | |
561 | ||
562 | /** @width: Width of the engine cycle counter in bits. */ | |
563 | __u32 width; | |
564 | ||
565 | /** | |
566 | * @engine_cycles: Engine cycles as read from its register | |
567 | * at 0x358 offset. | |
568 | */ | |
569 | __u64 engine_cycles; | |
570 | ||
571 | /** | |
572 | * @cpu_timestamp: CPU timestamp in ns. The timestamp is captured before | |
573 | * reading the engine_cycles register using the reference clockid set by the | |
574 | * user. | |
575 | */ | |
576 | __u64 cpu_timestamp; | |
577 | ||
578 | /** | |
579 | * @cpu_delta: Time delta in ns captured around reading the lower dword | |
580 | * of the engine_cycles register. | |
581 | */ | |
582 | __u64 cpu_delta; | |
583 | }; | |
584 | ||
9bc36e58 JRS |
585 | /** |
586 | * struct drm_xe_query_uc_fw_version - query a micro-controller firmware version | |
587 | * | |
588 | * Given a uc_type this will return the branch, major, minor and patch version | |
589 | * of the micro-controller firmware. | |
590 | */ | |
591 | struct drm_xe_query_uc_fw_version { | |
592 | /** @uc_type: The micro-controller type to query firmware version */ | |
593 | #define XE_QUERY_UC_TYPE_GUC_SUBMISSION 0 | |
b2121f2b | 594 | #define XE_QUERY_UC_TYPE_HUC 1 |
9bc36e58 JRS |
595 | __u16 uc_type; |
596 | ||
597 | /** @pad: MBZ */ | |
598 | __u16 pad; | |
599 | ||
600 | /** @branch_ver: branch uc fw version */ | |
601 | __u32 branch_ver; | |
602 | /** @major_ver: major uc fw version */ | |
603 | __u32 major_ver; | |
604 | /** @minor_ver: minor uc fw version */ | |
605 | __u32 minor_ver; | |
606 | /** @patch_ver: patch uc fw version */ | |
607 | __u32 patch_ver; | |
608 | ||
609 | /** @pad2: MBZ */ | |
610 | __u32 pad2; | |
611 | ||
612 | /** @reserved: Reserved */ | |
613 | __u64 reserved; | |
614 | }; | |
615 | ||
ffd6620f | 616 | /** |
b0e47225 FD |
617 | * struct drm_xe_device_query - Input of &DRM_IOCTL_XE_DEVICE_QUERY - main |
618 | * structure to query device information | |
ffd6620f | 619 | * |
ff6c6bc5 FD |
620 | * The user selects the type of data to query among DRM_XE_DEVICE_QUERY_* |
621 | * and sets the value in the query member. This determines the type of | |
622 | * the structure provided by the driver in data, among struct drm_xe_query_*. | |
623 | * | |
801989b0 FD |
624 | * The @query can be: |
625 | * - %DRM_XE_DEVICE_QUERY_ENGINES | |
626 | * - %DRM_XE_DEVICE_QUERY_MEM_REGIONS | |
627 | * - %DRM_XE_DEVICE_QUERY_CONFIG | |
628 | * - %DRM_XE_DEVICE_QUERY_GT_LIST | |
629 | * - %DRM_XE_DEVICE_QUERY_HWCONFIG - Query type to retrieve the hardware | |
630 | * configuration of the device such as information on slices, memory, | |
631 | * caches, and so on. It is provided as a table of key / value | |
632 | * attributes. | |
633 | * - %DRM_XE_DEVICE_QUERY_GT_TOPOLOGY | |
634 | * - %DRM_XE_DEVICE_QUERY_ENGINE_CYCLES | |
635 | * | |
ff6c6bc5 FD |
636 | * If size is set to 0, the driver fills it with the required size for |
637 | * the requested type of data to query. If size is equal to the required | |
638 | * size, the queried information is copied into data. If size is set to | |
639 | * a value different from 0 and different from the required size, the | |
640 | * IOCTL call returns -EINVAL. | |
ffd6620f FD |
641 | * |
642 | * For example the following code snippet allows retrieving and printing | |
643 | * information about the device engines with DRM_XE_DEVICE_QUERY_ENGINES: | |
644 | * | |
645 | * .. code-block:: C | |
646 | * | |
60a6a849 FD |
647 | * struct drm_xe_query_engines *engines; |
648 | * struct drm_xe_device_query query = { | |
649 | * .extensions = 0, | |
650 | * .query = DRM_XE_DEVICE_QUERY_ENGINES, | |
651 | * .size = 0, | |
652 | * .data = 0, | |
653 | * }; | |
654 | * ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query); | |
655 | * engines = malloc(query.size); | |
656 | * query.data = (uintptr_t)engines; | |
657 | * ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query); | |
658 | * for (int i = 0; i < engines->num_engines; i++) { | |
659 | * printf("Engine %d: %s\n", i, | |
660 | * engines->engines[i].instance.engine_class == | |
661 | * DRM_XE_ENGINE_CLASS_RENDER ? "RENDER": | |
662 | * engines->engines[i].instance.engine_class == | |
663 | * DRM_XE_ENGINE_CLASS_COPY ? "COPY": | |
664 | * engines->engines[i].instance.engine_class == | |
665 | * DRM_XE_ENGINE_CLASS_VIDEO_DECODE ? "VIDEO_DECODE": | |
666 | * engines->engines[i].instance.engine_class == | |
667 | * DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE ? "VIDEO_ENHANCE": | |
668 | * engines->engines[i].instance.engine_class == | |
669 | * DRM_XE_ENGINE_CLASS_COMPUTE ? "COMPUTE": | |
670 | * "UNKNOWN"); | |
671 | * } | |
672 | * free(engines); | |
ffd6620f | 673 | */ |
dd08ebf6 MB |
674 | struct drm_xe_device_query { |
675 | /** @extensions: Pointer to the first extension struct, if any */ | |
676 | __u64 extensions; | |
677 | ||
7793d00d | 678 | #define DRM_XE_DEVICE_QUERY_ENGINES 0 |
b02606d3 | 679 | #define DRM_XE_DEVICE_QUERY_MEM_REGIONS 1 |
7793d00d | 680 | #define DRM_XE_DEVICE_QUERY_CONFIG 2 |
e16b4837 | 681 | #define DRM_XE_DEVICE_QUERY_GT_LIST 3 |
7793d00d UNR |
682 | #define DRM_XE_DEVICE_QUERY_HWCONFIG 4 |
683 | #define DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 5 | |
684 | #define DRM_XE_DEVICE_QUERY_ENGINE_CYCLES 6 | |
9bc36e58 | 685 | #define DRM_XE_DEVICE_QUERY_UC_FW_VERSION 7 |
4f082f2c FD |
686 | /** @query: The type of data to query */ |
687 | __u32 query; | |
dd08ebf6 MB |
688 | |
689 | /** @size: Size of the queried data */ | |
690 | __u32 size; | |
691 | ||
692 | /** @data: Queried data is placed here */ | |
693 | __u64 data; | |
694 | ||
695 | /** @reserved: Reserved */ | |
696 | __u64 reserved[2]; | |
697 | }; | |
698 | ||
b0e47225 FD |
699 | /** |
700 | * struct drm_xe_gem_create - Input of &DRM_IOCTL_XE_GEM_CREATE - A structure for | |
701 | * gem creation | |
801989b0 FD |
702 | * |
703 | * The @flags can be: | |
704 | * - %DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING | |
705 | * - %DRM_XE_GEM_CREATE_FLAG_SCANOUT | |
706 | * - %DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM - When using VRAM as a | |
707 | * possible placement, ensure that the corresponding VRAM allocation | |
708 | * will always use the CPU accessible part of VRAM. This is important | |
709 | * for small-bar systems (on full-bar systems this gets turned into a | |
710 | * noop). | |
711 | * Note1: System memory can be used as an extra placement if the kernel | |
712 | * should spill the allocation to system memory, if space can't be made | |
713 | * available in the CPU accessible part of VRAM (giving the same | |
714 | * behaviour as the i915 interface, see | |
715 | * I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS). | |
716 | * Note2: For clear-color CCS surfaces the kernel needs to read the | |
717 | * clear-color value stored in the buffer, and on discrete platforms we | |
718 | * need to use VRAM for display surfaces, therefore the kernel requires | |
719 | * setting this flag for such objects, otherwise an error is thrown on | |
720 | * small-bar systems. | |
721 | * | |
722 | * @cpu_caching supports the following values: | |
723 | * - %DRM_XE_GEM_CPU_CACHING_WB - Allocate the pages with write-back | |
724 | * caching. On iGPU this can't be used for scanout surfaces. Currently | |
725 | * not allowed for objects placed in VRAM. | |
726 | * - %DRM_XE_GEM_CPU_CACHING_WC - Allocate the pages as write-combined. This | |
727 | * is uncached. Scanout surfaces should likely use this. All objects | |
728 | * that can be placed in VRAM must use this. | |
b0e47225 | 729 | */ |
dd08ebf6 MB |
730 | struct drm_xe_gem_create { |
731 | /** @extensions: Pointer to the first extension struct, if any */ | |
732 | __u64 extensions; | |
733 | ||
734 | /** | |
4e03b584 MCC |
735 | * @size: Size of the object to be created, must match region |
736 | * (system or vram) minimum alignment (&min_page_size). | |
dd08ebf6 MB |
737 | */ |
738 | __u64 size; | |
739 | ||
535881a8 RV |
740 | /** |
741 | * @placement: A mask of memory instances of where BO can be placed. | |
742 | * Each index in this mask refers directly to the struct | |
743 | * drm_xe_query_mem_regions' instance, no assumptions should | |
744 | * be made about order. The type of each region is described | |
745 | * by struct drm_xe_query_mem_regions' mem_class. | |
746 | */ | |
6b8c1edc RV |
747 | __u32 placement; |
748 | ||
749 | #define DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING (1 << 0) | |
750 | #define DRM_XE_GEM_CREATE_FLAG_SCANOUT (1 << 1) | |
6b8c1edc | 751 | #define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM (1 << 2) |
dd08ebf6 MB |
752 | /** |
753 | * @flags: Flags, currently a mask of memory instances of where BO can | |
754 | * be placed | |
755 | */ | |
dd08ebf6 MB |
756 | __u32 flags; |
757 | ||
758 | /** | |
759 | * @vm_id: Attached VM, if any | |
760 | * | |
761 | * If a VM is specified, this BO must: | |
762 | * | |
763 | * 1. Only ever be bound to that VM. | |
dd08ebf6 MB |
764 | * 2. Cannot be exported as a PRIME fd. |
765 | */ | |
766 | __u32 vm_id; | |
767 | ||
768 | /** | |
769 | * @handle: Returned handle for the object. | |
770 | * | |
771 | * Object handles are nonzero. | |
772 | */ | |
773 | __u32 handle; | |
774 | ||
0bf90a8c FD |
775 | #define DRM_XE_GEM_CPU_CACHING_WB 1 |
776 | #define DRM_XE_GEM_CPU_CACHING_WC 2 | |
622f709c PM |
777 | /** |
778 | * @cpu_caching: The CPU caching mode to select for this object. If | |
779 | * mmaping the object the mode selected here will also be used. | |
622f709c | 780 | */ |
622f709c | 781 | __u16 cpu_caching; |
e2bd81af | 782 | /** @pad: MBZ */ |
7a56bd0c | 783 | __u16 pad[3]; |
e2bd81af | 784 | |
dd08ebf6 MB |
785 | /** @reserved: Reserved */ |
786 | __u64 reserved[2]; | |
787 | }; | |
788 | ||
b0e47225 FD |
789 | /** |
790 | * struct drm_xe_gem_mmap_offset - Input of &DRM_IOCTL_XE_GEM_MMAP_OFFSET | |
791 | */ | |
dd08ebf6 MB |
792 | struct drm_xe_gem_mmap_offset { |
793 | /** @extensions: Pointer to the first extension struct, if any */ | |
794 | __u64 extensions; | |
795 | ||
796 | /** @handle: Handle for the object being mapped. */ | |
797 | __u32 handle; | |
798 | ||
799 | /** @flags: Must be zero */ | |
800 | __u32 flags; | |
801 | ||
802 | /** @offset: The fake offset to use for subsequent mmap call */ | |
803 | __u64 offset; | |
804 | ||
805 | /** @reserved: Reserved */ | |
806 | __u64 reserved[2]; | |
807 | }; | |
808 | ||
b0e47225 FD |
809 | /** |
810 | * struct drm_xe_vm_create - Input of &DRM_IOCTL_XE_VM_CREATE | |
801989b0 FD |
811 | * |
812 | * The @flags can be: | |
813 | * - %DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE | |
814 | * - %DRM_XE_VM_CREATE_FLAG_LR_MODE - An LR, or Long Running VM accepts | |
815 | * exec submissions to its exec_queues that don't have an upper time | |
816 | * limit on the job execution time. But exec submissions to these | |
817 | * don't allow any of the flags DRM_XE_SYNC_FLAG_SYNCOBJ, | |
818 | * DRM_XE_SYNC_FLAG_TIMELINE_SYNCOBJ, DRM_XE_SYNC_FLAG_DMA_BUF, | |
819 | * used as out-syncobjs, that is, together with DRM_XE_SYNC_FLAG_SIGNAL. | |
820 | * LR VMs can be created in recoverable page-fault mode using | |
821 | * DRM_XE_VM_CREATE_FLAG_FAULT_MODE, if the device supports it. | |
822 | * If that flag is omitted, the UMD can not rely on the slightly | |
823 | * different per-VM overcommit semantics that are enabled by | |
824 | * DRM_XE_VM_CREATE_FLAG_FAULT_MODE (see below), but KMD may | |
825 | * still enable recoverable pagefaults if supported by the device. | |
826 | * - %DRM_XE_VM_CREATE_FLAG_FAULT_MODE - Requires also | |
827 | * DRM_XE_VM_CREATE_FLAG_LR_MODE. It allows memory to be allocated on | |
828 | * demand when accessed, and also allows per-VM overcommit of memory. | |
829 | * The xe driver internally uses recoverable pagefaults to implement | |
830 | * this. | |
b0e47225 | 831 | */ |
dd08ebf6 | 832 | struct drm_xe_vm_create { |
4f082f2c | 833 | /** @extensions: Pointer to the first extension struct, if any */ |
dd08ebf6 MB |
834 | __u64 extensions; |
835 | ||
9ad74351 | 836 | #define DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE (1 << 0) |
9329f066 | 837 | #define DRM_XE_VM_CREATE_FLAG_LR_MODE (1 << 1) |
d3d76739 | 838 | #define DRM_XE_VM_CREATE_FLAG_FAULT_MODE (1 << 2) |
4f082f2c FD |
839 | /** @flags: Flags */ |
840 | __u32 flags; | |
dd08ebf6 MB |
841 | |
842 | /** @vm_id: Returned VM ID */ | |
843 | __u32 vm_id; | |
844 | ||
845 | /** @reserved: Reserved */ | |
846 | __u64 reserved[2]; | |
847 | }; | |
848 | ||
b0e47225 FD |
849 | /** |
850 | * struct drm_xe_vm_destroy - Input of &DRM_IOCTL_XE_VM_DESTROY | |
851 | */ | |
dd08ebf6 MB |
852 | struct drm_xe_vm_destroy { |
853 | /** @vm_id: VM ID */ | |
854 | __u32 vm_id; | |
855 | ||
856 | /** @pad: MBZ */ | |
857 | __u32 pad; | |
858 | ||
859 | /** @reserved: Reserved */ | |
860 | __u64 reserved[2]; | |
861 | }; | |
862 | ||
b0e47225 | 863 | /** |
801989b0 FD |
864 | * struct drm_xe_vm_bind_op - run bind operations |
865 | * | |
866 | * The @op can be: | |
867 | * - %DRM_XE_VM_BIND_OP_MAP | |
868 | * - %DRM_XE_VM_BIND_OP_UNMAP | |
869 | * - %DRM_XE_VM_BIND_OP_MAP_USERPTR | |
870 | * - %DRM_XE_VM_BIND_OP_UNMAP_ALL | |
871 | * - %DRM_XE_VM_BIND_OP_PREFETCH | |
872 | * | |
873 | * and the @flags can be: | |
31ced035 FD |
874 | * - %DRM_XE_VM_BIND_FLAG_READONLY - Setup the page tables as read-only |
875 | * to ensure write protection | |
876 | * - %DRM_XE_VM_BIND_FLAG_IMMEDIATE - On a faulting VM, do the | |
877 | * MAP operation immediately rather than deferring the MAP to the page | |
878 | * fault handler. This is implied on a non-faulting VM as there is no | |
879 | * fault handler to defer to. | |
801989b0 FD |
880 | * - %DRM_XE_VM_BIND_FLAG_NULL - When the NULL flag is set, the page |
881 | * tables are setup with a special bit which indicates writes are | |
882 | * dropped and all reads return zero. In the future, the NULL flags | |
883 | * will only be valid for DRM_XE_VM_BIND_OP_MAP operations, the BO | |
884 | * handle MBZ, and the BO offset MBZ. This flag is intended to | |
885 | * implement VK sparse bindings. | |
b0e47225 | 886 | */ |
dd08ebf6 | 887 | struct drm_xe_vm_bind_op { |
c4ad3710 MK |
888 | /** @extensions: Pointer to the first extension struct, if any */ |
889 | __u64 extensions; | |
890 | ||
dd08ebf6 MB |
891 | /** |
892 | * @obj: GEM object to operate on, MBZ for MAP_USERPTR, MBZ for UNMAP | |
893 | */ | |
894 | __u32 obj; | |
895 | ||
e1fbc4f1 MA |
896 | /** |
897 | * @pat_index: The platform defined @pat_index to use for this mapping. | |
898 | * The index basically maps to some predefined memory attributes, | |
899 | * including things like caching, coherency, compression etc. The exact | |
900 | * meaning of the pat_index is platform specific and defined in the | |
901 | * Bspec and PRMs. When the KMD sets up the binding the index here is | |
902 | * encoded into the ppGTT PTE. | |
903 | * | |
904 | * For coherency the @pat_index needs to be at least 1way coherent when | |
905 | * drm_xe_gem_create.cpu_caching is DRM_XE_GEM_CPU_CACHING_WB. The KMD | |
906 | * will extract the coherency mode from the @pat_index and reject if | |
907 | * there is a mismatch (see note below for pre-MTL platforms). | |
908 | * | |
909 | * Note: On pre-MTL platforms there is only a caching mode and no | |
910 | * explicit coherency mode, but on such hardware there is always a | |
911 | * shared-LLC (or is dgpu) so all GT memory accesses are coherent with | |
912 | * CPU caches even with the caching mode set as uncached. It's only the | |
913 | * display engine that is incoherent (on dgpu it must be in VRAM which | |
914 | * is always mapped as WC on the CPU). However to keep the uapi somewhat | |
915 | * consistent with newer platforms the KMD groups the different cache | |
916 | * levels into the following coherency buckets on all pre-MTL platforms: | |
917 | * | |
918 | * ppGTT UC -> COH_NONE | |
919 | * ppGTT WC -> COH_NONE | |
920 | * ppGTT WT -> COH_NONE | |
921 | * ppGTT WB -> COH_AT_LEAST_1WAY | |
922 | * | |
923 | * In practice UC/WC/WT should only ever used for scanout surfaces on | |
924 | * such platforms (or perhaps in general for dma-buf if shared with | |
925 | * another device) since it is only the display engine that is actually | |
926 | * incoherent. Everything else should typically use WB given that we | |
927 | * have a shared-LLC. On MTL+ this completely changes and the HW | |
928 | * defines the coherency mode as part of the @pat_index, where | |
929 | * incoherent GT access is possible. | |
930 | * | |
931 | * Note: For userptr and externally imported dma-buf the kernel expects | |
932 | * either 1WAY or 2WAY for the @pat_index. | |
933 | * | |
934 | * For DRM_XE_VM_BIND_FLAG_NULL bindings there are no KMD restrictions | |
935 | * on the @pat_index. For such mappings there is no actual memory being | |
936 | * mapped (the address in the PTE is invalid), so the various PAT memory | |
937 | * attributes likely do not apply. Simply leaving as zero is one | |
938 | * option (still a valid pat_index). | |
939 | */ | |
940 | __u16 pat_index; | |
941 | ||
e2bd81af | 942 | /** @pad: MBZ */ |
e1fbc4f1 | 943 | __u16 pad; |
e2bd81af | 944 | |
dd08ebf6 MB |
945 | union { |
946 | /** | |
947 | * @obj_offset: Offset into the object, MBZ for CLEAR_RANGE, | |
948 | * ignored for unbind | |
949 | */ | |
950 | __u64 obj_offset; | |
4f082f2c | 951 | |
dd08ebf6 MB |
952 | /** @userptr: user pointer to bind on */ |
953 | __u64 userptr; | |
954 | }; | |
955 | ||
956 | /** | |
957 | * @range: Number of bytes from the object to bind to addr, MBZ for UNMAP_ALL | |
958 | */ | |
959 | __u64 range; | |
960 | ||
961 | /** @addr: Address to operate on, MBZ for UNMAP_ALL */ | |
962 | __u64 addr; | |
963 | ||
d5dc73db FD |
964 | #define DRM_XE_VM_BIND_OP_MAP 0x0 |
965 | #define DRM_XE_VM_BIND_OP_UNMAP 0x1 | |
966 | #define DRM_XE_VM_BIND_OP_MAP_USERPTR 0x2 | |
967 | #define DRM_XE_VM_BIND_OP_UNMAP_ALL 0x3 | |
968 | #define DRM_XE_VM_BIND_OP_PREFETCH 0x4 | |
ea0640fc FD |
969 | /** @op: Bind operation to perform */ |
970 | __u32 op; | |
dd08ebf6 | 971 | |
31ced035 FD |
972 | #define DRM_XE_VM_BIND_FLAG_READONLY (1 << 0) |
973 | #define DRM_XE_VM_BIND_FLAG_IMMEDIATE (1 << 1) | |
d3d76739 | 974 | #define DRM_XE_VM_BIND_FLAG_NULL (1 << 2) |
76a86b58 | 975 | #define DRM_XE_VM_BIND_FLAG_DUMPABLE (1 << 3) |
ea0640fc FD |
976 | /** @flags: Bind flags */ |
977 | __u32 flags; | |
4f082f2c | 978 | |
aaa115ff RV |
979 | /** |
980 | * @prefetch_mem_region_instance: Memory region to prefetch VMA to. | |
981 | * It is a region instance, not a mask. | |
982 | * To be used only with %DRM_XE_VM_BIND_OP_PREFETCH operation. | |
983 | */ | |
984 | __u32 prefetch_mem_region_instance; | |
dd08ebf6 | 985 | |
4efaadd3 | 986 | /** @pad2: MBZ */ |
7a56bd0c RV |
987 | __u32 pad2; |
988 | ||
dd08ebf6 | 989 | /** @reserved: Reserved */ |
cad4a0d6 | 990 | __u64 reserved[3]; |
dd08ebf6 MB |
991 | }; |
992 | ||
b0e47225 FD |
993 | /** |
994 | * struct drm_xe_vm_bind - Input of &DRM_IOCTL_XE_VM_BIND | |
db353311 FD |
995 | * |
996 | * Below is an example of a minimal use of @drm_xe_vm_bind to | |
997 | * asynchronously bind the buffer `data` at address `BIND_ADDRESS` to | |
998 | * illustrate `userptr`. It can be synchronized by using the example | |
999 | * provided for @drm_xe_sync. | |
1000 | * | |
1001 | * .. code-block:: C | |
1002 | * | |
1003 | * data = aligned_alloc(ALIGNMENT, BO_SIZE); | |
1004 | * struct drm_xe_vm_bind bind = { | |
1005 | * .vm_id = vm, | |
1006 | * .num_binds = 1, | |
1007 | * .bind.obj = 0, | |
1008 | * .bind.obj_offset = to_user_pointer(data), | |
1009 | * .bind.range = BO_SIZE, | |
1010 | * .bind.addr = BIND_ADDRESS, | |
1011 | * .bind.op = DRM_XE_VM_BIND_OP_MAP_USERPTR, | |
1012 | * .bind.flags = 0, | |
1013 | * .num_syncs = 1, | |
1014 | * .syncs = &sync, | |
1015 | * .exec_queue_id = 0, | |
1016 | * }; | |
1017 | * ioctl(fd, DRM_IOCTL_XE_VM_BIND, &bind); | |
1018 | * | |
b0e47225 | 1019 | */ |
dd08ebf6 MB |
1020 | struct drm_xe_vm_bind { |
1021 | /** @extensions: Pointer to the first extension struct, if any */ | |
1022 | __u64 extensions; | |
1023 | ||
1024 | /** @vm_id: The ID of the VM to bind to */ | |
1025 | __u32 vm_id; | |
1026 | ||
1027 | /** | |
9b9529ce FD |
1028 | * @exec_queue_id: exec_queue_id, must be of class DRM_XE_ENGINE_CLASS_VM_BIND |
1029 | * and exec queue must have same vm_id. If zero, the default VM bind engine | |
dd08ebf6 MB |
1030 | * is used. |
1031 | */ | |
9b9529ce | 1032 | __u32 exec_queue_id; |
dd08ebf6 | 1033 | |
e2bd81af CS |
1034 | /** @pad: MBZ */ |
1035 | __u32 pad; | |
1036 | ||
7a56bd0c RV |
1037 | /** @num_binds: number of binds in this IOCTL */ |
1038 | __u32 num_binds; | |
1039 | ||
dd08ebf6 MB |
1040 | union { |
1041 | /** @bind: used if num_binds == 1 */ | |
1042 | struct drm_xe_vm_bind_op bind; | |
4f082f2c | 1043 | |
dd08ebf6 MB |
1044 | /** |
1045 | * @vector_of_binds: userptr to array of struct | |
1046 | * drm_xe_vm_bind_op if num_binds > 1 | |
1047 | */ | |
1048 | __u64 vector_of_binds; | |
1049 | }; | |
1050 | ||
4efaadd3 | 1051 | /** @pad2: MBZ */ |
7a56bd0c RV |
1052 | __u32 pad2; |
1053 | ||
dd08ebf6 MB |
1054 | /** @num_syncs: amount of syncs to wait on */ |
1055 | __u32 num_syncs; | |
1056 | ||
1057 | /** @syncs: pointer to struct drm_xe_sync array */ | |
1058 | __u64 syncs; | |
1059 | ||
1060 | /** @reserved: Reserved */ | |
1061 | __u64 reserved[2]; | |
1062 | }; | |
1063 | ||
b0e47225 FD |
1064 | /** |
1065 | * struct drm_xe_exec_queue_create - Input of &DRM_IOCTL_XE_EXEC_QUEUE_CREATE | |
db353311 FD |
1066 | * |
1067 | * The example below shows how to use @drm_xe_exec_queue_create to create | |
1068 | * a simple exec_queue (no parallel submission) of class | |
1069 | * &DRM_XE_ENGINE_CLASS_RENDER. | |
1070 | * | |
1071 | * .. code-block:: C | |
1072 | * | |
1073 | * struct drm_xe_engine_class_instance instance = { | |
1074 | * .engine_class = DRM_XE_ENGINE_CLASS_RENDER, | |
1075 | * }; | |
1076 | * struct drm_xe_exec_queue_create exec_queue_create = { | |
1077 | * .extensions = 0, | |
1078 | * .vm_id = vm, | |
1079 | * .num_bb_per_exec = 1, | |
1080 | * .num_eng_per_bb = 1, | |
1081 | * .instances = to_user_pointer(&instance), | |
1082 | * }; | |
1083 | * ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_CREATE, &exec_queue_create); | |
1084 | * | |
b0e47225 | 1085 | */ |
9b9529ce | 1086 | struct drm_xe_exec_queue_create { |
0f1d88f2 RV |
1087 | #define DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY 0 |
1088 | #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY 0 | |
1089 | #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE 1 | |
0f1d88f2 | 1090 | |
4f082f2c | 1091 | /** @extensions: Pointer to the first extension struct, if any */ |
dd08ebf6 MB |
1092 | __u64 extensions; |
1093 | ||
9b9529ce | 1094 | /** @width: submission width (number BB per exec) for this exec queue */ |
dd08ebf6 MB |
1095 | __u16 width; |
1096 | ||
9b9529ce | 1097 | /** @num_placements: number of valid placements for this exec queue */ |
dd08ebf6 MB |
1098 | __u16 num_placements; |
1099 | ||
9b9529ce | 1100 | /** @vm_id: VM to use for this exec queue */ |
dd08ebf6 MB |
1101 | __u32 vm_id; |
1102 | ||
1103 | /** @flags: MBZ */ | |
1104 | __u32 flags; | |
1105 | ||
9b9529ce FD |
1106 | /** @exec_queue_id: Returned exec queue ID */ |
1107 | __u32 exec_queue_id; | |
dd08ebf6 MB |
1108 | |
1109 | /** | |
1110 | * @instances: user pointer to a 2-d array of struct | |
1111 | * drm_xe_engine_class_instance | |
1112 | * | |
1113 | * length = width (i) * num_placements (j) | |
1114 | * index = j + i * width | |
1115 | */ | |
1116 | __u64 instances; | |
1117 | ||
1118 | /** @reserved: Reserved */ | |
1119 | __u64 reserved[2]; | |
1120 | }; | |
1121 | ||
76ca3a22 RV |
1122 | /** |
1123 | * struct drm_xe_exec_queue_destroy - Input of &DRM_IOCTL_XE_EXEC_QUEUE_DESTROY | |
1124 | */ | |
1125 | struct drm_xe_exec_queue_destroy { | |
1126 | /** @exec_queue_id: Exec queue ID */ | |
1127 | __u32 exec_queue_id; | |
1128 | ||
1129 | /** @pad: MBZ */ | |
1130 | __u32 pad; | |
1131 | ||
1132 | /** @reserved: Reserved */ | |
1133 | __u64 reserved[2]; | |
1134 | }; | |
1135 | ||
b0e47225 FD |
1136 | /** |
1137 | * struct drm_xe_exec_queue_get_property - Input of &DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY | |
801989b0 FD |
1138 | * |
1139 | * The @property can be: | |
1140 | * - %DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN | |
b0e47225 | 1141 | */ |
9b9529ce | 1142 | struct drm_xe_exec_queue_get_property { |
19431b02 JRS |
1143 | /** @extensions: Pointer to the first extension struct, if any */ |
1144 | __u64 extensions; | |
1145 | ||
9b9529ce FD |
1146 | /** @exec_queue_id: Exec queue ID */ |
1147 | __u32 exec_queue_id; | |
19431b02 | 1148 | |
d5dc73db | 1149 | #define DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN 0 |
4f082f2c | 1150 | /** @property: property to get */ |
19431b02 JRS |
1151 | __u32 property; |
1152 | ||
1153 | /** @value: property value */ | |
1154 | __u64 value; | |
1155 | ||
1156 | /** @reserved: Reserved */ | |
1157 | __u64 reserved[2]; | |
1158 | }; | |
1159 | ||
b0e47225 | 1160 | /** |
801989b0 FD |
1161 | * struct drm_xe_sync - sync object |
1162 | * | |
1163 | * The @type can be: | |
1164 | * - %DRM_XE_SYNC_TYPE_SYNCOBJ | |
1165 | * - %DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ | |
1166 | * - %DRM_XE_SYNC_TYPE_USER_FENCE | |
1167 | * | |
1168 | * and the @flags can be: | |
1169 | * - %DRM_XE_SYNC_FLAG_SIGNAL | |
db353311 FD |
1170 | * |
1171 | * A minimal use of @drm_xe_sync looks like this: | |
1172 | * | |
1173 | * .. code-block:: C | |
1174 | * | |
1175 | * struct drm_xe_sync sync = { | |
1176 | * .flags = DRM_XE_SYNC_FLAG_SIGNAL, | |
1177 | * .type = DRM_XE_SYNC_TYPE_SYNCOBJ, | |
1178 | * }; | |
1179 | * struct drm_syncobj_create syncobj_create = { 0 }; | |
1180 | * ioctl(fd, DRM_IOCTL_SYNCOBJ_CREATE, &syncobj_create); | |
1181 | * sync.handle = syncobj_create.handle; | |
1182 | * ... | |
1183 | * use of &sync in drm_xe_exec or drm_xe_vm_bind | |
1184 | * ... | |
1185 | * struct drm_syncobj_wait wait = { | |
1186 | * .handles = &sync.handle, | |
1187 | * .timeout_nsec = INT64_MAX, | |
1188 | * .count_handles = 1, | |
1189 | * .flags = 0, | |
1190 | * .first_signaled = 0, | |
1191 | * .pad = 0, | |
1192 | * }; | |
1193 | * ioctl(fd, DRM_IOCTL_SYNCOBJ_WAIT, &wait); | |
b0e47225 | 1194 | */ |
dd08ebf6 MB |
1195 | struct drm_xe_sync { |
1196 | /** @extensions: Pointer to the first extension struct, if any */ | |
1197 | __u64 extensions; | |
1198 | ||
37d078e5 RV |
1199 | #define DRM_XE_SYNC_TYPE_SYNCOBJ 0x0 |
1200 | #define DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ 0x1 | |
1201 | #define DRM_XE_SYNC_TYPE_USER_FENCE 0x2 | |
1202 | /** @type: Type of the this sync object */ | |
1203 | __u32 type; | |
1204 | ||
1205 | #define DRM_XE_SYNC_FLAG_SIGNAL (1 << 0) | |
1206 | /** @flags: Sync Flags */ | |
4f082f2c | 1207 | __u32 flags; |
dd08ebf6 MB |
1208 | |
1209 | union { | |
4efaadd3 | 1210 | /** @handle: Handle for the object */ |
dd08ebf6 | 1211 | __u32 handle; |
4f082f2c | 1212 | |
dd08ebf6 | 1213 | /** |
4b437893 RV |
1214 | * @addr: Address of user fence. When sync is passed in via exec |
1215 | * IOCTL this is a GPU address in the VM. When sync passed in via | |
dd08ebf6 MB |
1216 | * VM bind IOCTL this is a user pointer. In either case, it is |
1217 | * the users responsibility that this address is present and | |
1218 | * mapped when the user fence is signalled. Must be qword | |
1219 | * aligned. | |
1220 | */ | |
1221 | __u64 addr; | |
1222 | }; | |
1223 | ||
4b437893 RV |
1224 | /** |
1225 | * @timeline_value: Input for the timeline sync object. Needs to be | |
1226 | * different than 0 when used with %DRM_XE_SYNC_FLAG_TIMELINE_SYNCOBJ. | |
1227 | */ | |
dd08ebf6 MB |
1228 | __u64 timeline_value; |
1229 | ||
1230 | /** @reserved: Reserved */ | |
1231 | __u64 reserved[2]; | |
1232 | }; | |
1233 | ||
b0e47225 FD |
1234 | /** |
1235 | * struct drm_xe_exec - Input of &DRM_IOCTL_XE_EXEC | |
db353311 FD |
1236 | * |
1237 | * This is an example to use @drm_xe_exec for execution of the object | |
1238 | * at BIND_ADDRESS (see example in @drm_xe_vm_bind) by an exec_queue | |
1239 | * (see example in @drm_xe_exec_queue_create). It can be synchronized | |
1240 | * by using the example provided for @drm_xe_sync. | |
1241 | * | |
1242 | * .. code-block:: C | |
1243 | * | |
1244 | * struct drm_xe_exec exec = { | |
1245 | * .exec_queue_id = exec_queue, | |
1246 | * .syncs = &sync, | |
1247 | * .num_syncs = 1, | |
1248 | * .address = BIND_ADDRESS, | |
1249 | * .num_batch_buffer = 1, | |
1250 | * }; | |
1251 | * ioctl(fd, DRM_IOCTL_XE_EXEC, &exec); | |
1252 | * | |
b0e47225 | 1253 | */ |
dd08ebf6 MB |
1254 | struct drm_xe_exec { |
1255 | /** @extensions: Pointer to the first extension struct, if any */ | |
1256 | __u64 extensions; | |
1257 | ||
9b9529ce FD |
1258 | /** @exec_queue_id: Exec queue ID for the batch buffer */ |
1259 | __u32 exec_queue_id; | |
dd08ebf6 MB |
1260 | |
1261 | /** @num_syncs: Amount of struct drm_xe_sync in array. */ | |
1262 | __u32 num_syncs; | |
1263 | ||
1264 | /** @syncs: Pointer to struct drm_xe_sync array. */ | |
1265 | __u64 syncs; | |
1266 | ||
1267 | /** | |
a0385a84 FD |
1268 | * @address: address of batch buffer if num_batch_buffer == 1 or an |
1269 | * array of batch buffer addresses | |
1270 | */ | |
dd08ebf6 MB |
1271 | __u64 address; |
1272 | ||
1273 | /** | |
1274 | * @num_batch_buffer: number of batch buffer in this exec, must match | |
1275 | * the width of the engine | |
1276 | */ | |
1277 | __u16 num_batch_buffer; | |
1278 | ||
e2bd81af CS |
1279 | /** @pad: MBZ */ |
1280 | __u16 pad[3]; | |
1281 | ||
dd08ebf6 MB |
1282 | /** @reserved: Reserved */ |
1283 | __u64 reserved[2]; | |
1284 | }; | |
1285 | ||
dd08ebf6 | 1286 | /** |
b0e47225 | 1287 | * struct drm_xe_wait_user_fence - Input of &DRM_IOCTL_XE_WAIT_USER_FENCE |
dd08ebf6 | 1288 | * |
2793fac1 | 1289 | * Wait on user fence, XE will wake-up on every HW engine interrupt in the |
63f9c3cd MA |
1290 | * instances list and check if user fence is complete:: |
1291 | * | |
1292 | * (*addr & MASK) OP (VALUE & MASK) | |
dd08ebf6 MB |
1293 | * |
1294 | * Returns to user on user fence completion or timeout. | |
801989b0 FD |
1295 | * |
1296 | * The @op can be: | |
1297 | * - %DRM_XE_UFENCE_WAIT_OP_EQ | |
1298 | * - %DRM_XE_UFENCE_WAIT_OP_NEQ | |
1299 | * - %DRM_XE_UFENCE_WAIT_OP_GT | |
1300 | * - %DRM_XE_UFENCE_WAIT_OP_GTE | |
1301 | * - %DRM_XE_UFENCE_WAIT_OP_LT | |
1302 | * - %DRM_XE_UFENCE_WAIT_OP_LTE | |
1303 | * | |
1304 | * and the @flags can be: | |
1305 | * - %DRM_XE_UFENCE_WAIT_FLAG_ABSTIME | |
1306 | * - %DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP | |
1307 | * | |
1308 | * The @mask values can be for example: | |
1309 | * - 0xffu for u8 | |
1310 | * - 0xffffu for u16 | |
1311 | * - 0xffffffffu for u32 | |
1312 | * - 0xffffffffffffffffu for u64 | |
dd08ebf6 MB |
1313 | */ |
1314 | struct drm_xe_wait_user_fence { | |
1315 | /** @extensions: Pointer to the first extension struct, if any */ | |
1316 | __u64 extensions; | |
4f082f2c | 1317 | |
b21ae51d MB |
1318 | /** |
1319 | * @addr: user pointer address to wait on, must qword aligned | |
1320 | */ | |
1321 | __u64 addr; | |
4f082f2c | 1322 | |
4a349c86 RV |
1323 | #define DRM_XE_UFENCE_WAIT_OP_EQ 0x0 |
1324 | #define DRM_XE_UFENCE_WAIT_OP_NEQ 0x1 | |
1325 | #define DRM_XE_UFENCE_WAIT_OP_GT 0x2 | |
1326 | #define DRM_XE_UFENCE_WAIT_OP_GTE 0x3 | |
1327 | #define DRM_XE_UFENCE_WAIT_OP_LT 0x4 | |
1328 | #define DRM_XE_UFENCE_WAIT_OP_LTE 0x5 | |
4f082f2c | 1329 | /** @op: wait operation (type of comparison) */ |
dd08ebf6 | 1330 | __u16 op; |
4f082f2c | 1331 | |
9212da07 | 1332 | #define DRM_XE_UFENCE_WAIT_FLAG_ABSTIME (1 << 0) |
4f082f2c | 1333 | /** @flags: wait flags */ |
dd08ebf6 | 1334 | __u16 flags; |
4f082f2c | 1335 | |
e2bd81af CS |
1336 | /** @pad: MBZ */ |
1337 | __u32 pad; | |
4f082f2c | 1338 | |
dd08ebf6 MB |
1339 | /** @value: compare value */ |
1340 | __u64 value; | |
4f082f2c | 1341 | |
801989b0 | 1342 | /** @mask: comparison mask */ |
dd08ebf6 | 1343 | __u64 mask; |
4a349c86 | 1344 | |
5572a004 ZK |
1345 | /** |
1346 | * @timeout: how long to wait before bailing, value in nanoseconds. | |
3ac4a789 | 1347 | * Without DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flag set (relative timeout) |
5572a004 ZK |
1348 | * it contains timeout expressed in nanoseconds to wait (fence will |
1349 | * expire at now() + timeout). | |
3ac4a789 | 1350 | * When DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flat is set (absolute timeout) wait |
5572a004 ZK |
1351 | * will end at timeout (uses system MONOTONIC_CLOCK). |
1352 | * Passing negative timeout leads to neverending wait. | |
1353 | * | |
1354 | * On relative timeout this value is updated with timeout left | |
1355 | * (for restarting the call in case of signal delivery). | |
1356 | * On absolute timeout this value stays intact (restarted call still | |
1357 | * expire at the same point of time). | |
1358 | */ | |
dd08ebf6 | 1359 | __s64 timeout; |
4f082f2c | 1360 | |
9212da07 BK |
1361 | /** @exec_queue_id: exec_queue_id returned from xe_exec_queue_create_ioctl */ |
1362 | __u32 exec_queue_id; | |
4f082f2c | 1363 | |
9212da07 BK |
1364 | /** @pad2: MBZ */ |
1365 | __u32 pad2; | |
dd08ebf6 MB |
1366 | |
1367 | /** @reserved: Reserved */ | |
1368 | __u64 reserved[2]; | |
1369 | }; | |
76ca3a22 | 1370 | |
dd08ebf6 MB |
1371 | #if defined(__cplusplus) |
1372 | } | |
1373 | #endif | |
1374 | ||
1375 | #endif /* _UAPI_XE_DRM_H_ */ |