Commit | Line | Data |
---|---|---|
81629cba AD |
1 | /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- |
2 | * | |
3 | * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. | |
4 | * Copyright 2000 VA Linux Systems, Inc., Fremont, California. | |
5 | * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. | |
6 | * Copyright 2014 Advanced Micro Devices, Inc. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the "Software"), | |
10 | * to deal in the Software without restriction, including without limitation | |
11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
12 | * and/or sell copies of the Software, and to permit persons to whom the | |
13 | * Software is furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
22 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
23 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
24 | * OTHER DEALINGS IN THE SOFTWARE. | |
25 | * | |
26 | * Authors: | |
27 | * Kevin E. Martin <martin@valinux.com> | |
28 | * Gareth Hughes <gareth@valinux.com> | |
29 | * Keith Whitwell <keith@tungstengraphics.com> | |
30 | */ | |
31 | ||
32 | #ifndef __AMDGPU_DRM_H__ | |
33 | #define __AMDGPU_DRM_H__ | |
34 | ||
b3fcf36a | 35 | #include "drm.h" |
81629cba | 36 | |
cfa7152f EV |
37 | #if defined(__cplusplus) |
38 | extern "C" { | |
39 | #endif | |
40 | ||
81629cba AD |
41 | #define DRM_AMDGPU_GEM_CREATE 0x00 |
42 | #define DRM_AMDGPU_GEM_MMAP 0x01 | |
43 | #define DRM_AMDGPU_CTX 0x02 | |
44 | #define DRM_AMDGPU_BO_LIST 0x03 | |
45 | #define DRM_AMDGPU_CS 0x04 | |
46 | #define DRM_AMDGPU_INFO 0x05 | |
47 | #define DRM_AMDGPU_GEM_METADATA 0x06 | |
48 | #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 | |
49 | #define DRM_AMDGPU_GEM_VA 0x08 | |
50 | #define DRM_AMDGPU_WAIT_CS 0x09 | |
51 | #define DRM_AMDGPU_GEM_OP 0x10 | |
52 | #define DRM_AMDGPU_GEM_USERPTR 0x11 | |
eef18a82 | 53 | #define DRM_AMDGPU_WAIT_FENCES 0x12 |
cfbcacf4 | 54 | #define DRM_AMDGPU_VM 0x13 |
7ca24cf2 | 55 | #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 |
52c6a62c | 56 | #define DRM_AMDGPU_SCHED 0x15 |
81629cba AD |
57 | |
58 | #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) | |
59 | #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) | |
60 | #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) | |
61 | #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) | |
62 | #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) | |
63 | #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) | |
64 | #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) | |
65 | #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) | |
34b5f6a6 | 66 | #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) |
81629cba AD |
67 | #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) |
68 | #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) | |
69 | #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) | |
eef18a82 | 70 | #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) |
cfbcacf4 | 71 | #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) |
7ca24cf2 | 72 | #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) |
52c6a62c | 73 | #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) |
81629cba | 74 | |
b646c1dc SL |
75 | /** |
76 | * DOC: memory domains | |
77 | * | |
78 | * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible. | |
79 | * Memory in this pool could be swapped out to disk if there is pressure. | |
80 | * | |
81 | * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the | |
82 | * GPU's virtual address space via gart. Gart memory linearizes non-contiguous | |
326db0dc | 83 | * pages of system memory, allows GPU access system memory in a linearized |
b646c1dc SL |
84 | * fashion. |
85 | * | |
86 | * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory | |
87 | * carved out by the BIOS. | |
88 | * | |
89 | * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data | |
90 | * across shader threads. | |
91 | * | |
92 | * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the | |
93 | * execution of all the waves on a device. | |
94 | * | |
95 | * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines | |
96 | * for appending data. | |
89927235 AD |
97 | * |
98 | * %AMDGPU_GEM_DOMAIN_DOORBELL Doorbell. It is an MMIO region for | |
99 | * signalling user mode queues. | |
b646c1dc | 100 | */ |
81629cba AD |
101 | #define AMDGPU_GEM_DOMAIN_CPU 0x1 |
102 | #define AMDGPU_GEM_DOMAIN_GTT 0x2 | |
103 | #define AMDGPU_GEM_DOMAIN_VRAM 0x4 | |
104 | #define AMDGPU_GEM_DOMAIN_GDS 0x8 | |
105 | #define AMDGPU_GEM_DOMAIN_GWS 0x10 | |
106 | #define AMDGPU_GEM_DOMAIN_OA 0x20 | |
89927235 | 107 | #define AMDGPU_GEM_DOMAIN_DOORBELL 0x40 |
3f188453 CZ |
108 | #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ |
109 | AMDGPU_GEM_DOMAIN_GTT | \ | |
110 | AMDGPU_GEM_DOMAIN_VRAM | \ | |
111 | AMDGPU_GEM_DOMAIN_GDS | \ | |
112 | AMDGPU_GEM_DOMAIN_GWS | \ | |
89927235 AD |
113 | AMDGPU_GEM_DOMAIN_OA | \ |
114 | AMDGPU_GEM_DOMAIN_DOORBELL) | |
81629cba | 115 | |
81629cba AD |
116 | /* Flag that CPU access will be required for the case of VRAM domain */ |
117 | #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) | |
118 | /* Flag that CPU access will not work, this VRAM domain is invisible */ | |
119 | #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) | |
81629cba | 120 | /* Flag that USWC attributes should be used for GTT */ |
88671288 | 121 | #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) |
4fea83ff FC |
122 | /* Flag that the memory should be in VRAM and cleared */ |
123 | #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) | |
03f48dd5 CK |
124 | /* Flag that allocating the BO should use linear VRAM */ |
125 | #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) | |
e1eb899b CK |
126 | /* Flag that BO is always valid in this VM */ |
127 | #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) | |
177ae09b AR |
128 | /* Flag that BO sharing will be explicitly synchronized */ |
129 | #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) | |
959a2091 | 130 | /* Flag that indicates allocating MQD gart on GFX9, where the mtype |
fa5bde80 YZ |
131 | * for the second page onward should be set to NC. It should never |
132 | * be used by user space applications. | |
959a2091 | 133 | */ |
fa5bde80 | 134 | #define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8) |
d8f4981e FK |
135 | /* Flag that BO may contain sensitive data that must be wiped before |
136 | * releasing the memory | |
137 | */ | |
138 | #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9) | |
35ce0060 AD |
139 | /* Flag that BO will be encrypted and that the TMZ bit should be |
140 | * set in the PTEs when mapping this buffer via GPUVM or | |
141 | * accessing it with various hw blocks | |
142 | */ | |
143 | #define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10) | |
b453e42a FK |
144 | /* Flag that BO will be used only in preemptible context, which does |
145 | * not require GTT memory accounting | |
146 | */ | |
147 | #define AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11) | |
fab2cc83 CK |
148 | /* Flag that BO can be discarded under memory pressure without keeping the |
149 | * content. | |
150 | */ | |
151 | #define AMDGPU_GEM_CREATE_DISCARDABLE (1 << 12) | |
d1a372af | 152 | /* Flag that BO is shared coherently between multiple devices or CPU threads. |
5f248462 | 153 | * May depend on GPU instructions to flush caches to system scope explicitly. |
d1a372af FK |
154 | * |
155 | * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and | |
156 | * may override the MTYPE selected in AMDGPU_VA_OP_MAP. | |
157 | */ | |
158 | #define AMDGPU_GEM_CREATE_COHERENT (1 << 13) | |
159 | /* Flag that BO should not be cached by GPU. Coherent without having to flush | |
160 | * GPU caches explicitly | |
161 | * | |
162 | * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and | |
163 | * may override the MTYPE selected in AMDGPU_VA_OP_MAP. | |
164 | */ | |
165 | #define AMDGPU_GEM_CREATE_UNCACHED (1 << 14) | |
5f248462 DF |
166 | /* Flag that BO should be coherent across devices when using device-level |
167 | * atomics. May depend on GPU instructions to flush caches to device scope | |
168 | * explicitly, promoting them to system scope automatically. | |
169 | * | |
170 | * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and | |
171 | * may override the MTYPE selected in AMDGPU_VA_OP_MAP. | |
172 | */ | |
173 | #define AMDGPU_GEM_CREATE_EXT_COHERENT (1 << 15) | |
81629cba | 174 | |
81629cba AD |
175 | struct drm_amdgpu_gem_create_in { |
176 | /** the requested memory size */ | |
2ce9dde0 | 177 | __u64 bo_size; |
81629cba | 178 | /** physical start_addr alignment in bytes for some HW requirements */ |
2ce9dde0 | 179 | __u64 alignment; |
81629cba | 180 | /** the requested memory domains */ |
2ce9dde0 | 181 | __u64 domains; |
81629cba | 182 | /** allocation flags */ |
2ce9dde0 | 183 | __u64 domain_flags; |
81629cba AD |
184 | }; |
185 | ||
186 | struct drm_amdgpu_gem_create_out { | |
187 | /** returned GEM object handle */ | |
2ce9dde0 MR |
188 | __u32 handle; |
189 | __u32 _pad; | |
81629cba AD |
190 | }; |
191 | ||
192 | union drm_amdgpu_gem_create { | |
193 | struct drm_amdgpu_gem_create_in in; | |
194 | struct drm_amdgpu_gem_create_out out; | |
195 | }; | |
196 | ||
197 | /** Opcode to create new residency list. */ | |
198 | #define AMDGPU_BO_LIST_OP_CREATE 0 | |
199 | /** Opcode to destroy previously created residency list */ | |
200 | #define AMDGPU_BO_LIST_OP_DESTROY 1 | |
201 | /** Opcode to update resource information in the list */ | |
202 | #define AMDGPU_BO_LIST_OP_UPDATE 2 | |
203 | ||
204 | struct drm_amdgpu_bo_list_in { | |
205 | /** Type of operation */ | |
2ce9dde0 | 206 | __u32 operation; |
81629cba | 207 | /** Handle of list or 0 if we want to create one */ |
2ce9dde0 | 208 | __u32 list_handle; |
81629cba | 209 | /** Number of BOs in list */ |
2ce9dde0 | 210 | __u32 bo_number; |
81629cba | 211 | /** Size of each element describing BO */ |
2ce9dde0 | 212 | __u32 bo_info_size; |
81629cba | 213 | /** Pointer to array describing BOs */ |
2ce9dde0 | 214 | __u64 bo_info_ptr; |
81629cba AD |
215 | }; |
216 | ||
217 | struct drm_amdgpu_bo_list_entry { | |
218 | /** Handle of BO */ | |
2ce9dde0 | 219 | __u32 bo_handle; |
81629cba | 220 | /** New (if specified) BO priority to be used during migration */ |
2ce9dde0 | 221 | __u32 bo_priority; |
81629cba AD |
222 | }; |
223 | ||
224 | struct drm_amdgpu_bo_list_out { | |
225 | /** Handle of resource list */ | |
2ce9dde0 MR |
226 | __u32 list_handle; |
227 | __u32 _pad; | |
81629cba AD |
228 | }; |
229 | ||
230 | union drm_amdgpu_bo_list { | |
231 | struct drm_amdgpu_bo_list_in in; | |
232 | struct drm_amdgpu_bo_list_out out; | |
233 | }; | |
234 | ||
235 | /* context related */ | |
236 | #define AMDGPU_CTX_OP_ALLOC_CTX 1 | |
237 | #define AMDGPU_CTX_OP_FREE_CTX 2 | |
238 | #define AMDGPU_CTX_OP_QUERY_STATE 3 | |
bc1b1bf6 | 239 | #define AMDGPU_CTX_OP_QUERY_STATE2 4 |
8cda7a4f AD |
240 | #define AMDGPU_CTX_OP_GET_STABLE_PSTATE 5 |
241 | #define AMDGPU_CTX_OP_SET_STABLE_PSTATE 6 | |
81629cba | 242 | |
d94aed5a MO |
243 | /* GPU reset status */ |
244 | #define AMDGPU_CTX_NO_RESET 0 | |
675da0dd CK |
245 | /* this the context caused it */ |
246 | #define AMDGPU_CTX_GUILTY_RESET 1 | |
247 | /* some other context caused it */ | |
248 | #define AMDGPU_CTX_INNOCENT_RESET 2 | |
249 | /* unknown cause */ | |
250 | #define AMDGPU_CTX_UNKNOWN_RESET 3 | |
d94aed5a | 251 | |
0029e4d4 | 252 | /* indicate gpu reset occurred after ctx created */ |
bc1b1bf6 | 253 | #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) |
0029e4d4 | 254 | /* indicate vram lost occurred after ctx created */ |
bc1b1bf6 ML |
255 | #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) |
256 | /* indicate some job from this context once cause gpu hang */ | |
257 | #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) | |
ae363a21 | 258 | /* indicate some errors are detected by RAS */ |
259 | #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3) | |
260 | #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4) | |
489763af PEPP |
261 | /* indicate that the reset hasn't completed yet */ |
262 | #define AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS (1<<5) | |
bc1b1bf6 | 263 | |
c2636dc5 | 264 | /* Context priority level */ |
f3d19bf8 | 265 | #define AMDGPU_CTX_PRIORITY_UNSET -2048 |
8bc4c256 AR |
266 | #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 |
267 | #define AMDGPU_CTX_PRIORITY_LOW -512 | |
c2636dc5 | 268 | #define AMDGPU_CTX_PRIORITY_NORMAL 0 |
cf034477 EV |
269 | /* |
270 | * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires | |
271 | * CAP_SYS_NICE or DRM_MASTER | |
272 | */ | |
8bc4c256 AR |
273 | #define AMDGPU_CTX_PRIORITY_HIGH 512 |
274 | #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 | |
c2636dc5 | 275 | |
8cda7a4f AD |
276 | /* select a stable profiling pstate for perfmon tools */ |
277 | #define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf | |
278 | #define AMDGPU_CTX_STABLE_PSTATE_NONE 0 | |
279 | #define AMDGPU_CTX_STABLE_PSTATE_STANDARD 1 | |
280 | #define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2 | |
281 | #define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3 | |
282 | #define AMDGPU_CTX_STABLE_PSTATE_PEAK 4 | |
283 | ||
81629cba | 284 | struct drm_amdgpu_ctx_in { |
675da0dd | 285 | /** AMDGPU_CTX_OP_* */ |
2ce9dde0 | 286 | __u32 op; |
8cda7a4f | 287 | /** Flags */ |
2ce9dde0 MR |
288 | __u32 flags; |
289 | __u32 ctx_id; | |
cf034477 | 290 | /** AMDGPU_CTX_PRIORITY_* */ |
c2636dc5 | 291 | __s32 priority; |
81629cba AD |
292 | }; |
293 | ||
294 | union drm_amdgpu_ctx_out { | |
295 | struct { | |
2ce9dde0 MR |
296 | __u32 ctx_id; |
297 | __u32 _pad; | |
81629cba AD |
298 | } alloc; |
299 | ||
300 | struct { | |
675da0dd | 301 | /** For future use, no flags defined so far */ |
2ce9dde0 | 302 | __u64 flags; |
d94aed5a | 303 | /** Number of resets caused by this context so far. */ |
2ce9dde0 | 304 | __u32 hangs; |
d94aed5a | 305 | /** Reset status since the last call of the ioctl. */ |
2ce9dde0 | 306 | __u32 reset_status; |
81629cba | 307 | } state; |
8cda7a4f AD |
308 | |
309 | struct { | |
310 | __u32 flags; | |
311 | __u32 _pad; | |
312 | } pstate; | |
81629cba AD |
313 | }; |
314 | ||
315 | union drm_amdgpu_ctx { | |
316 | struct drm_amdgpu_ctx_in in; | |
317 | union drm_amdgpu_ctx_out out; | |
318 | }; | |
319 | ||
cfbcacf4 CZ |
320 | /* vm ioctl */ |
321 | #define AMDGPU_VM_OP_RESERVE_VMID 1 | |
322 | #define AMDGPU_VM_OP_UNRESERVE_VMID 2 | |
323 | ||
324 | struct drm_amdgpu_vm_in { | |
325 | /** AMDGPU_VM_OP_* */ | |
326 | __u32 op; | |
327 | __u32 flags; | |
328 | }; | |
329 | ||
330 | struct drm_amdgpu_vm_out { | |
331 | /** For future use, no flags defined so far */ | |
332 | __u64 flags; | |
333 | }; | |
334 | ||
335 | union drm_amdgpu_vm { | |
336 | struct drm_amdgpu_vm_in in; | |
337 | struct drm_amdgpu_vm_out out; | |
338 | }; | |
339 | ||
52c6a62c AR |
340 | /* sched ioctl */ |
341 | #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 | |
b5bb37ed | 342 | #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 |
52c6a62c AR |
343 | |
344 | struct drm_amdgpu_sched_in { | |
345 | /* AMDGPU_SCHED_OP_* */ | |
346 | __u32 op; | |
347 | __u32 fd; | |
cf034477 | 348 | /** AMDGPU_CTX_PRIORITY_* */ |
52c6a62c | 349 | __s32 priority; |
b5bb37ed | 350 | __u32 ctx_id; |
52c6a62c AR |
351 | }; |
352 | ||
353 | union drm_amdgpu_sched { | |
354 | struct drm_amdgpu_sched_in in; | |
355 | }; | |
356 | ||
81629cba AD |
357 | /* |
358 | * This is not a reliable API and you should expect it to fail for any | |
359 | * number of reasons and have fallback path that do not use userptr to | |
360 | * perform any operation. | |
361 | */ | |
362 | #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) | |
363 | #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) | |
364 | #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) | |
365 | #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) | |
366 | ||
367 | struct drm_amdgpu_gem_userptr { | |
2ce9dde0 MR |
368 | __u64 addr; |
369 | __u64 size; | |
675da0dd | 370 | /* AMDGPU_GEM_USERPTR_* */ |
2ce9dde0 | 371 | __u32 flags; |
675da0dd | 372 | /* Resulting GEM handle */ |
2ce9dde0 | 373 | __u32 handle; |
81629cba AD |
374 | }; |
375 | ||
00ac6f6b | 376 | /* SI-CI-VI: */ |
fbd76d59 MO |
377 | /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ |
378 | #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 | |
379 | #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf | |
380 | #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 | |
381 | #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f | |
382 | #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 | |
383 | #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 | |
384 | #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 | |
385 | #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 | |
386 | #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 | |
387 | #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 | |
388 | #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 | |
389 | #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 | |
390 | #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 | |
391 | #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 | |
392 | #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 | |
393 | #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 | |
394 | ||
00ac6f6b AD |
395 | /* GFX9 and later: */ |
396 | #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 | |
397 | #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f | |
ce331f8f NK |
398 | #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 |
399 | #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF | |
400 | #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 | |
401 | #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF | |
402 | #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 | |
403 | #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 | |
c5705372 MO |
404 | #define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44 |
405 | #define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1 | |
406 | #define AMDGPU_TILING_SCANOUT_SHIFT 63 | |
407 | #define AMDGPU_TILING_SCANOUT_MASK 0x1 | |
00ac6f6b AD |
408 | |
409 | /* Set/Get helpers for tiling flags. */ | |
fbd76d59 | 410 | #define AMDGPU_TILING_SET(field, value) \ |
00ac6f6b | 411 | (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) |
fbd76d59 | 412 | #define AMDGPU_TILING_GET(value, field) \ |
00ac6f6b | 413 | (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) |
81629cba AD |
414 | |
415 | #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 | |
416 | #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 | |
417 | ||
418 | /** The same structure is shared for input/output */ | |
419 | struct drm_amdgpu_gem_metadata { | |
675da0dd | 420 | /** GEM Object handle */ |
2ce9dde0 | 421 | __u32 handle; |
675da0dd | 422 | /** Do we want get or set metadata */ |
2ce9dde0 | 423 | __u32 op; |
81629cba | 424 | struct { |
675da0dd | 425 | /** For future use, no flags defined so far */ |
2ce9dde0 | 426 | __u64 flags; |
675da0dd | 427 | /** family specific tiling info */ |
2ce9dde0 MR |
428 | __u64 tiling_info; |
429 | __u32 data_size_bytes; | |
430 | __u32 data[64]; | |
81629cba AD |
431 | } data; |
432 | }; | |
433 | ||
434 | struct drm_amdgpu_gem_mmap_in { | |
675da0dd | 435 | /** the GEM object handle */ |
2ce9dde0 MR |
436 | __u32 handle; |
437 | __u32 _pad; | |
81629cba AD |
438 | }; |
439 | ||
440 | struct drm_amdgpu_gem_mmap_out { | |
675da0dd | 441 | /** mmap offset from the vma offset manager */ |
2ce9dde0 | 442 | __u64 addr_ptr; |
81629cba AD |
443 | }; |
444 | ||
445 | union drm_amdgpu_gem_mmap { | |
446 | struct drm_amdgpu_gem_mmap_in in; | |
447 | struct drm_amdgpu_gem_mmap_out out; | |
448 | }; | |
449 | ||
450 | struct drm_amdgpu_gem_wait_idle_in { | |
675da0dd | 451 | /** GEM object handle */ |
2ce9dde0 | 452 | __u32 handle; |
675da0dd | 453 | /** For future use, no flags defined so far */ |
2ce9dde0 | 454 | __u32 flags; |
675da0dd | 455 | /** Absolute timeout to wait */ |
2ce9dde0 | 456 | __u64 timeout; |
81629cba AD |
457 | }; |
458 | ||
459 | struct drm_amdgpu_gem_wait_idle_out { | |
675da0dd | 460 | /** BO status: 0 - BO is idle, 1 - BO is busy */ |
2ce9dde0 | 461 | __u32 status; |
675da0dd | 462 | /** Returned current memory domain */ |
2ce9dde0 | 463 | __u32 domain; |
81629cba AD |
464 | }; |
465 | ||
466 | union drm_amdgpu_gem_wait_idle { | |
467 | struct drm_amdgpu_gem_wait_idle_in in; | |
468 | struct drm_amdgpu_gem_wait_idle_out out; | |
469 | }; | |
470 | ||
471 | struct drm_amdgpu_wait_cs_in { | |
d7b1eeb2 ML |
472 | /* Command submission handle |
473 | * handle equals 0 means none to wait for | |
080b24eb | 474 | * handle equals ~0ull means wait for the latest sequence number |
d7b1eeb2 | 475 | */ |
2ce9dde0 | 476 | __u64 handle; |
675da0dd | 477 | /** Absolute timeout to wait */ |
2ce9dde0 MR |
478 | __u64 timeout; |
479 | __u32 ip_type; | |
480 | __u32 ip_instance; | |
481 | __u32 ring; | |
482 | __u32 ctx_id; | |
81629cba AD |
483 | }; |
484 | ||
485 | struct drm_amdgpu_wait_cs_out { | |
675da0dd | 486 | /** CS status: 0 - CS completed, 1 - CS still busy */ |
2ce9dde0 | 487 | __u64 status; |
81629cba AD |
488 | }; |
489 | ||
490 | union drm_amdgpu_wait_cs { | |
491 | struct drm_amdgpu_wait_cs_in in; | |
492 | struct drm_amdgpu_wait_cs_out out; | |
493 | }; | |
494 | ||
eef18a82 JZ |
495 | struct drm_amdgpu_fence { |
496 | __u32 ctx_id; | |
497 | __u32 ip_type; | |
498 | __u32 ip_instance; | |
499 | __u32 ring; | |
500 | __u64 seq_no; | |
501 | }; | |
502 | ||
503 | struct drm_amdgpu_wait_fences_in { | |
504 | /** This points to uint64_t * which points to fences */ | |
505 | __u64 fences; | |
506 | __u32 fence_count; | |
507 | __u32 wait_all; | |
508 | __u64 timeout_ns; | |
509 | }; | |
510 | ||
511 | struct drm_amdgpu_wait_fences_out { | |
512 | __u32 status; | |
513 | __u32 first_signaled; | |
514 | }; | |
515 | ||
516 | union drm_amdgpu_wait_fences { | |
517 | struct drm_amdgpu_wait_fences_in in; | |
518 | struct drm_amdgpu_wait_fences_out out; | |
519 | }; | |
520 | ||
675da0dd CK |
521 | #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 |
522 | #define AMDGPU_GEM_OP_SET_PLACEMENT 1 | |
523 | ||
81629cba AD |
524 | /* Sets or returns a value associated with a buffer. */ |
525 | struct drm_amdgpu_gem_op { | |
675da0dd | 526 | /** GEM object handle */ |
2ce9dde0 | 527 | __u32 handle; |
675da0dd | 528 | /** AMDGPU_GEM_OP_* */ |
2ce9dde0 | 529 | __u32 op; |
675da0dd | 530 | /** Input or return value */ |
2ce9dde0 | 531 | __u64 value; |
81629cba AD |
532 | }; |
533 | ||
81629cba AD |
534 | #define AMDGPU_VA_OP_MAP 1 |
535 | #define AMDGPU_VA_OP_UNMAP 2 | |
dc54d3d1 | 536 | #define AMDGPU_VA_OP_CLEAR 3 |
80f95c57 | 537 | #define AMDGPU_VA_OP_REPLACE 4 |
81629cba | 538 | |
fc220f65 CK |
539 | /* Delay the page table update till the next CS */ |
540 | #define AMDGPU_VM_DELAY_UPDATE (1 << 0) | |
541 | ||
81629cba AD |
542 | /* Mapping flags */ |
543 | /* readable mapping */ | |
544 | #define AMDGPU_VM_PAGE_READABLE (1 << 1) | |
545 | /* writable mapping */ | |
546 | #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) | |
547 | /* executable mapping, new for VI */ | |
548 | #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) | |
b85891bd JZ |
549 | /* partially resident texture */ |
550 | #define AMDGPU_VM_PAGE_PRT (1 << 4) | |
66e02bc3 AX |
551 | /* MTYPE flags use bit 5 to 8 */ |
552 | #define AMDGPU_VM_MTYPE_MASK (0xf << 5) | |
553 | /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ | |
554 | #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) | |
130c8893 | 555 | /* Use Non Coherent MTYPE instead of default MTYPE */ |
66e02bc3 | 556 | #define AMDGPU_VM_MTYPE_NC (1 << 5) |
130c8893 | 557 | /* Use Write Combine MTYPE instead of default MTYPE */ |
66e02bc3 | 558 | #define AMDGPU_VM_MTYPE_WC (2 << 5) |
130c8893 | 559 | /* Use Cache Coherent MTYPE instead of default MTYPE */ |
66e02bc3 | 560 | #define AMDGPU_VM_MTYPE_CC (3 << 5) |
130c8893 | 561 | /* Use UnCached MTYPE instead of default MTYPE */ |
66e02bc3 | 562 | #define AMDGPU_VM_MTYPE_UC (4 << 5) |
130c8893 | 563 | /* Use Read Write MTYPE instead of default MTYPE */ |
484deaed | 564 | #define AMDGPU_VM_MTYPE_RW (5 << 5) |
b6c65a2c CK |
565 | /* don't allocate MALL */ |
566 | #define AMDGPU_VM_PAGE_NOALLOC (1 << 9) | |
81629cba | 567 | |
34b5f6a6 | 568 | struct drm_amdgpu_gem_va { |
675da0dd | 569 | /** GEM object handle */ |
2ce9dde0 MR |
570 | __u32 handle; |
571 | __u32 _pad; | |
675da0dd | 572 | /** AMDGPU_VA_OP_* */ |
2ce9dde0 | 573 | __u32 operation; |
675da0dd | 574 | /** AMDGPU_VM_PAGE_* */ |
2ce9dde0 | 575 | __u32 flags; |
675da0dd | 576 | /** va address to assign . Must be correctly aligned.*/ |
2ce9dde0 | 577 | __u64 va_address; |
675da0dd | 578 | /** Specify offset inside of BO to assign. Must be correctly aligned.*/ |
2ce9dde0 | 579 | __u64 offset_in_bo; |
675da0dd | 580 | /** Specify mapping size. Must be correctly aligned. */ |
2ce9dde0 | 581 | __u64 map_size; |
81629cba AD |
582 | }; |
583 | ||
81629cba AD |
584 | #define AMDGPU_HW_IP_GFX 0 |
585 | #define AMDGPU_HW_IP_COMPUTE 1 | |
586 | #define AMDGPU_HW_IP_DMA 2 | |
587 | #define AMDGPU_HW_IP_UVD 3 | |
588 | #define AMDGPU_HW_IP_VCE 4 | |
a50798b6 | 589 | #define AMDGPU_HW_IP_UVD_ENC 5 |
66e236f1 | 590 | #define AMDGPU_HW_IP_VCN_DEC 6 |
4528c186 RD |
591 | /* |
592 | * From VCN4, AMDGPU_HW_IP_VCN_ENC is re-used to support | |
593 | * both encoding and decoding jobs. | |
594 | */ | |
fcfc5a90 | 595 | #define AMDGPU_HW_IP_VCN_ENC 7 |
81d35014 | 596 | #define AMDGPU_HW_IP_VCN_JPEG 8 |
f6523900 HR |
597 | #define AMDGPU_HW_IP_VPE 9 |
598 | #define AMDGPU_HW_IP_NUM 10 | |
81629cba AD |
599 | |
600 | #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 | |
601 | ||
602 | #define AMDGPU_CHUNK_ID_IB 0x01 | |
603 | #define AMDGPU_CHUNK_ID_FENCE 0x02 | |
2b48d323 | 604 | #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 |
660e8558 DA |
605 | #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 |
606 | #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 | |
964d0fbf | 607 | #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 |
67dd1a36 | 608 | #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 |
2624dd15 CZ |
609 | #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 |
610 | #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 | |
043dc33f | 611 | #define AMDGPU_CHUNK_ID_CP_GFX_SHADOW 0x0a |
675da0dd | 612 | |
81629cba | 613 | struct drm_amdgpu_cs_chunk { |
2ce9dde0 MR |
614 | __u32 chunk_id; |
615 | __u32 length_dw; | |
616 | __u64 chunk_data; | |
81629cba AD |
617 | }; |
618 | ||
619 | struct drm_amdgpu_cs_in { | |
620 | /** Rendering context id */ | |
2ce9dde0 | 621 | __u32 ctx_id; |
81629cba | 622 | /** Handle of resource list associated with CS */ |
2ce9dde0 MR |
623 | __u32 bo_list_handle; |
624 | __u32 num_chunks; | |
e90c2b21 | 625 | __u32 flags; |
2ce9dde0 MR |
626 | /** this points to __u64 * which point to cs chunks */ |
627 | __u64 chunks; | |
81629cba AD |
628 | }; |
629 | ||
630 | struct drm_amdgpu_cs_out { | |
2ce9dde0 | 631 | __u64 handle; |
81629cba AD |
632 | }; |
633 | ||
634 | union drm_amdgpu_cs { | |
675da0dd CK |
635 | struct drm_amdgpu_cs_in in; |
636 | struct drm_amdgpu_cs_out out; | |
81629cba AD |
637 | }; |
638 | ||
639 | /* Specify flags to be used for IB */ | |
640 | ||
641 | /* This IB should be submitted to CE */ | |
642 | #define AMDGPU_IB_FLAG_CE (1<<0) | |
643 | ||
ed834af2 | 644 | /* Preamble flag, which means the IB could be dropped if no context switch */ |
cab6d57c | 645 | #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) |
aa2bdb24 | 646 | |
71aec257 ML |
647 | /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ |
648 | #define AMDGPU_IB_FLAG_PREEMPT (1<<2) | |
649 | ||
d240cd9e MO |
650 | /* The IB fence should do the L2 writeback but not invalidate any shader |
651 | * caches (L2/vL1/sL1/I$). */ | |
652 | #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) | |
653 | ||
41cca166 MO |
654 | /* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER. |
655 | * This will reset wave ID counters for the IB. | |
656 | */ | |
657 | #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) | |
658 | ||
0bb5d5b0 LT |
659 | /* Flag the IB as secure (TMZ) |
660 | */ | |
661 | #define AMDGPU_IB_FLAGS_SECURE (1 << 5) | |
662 | ||
43c8546b AG |
663 | /* Tell KMD to flush and invalidate caches |
664 | */ | |
665 | #define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6) | |
666 | ||
81629cba | 667 | struct drm_amdgpu_cs_chunk_ib { |
2ce9dde0 | 668 | __u32 _pad; |
675da0dd | 669 | /** AMDGPU_IB_FLAG_* */ |
2ce9dde0 | 670 | __u32 flags; |
675da0dd | 671 | /** Virtual address to begin IB execution */ |
2ce9dde0 | 672 | __u64 va_start; |
675da0dd | 673 | /** Size of submission */ |
2ce9dde0 | 674 | __u32 ib_bytes; |
675da0dd | 675 | /** HW IP to submit to */ |
2ce9dde0 | 676 | __u32 ip_type; |
675da0dd | 677 | /** HW IP index of the same type to submit to */ |
2ce9dde0 | 678 | __u32 ip_instance; |
675da0dd | 679 | /** Ring index to submit to */ |
2ce9dde0 | 680 | __u32 ring; |
81629cba AD |
681 | }; |
682 | ||
2b48d323 | 683 | struct drm_amdgpu_cs_chunk_dep { |
2ce9dde0 MR |
684 | __u32 ip_type; |
685 | __u32 ip_instance; | |
686 | __u32 ring; | |
687 | __u32 ctx_id; | |
688 | __u64 handle; | |
2b48d323 CK |
689 | }; |
690 | ||
81629cba | 691 | struct drm_amdgpu_cs_chunk_fence { |
2ce9dde0 MR |
692 | __u32 handle; |
693 | __u32 offset; | |
81629cba AD |
694 | }; |
695 | ||
660e8558 DA |
696 | struct drm_amdgpu_cs_chunk_sem { |
697 | __u32 handle; | |
698 | }; | |
699 | ||
2624dd15 CZ |
700 | struct drm_amdgpu_cs_chunk_syncobj { |
701 | __u32 handle; | |
702 | __u32 flags; | |
703 | __u64 point; | |
704 | }; | |
705 | ||
7ca24cf2 MO |
706 | #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 |
707 | #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 | |
708 | #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 | |
709 | ||
710 | union drm_amdgpu_fence_to_handle { | |
711 | struct { | |
712 | struct drm_amdgpu_fence fence; | |
713 | __u32 what; | |
56e0349f | 714 | __u32 pad; |
7ca24cf2 MO |
715 | } in; |
716 | struct { | |
717 | __u32 handle; | |
718 | } out; | |
719 | }; | |
720 | ||
81629cba AD |
721 | struct drm_amdgpu_cs_chunk_data { |
722 | union { | |
723 | struct drm_amdgpu_cs_chunk_ib ib_data; | |
724 | struct drm_amdgpu_cs_chunk_fence fence_data; | |
725 | }; | |
726 | }; | |
727 | ||
043dc33f AD |
728 | #define AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW 0x1 |
729 | ||
730 | struct drm_amdgpu_cs_chunk_cp_gfx_shadow { | |
731 | __u64 shadow_va; | |
732 | __u64 csa_va; | |
733 | __u64 gds_va; | |
734 | __u64 flags; | |
735 | }; | |
736 | ||
c45dd3bd | 737 | /* |
81629cba AD |
738 | * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU |
739 | * | |
740 | */ | |
741 | #define AMDGPU_IDS_FLAGS_FUSION 0x1 | |
aafcafa0 | 742 | #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 |
16c642ec | 743 | #define AMDGPU_IDS_FLAGS_TMZ 0x4 |
b299221f | 744 | #define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x8 |
81629cba AD |
745 | |
746 | /* indicate if acceleration can be working */ | |
747 | #define AMDGPU_INFO_ACCEL_WORKING 0x00 | |
748 | /* get the crtc_id from the mode object id? */ | |
749 | #define AMDGPU_INFO_CRTC_FROM_ID 0x01 | |
750 | /* query hw IP info */ | |
751 | #define AMDGPU_INFO_HW_IP_INFO 0x02 | |
752 | /* query hw IP instance count for the specified type */ | |
753 | #define AMDGPU_INFO_HW_IP_COUNT 0x03 | |
754 | /* timestamp for GL_ARB_timer_query */ | |
755 | #define AMDGPU_INFO_TIMESTAMP 0x05 | |
756 | /* Query the firmware version */ | |
757 | #define AMDGPU_INFO_FW_VERSION 0x0e | |
758 | /* Subquery id: Query VCE firmware version */ | |
759 | #define AMDGPU_INFO_FW_VCE 0x1 | |
760 | /* Subquery id: Query UVD firmware version */ | |
761 | #define AMDGPU_INFO_FW_UVD 0x2 | |
762 | /* Subquery id: Query GMC firmware version */ | |
763 | #define AMDGPU_INFO_FW_GMC 0x03 | |
764 | /* Subquery id: Query GFX ME firmware version */ | |
765 | #define AMDGPU_INFO_FW_GFX_ME 0x04 | |
766 | /* Subquery id: Query GFX PFP firmware version */ | |
767 | #define AMDGPU_INFO_FW_GFX_PFP 0x05 | |
768 | /* Subquery id: Query GFX CE firmware version */ | |
769 | #define AMDGPU_INFO_FW_GFX_CE 0x06 | |
770 | /* Subquery id: Query GFX RLC firmware version */ | |
771 | #define AMDGPU_INFO_FW_GFX_RLC 0x07 | |
772 | /* Subquery id: Query GFX MEC firmware version */ | |
773 | #define AMDGPU_INFO_FW_GFX_MEC 0x08 | |
774 | /* Subquery id: Query SMC firmware version */ | |
775 | #define AMDGPU_INFO_FW_SMC 0x0a | |
776 | /* Subquery id: Query SDMA firmware version */ | |
777 | #define AMDGPU_INFO_FW_SDMA 0x0b | |
6a7ed07e HR |
778 | /* Subquery id: Query PSP SOS firmware version */ |
779 | #define AMDGPU_INFO_FW_SOS 0x0c | |
780 | /* Subquery id: Query PSP ASD firmware version */ | |
781 | #define AMDGPU_INFO_FW_ASD 0x0d | |
3ac952b1 AD |
782 | /* Subquery id: Query VCN firmware version */ |
783 | #define AMDGPU_INFO_FW_VCN 0x0e | |
621a6318 HR |
784 | /* Subquery id: Query GFX RLC SRLC firmware version */ |
785 | #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f | |
786 | /* Subquery id: Query GFX RLC SRLG firmware version */ | |
787 | #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 | |
788 | /* Subquery id: Query GFX RLC SRLS firmware version */ | |
789 | #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 | |
4d11b4b2 DF |
790 | /* Subquery id: Query DMCU firmware version */ |
791 | #define AMDGPU_INFO_FW_DMCU 0x12 | |
9b9ca62d | 792 | #define AMDGPU_INFO_FW_TA 0x13 |
976e51a7 NK |
793 | /* Subquery id: Query DMCUB firmware version */ |
794 | #define AMDGPU_INFO_FW_DMCUB 0x14 | |
6fbcb00c HR |
795 | /* Subquery id: Query TOC firmware version */ |
796 | #define AMDGPU_INFO_FW_TOC 0x15 | |
c4381d0e BZ |
797 | /* Subquery id: Query CAP firmware version */ |
798 | #define AMDGPU_INFO_FW_CAP 0x16 | |
2f9d510f HZ |
799 | /* Subquery id: Query GFX RLCP firmware version */ |
800 | #define AMDGPU_INFO_FW_GFX_RLCP 0x17 | |
801 | /* Subquery id: Query GFX RLCV firmware version */ | |
802 | #define AMDGPU_INFO_FW_GFX_RLCV 0x18 | |
10faf078 YZ |
803 | /* Subquery id: Query MES_KIQ firmware version */ |
804 | #define AMDGPU_INFO_FW_MES_KIQ 0x19 | |
805 | /* Subquery id: Query MES firmware version */ | |
806 | #define AMDGPU_INFO_FW_MES 0x1a | |
b7236296 DF |
807 | /* Subquery id: Query IMU firmware version */ |
808 | #define AMDGPU_INFO_FW_IMU 0x1b | |
5f6e9cdc LY |
809 | /* Subquery id: Query VPE firmware version */ |
810 | #define AMDGPU_INFO_FW_VPE 0x1c | |
976e51a7 | 811 | |
81629cba AD |
812 | /* number of bytes moved for TTM migration */ |
813 | #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f | |
814 | /* the used VRAM size */ | |
815 | #define AMDGPU_INFO_VRAM_USAGE 0x10 | |
816 | /* the used GTT size */ | |
817 | #define AMDGPU_INFO_GTT_USAGE 0x11 | |
818 | /* Information about GDS, etc. resource configuration */ | |
819 | #define AMDGPU_INFO_GDS_CONFIG 0x13 | |
820 | /* Query information about VRAM and GTT domains */ | |
821 | #define AMDGPU_INFO_VRAM_GTT 0x14 | |
822 | /* Query information about register in MMR address space*/ | |
823 | #define AMDGPU_INFO_READ_MMR_REG 0x15 | |
824 | /* Query information about device: rev id, family, etc. */ | |
825 | #define AMDGPU_INFO_DEV_INFO 0x16 | |
826 | /* visible vram usage */ | |
827 | #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 | |
83a59b63 MO |
828 | /* number of TTM buffer evictions */ |
829 | #define AMDGPU_INFO_NUM_EVICTIONS 0x18 | |
e0adf6c8 JZ |
830 | /* Query memory about VRAM and GTT domains */ |
831 | #define AMDGPU_INFO_MEMORY 0x19 | |
bbe87974 AD |
832 | /* Query vce clock table */ |
833 | #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A | |
40ee5888 EQ |
834 | /* Query vbios related information */ |
835 | #define AMDGPU_INFO_VBIOS 0x1B | |
836 | /* Subquery id: Query vbios size */ | |
837 | #define AMDGPU_INFO_VBIOS_SIZE 0x1 | |
838 | /* Subquery id: Query vbios image */ | |
839 | #define AMDGPU_INFO_VBIOS_IMAGE 0x2 | |
29b4c589 JG |
840 | /* Subquery id: Query vbios info */ |
841 | #define AMDGPU_INFO_VBIOS_INFO 0x3 | |
44879b62 AN |
842 | /* Query UVD handles */ |
843 | #define AMDGPU_INFO_NUM_HANDLES 0x1C | |
5ebbac4b AD |
844 | /* Query sensor related information */ |
845 | #define AMDGPU_INFO_SENSOR 0x1D | |
846 | /* Subquery id: Query GPU shader clock */ | |
847 | #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 | |
848 | /* Subquery id: Query GPU memory clock */ | |
849 | #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 | |
850 | /* Subquery id: Query GPU temperature */ | |
851 | #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 | |
852 | /* Subquery id: Query GPU load */ | |
853 | #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 | |
854 | /* Subquery id: Query average GPU power */ | |
855 | #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 | |
856 | /* Subquery id: Query northbridge voltage */ | |
857 | #define AMDGPU_INFO_SENSOR_VDDNB 0x6 | |
858 | /* Subquery id: Query graphics voltage */ | |
859 | #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 | |
60bbade2 RZ |
860 | /* Subquery id: Query GPU stable pstate shader clock */ |
861 | #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 | |
862 | /* Subquery id: Query GPU stable pstate memory clock */ | |
863 | #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 | |
5cfd9784 EQ |
864 | /* Subquery id: Query GPU peak pstate shader clock */ |
865 | #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK 0xa | |
866 | /* Subquery id: Query GPU peak pstate memory clock */ | |
867 | #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK 0xb | |
d3f452f3 AD |
868 | /* Subquery id: Query input GPU power */ |
869 | #define AMDGPU_INFO_SENSOR_GPU_INPUT_POWER 0xc | |
68e2c5ff MO |
870 | /* Number of VRAM page faults on CPU access. */ |
871 | #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E | |
1f7251b7 | 872 | #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F |
5cb77114 | 873 | /* query ras mask of enabled features*/ |
874 | #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 | |
5cb77114 | 875 | /* RAS MASK: UMC (VRAM) */ |
876 | #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) | |
877 | /* RAS MASK: SDMA */ | |
878 | #define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1) | |
879 | /* RAS MASK: GFX */ | |
880 | #define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2) | |
881 | /* RAS MASK: MMHUB */ | |
882 | #define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3) | |
883 | /* RAS MASK: ATHUB */ | |
884 | #define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4) | |
885 | /* RAS MASK: PCIE */ | |
886 | #define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5) | |
887 | /* RAS MASK: HDP */ | |
888 | #define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6) | |
889 | /* RAS MASK: XGMI */ | |
890 | #define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7) | |
891 | /* RAS MASK: DF */ | |
892 | #define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8) | |
893 | /* RAS MASK: SMN */ | |
894 | #define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9) | |
895 | /* RAS MASK: SEM */ | |
896 | #define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10) | |
897 | /* RAS MASK: MP0 */ | |
898 | #define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11) | |
899 | /* RAS MASK: MP1 */ | |
900 | #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) | |
901 | /* RAS MASK: FUSE */ | |
902 | #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) | |
72f4c9d5 AD |
903 | /* query video encode/decode caps */ |
904 | #define AMDGPU_INFO_VIDEO_CAPS 0x21 | |
905 | /* Subquery id: Decode */ | |
906 | #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0 | |
907 | /* Subquery id: Encode */ | |
908 | #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1 | |
4f18b9a6 BN |
909 | /* Query the max number of IBs per gang per submission */ |
910 | #define AMDGPU_INFO_MAX_IBS 0x22 | |
7a41ed8b AD |
911 | /* query last page fault info */ |
912 | #define AMDGPU_INFO_GPUVM_FAULT 0x23 | |
81629cba AD |
913 | |
914 | #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 | |
915 | #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff | |
916 | #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 | |
917 | #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff | |
918 | ||
000cab9a HR |
919 | struct drm_amdgpu_query_fw { |
920 | /** AMDGPU_INFO_FW_* */ | |
921 | __u32 fw_type; | |
922 | /** | |
923 | * Index of the IP if there are more IPs of | |
924 | * the same type. | |
925 | */ | |
926 | __u32 ip_instance; | |
927 | /** | |
928 | * Index of the engine. Whether this is used depends | |
929 | * on the firmware type. (e.g. MEC, SDMA) | |
930 | */ | |
931 | __u32 index; | |
932 | __u32 _pad; | |
933 | }; | |
934 | ||
81629cba AD |
935 | /* Input structure for the INFO ioctl */ |
936 | struct drm_amdgpu_info { | |
937 | /* Where the return value will be stored */ | |
2ce9dde0 | 938 | __u64 return_pointer; |
81629cba AD |
939 | /* The size of the return value. Just like "size" in "snprintf", |
940 | * it limits how many bytes the kernel can write. */ | |
2ce9dde0 | 941 | __u32 return_size; |
81629cba | 942 | /* The query request id. */ |
2ce9dde0 | 943 | __u32 query; |
81629cba AD |
944 | |
945 | union { | |
946 | struct { | |
2ce9dde0 MR |
947 | __u32 id; |
948 | __u32 _pad; | |
81629cba AD |
949 | } mode_crtc; |
950 | ||
951 | struct { | |
952 | /** AMDGPU_HW_IP_* */ | |
2ce9dde0 | 953 | __u32 type; |
81629cba | 954 | /** |
675da0dd CK |
955 | * Index of the IP if there are more IPs of the same |
956 | * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. | |
81629cba | 957 | */ |
2ce9dde0 | 958 | __u32 ip_instance; |
81629cba AD |
959 | } query_hw_ip; |
960 | ||
961 | struct { | |
2ce9dde0 | 962 | __u32 dword_offset; |
675da0dd | 963 | /** number of registers to read */ |
2ce9dde0 MR |
964 | __u32 count; |
965 | __u32 instance; | |
675da0dd | 966 | /** For future use, no flags defined so far */ |
2ce9dde0 | 967 | __u32 flags; |
81629cba AD |
968 | } read_mmr_reg; |
969 | ||
000cab9a | 970 | struct drm_amdgpu_query_fw query_fw; |
40ee5888 EQ |
971 | |
972 | struct { | |
973 | __u32 type; | |
974 | __u32 offset; | |
975 | } vbios_info; | |
5ebbac4b AD |
976 | |
977 | struct { | |
978 | __u32 type; | |
979 | } sensor_info; | |
f35e9bdb AD |
980 | |
981 | struct { | |
982 | __u32 type; | |
983 | } video_cap; | |
81629cba AD |
984 | }; |
985 | }; | |
986 | ||
987 | struct drm_amdgpu_info_gds { | |
988 | /** GDS GFX partition size */ | |
2ce9dde0 | 989 | __u32 gds_gfx_partition_size; |
81629cba | 990 | /** GDS compute partition size */ |
2ce9dde0 | 991 | __u32 compute_partition_size; |
81629cba | 992 | /** total GDS memory size */ |
2ce9dde0 | 993 | __u32 gds_total_size; |
81629cba | 994 | /** GWS size per GFX partition */ |
2ce9dde0 | 995 | __u32 gws_per_gfx_partition; |
81629cba | 996 | /** GSW size per compute partition */ |
2ce9dde0 | 997 | __u32 gws_per_compute_partition; |
81629cba | 998 | /** OA size per GFX partition */ |
2ce9dde0 | 999 | __u32 oa_per_gfx_partition; |
81629cba | 1000 | /** OA size per compute partition */ |
2ce9dde0 MR |
1001 | __u32 oa_per_compute_partition; |
1002 | __u32 _pad; | |
81629cba AD |
1003 | }; |
1004 | ||
1005 | struct drm_amdgpu_info_vram_gtt { | |
2ce9dde0 MR |
1006 | __u64 vram_size; |
1007 | __u64 vram_cpu_accessible_size; | |
1008 | __u64 gtt_size; | |
81629cba AD |
1009 | }; |
1010 | ||
e0adf6c8 JZ |
1011 | struct drm_amdgpu_heap_info { |
1012 | /** max. physical memory */ | |
1013 | __u64 total_heap_size; | |
1014 | ||
1015 | /** Theoretical max. available memory in the given heap */ | |
1016 | __u64 usable_heap_size; | |
1017 | ||
1018 | /** | |
1019 | * Number of bytes allocated in the heap. This includes all processes | |
1020 | * and private allocations in the kernel. It changes when new buffers | |
1021 | * are allocated, freed, and moved. It cannot be larger than | |
1022 | * heap_size. | |
1023 | */ | |
1024 | __u64 heap_usage; | |
1025 | ||
1026 | /** | |
1027 | * Theoretical possible max. size of buffer which | |
1028 | * could be allocated in the given heap | |
1029 | */ | |
1030 | __u64 max_allocation; | |
9f6163e7 JZ |
1031 | }; |
1032 | ||
e0adf6c8 JZ |
1033 | struct drm_amdgpu_memory_info { |
1034 | struct drm_amdgpu_heap_info vram; | |
1035 | struct drm_amdgpu_heap_info cpu_accessible_vram; | |
1036 | struct drm_amdgpu_heap_info gtt; | |
cfa32556 JZ |
1037 | }; |
1038 | ||
81629cba | 1039 | struct drm_amdgpu_info_firmware { |
2ce9dde0 MR |
1040 | __u32 ver; |
1041 | __u32 feature; | |
81629cba AD |
1042 | }; |
1043 | ||
29b4c589 JG |
1044 | struct drm_amdgpu_info_vbios { |
1045 | __u8 name[64]; | |
1046 | __u8 vbios_pn[64]; | |
1047 | __u32 version; | |
1048 | __u32 pad; | |
1049 | __u8 vbios_ver_str[32]; | |
1050 | __u8 date[32]; | |
1051 | }; | |
1052 | ||
81c59f54 KW |
1053 | #define AMDGPU_VRAM_TYPE_UNKNOWN 0 |
1054 | #define AMDGPU_VRAM_TYPE_GDDR1 1 | |
1055 | #define AMDGPU_VRAM_TYPE_DDR2 2 | |
1056 | #define AMDGPU_VRAM_TYPE_GDDR3 3 | |
1057 | #define AMDGPU_VRAM_TYPE_GDDR4 4 | |
1058 | #define AMDGPU_VRAM_TYPE_GDDR5 5 | |
1059 | #define AMDGPU_VRAM_TYPE_HBM 6 | |
1060 | #define AMDGPU_VRAM_TYPE_DDR3 7 | |
1e09b053 | 1061 | #define AMDGPU_VRAM_TYPE_DDR4 8 |
d67383e6 | 1062 | #define AMDGPU_VRAM_TYPE_GDDR6 9 |
1e483203 | 1063 | #define AMDGPU_VRAM_TYPE_DDR5 10 |
d534ca71 AD |
1064 | #define AMDGPU_VRAM_TYPE_LPDDR4 11 |
1065 | #define AMDGPU_VRAM_TYPE_LPDDR5 12 | |
81c59f54 | 1066 | |
81629cba AD |
1067 | struct drm_amdgpu_info_device { |
1068 | /** PCI Device ID */ | |
2ce9dde0 | 1069 | __u32 device_id; |
81629cba | 1070 | /** Internal chip revision: A0, A1, etc.) */ |
2ce9dde0 MR |
1071 | __u32 chip_rev; |
1072 | __u32 external_rev; | |
81629cba | 1073 | /** Revision id in PCI Config space */ |
2ce9dde0 MR |
1074 | __u32 pci_rev; |
1075 | __u32 family; | |
1076 | __u32 num_shader_engines; | |
1077 | __u32 num_shader_arrays_per_engine; | |
675da0dd | 1078 | /* in KHz */ |
2ce9dde0 MR |
1079 | __u32 gpu_counter_freq; |
1080 | __u64 max_engine_clock; | |
1081 | __u64 max_memory_clock; | |
81629cba | 1082 | /* cu information */ |
2ce9dde0 | 1083 | __u32 cu_active_number; |
dbfe85ea | 1084 | /* NOTE: cu_ao_mask is INVALID, DON'T use it */ |
2ce9dde0 MR |
1085 | __u32 cu_ao_mask; |
1086 | __u32 cu_bitmap[4][4]; | |
81629cba | 1087 | /** Render backend pipe mask. One render backend is CB+DB. */ |
2ce9dde0 MR |
1088 | __u32 enabled_rb_pipes_mask; |
1089 | __u32 num_rb_pipes; | |
1090 | __u32 num_hw_gfx_contexts; | |
e3e84b0a MO |
1091 | /* PCIe version (the smaller of the GPU and the CPU/motherboard) */ |
1092 | __u32 pcie_gen; | |
2ce9dde0 | 1093 | __u64 ids_flags; |
81629cba | 1094 | /** Starting virtual address for UMDs. */ |
2ce9dde0 | 1095 | __u64 virtual_address_offset; |
02b70c8c | 1096 | /** The maximum virtual address */ |
2ce9dde0 | 1097 | __u64 virtual_address_max; |
81629cba | 1098 | /** Required alignment of virtual addresses. */ |
2ce9dde0 | 1099 | __u32 virtual_address_alignment; |
81629cba | 1100 | /** Page table entry - fragment size */ |
2ce9dde0 MR |
1101 | __u32 pte_fragment_size; |
1102 | __u32 gart_page_size; | |
a101a899 | 1103 | /** constant engine ram size*/ |
2ce9dde0 | 1104 | __u32 ce_ram_size; |
cab6d57c | 1105 | /** video memory type info*/ |
2ce9dde0 | 1106 | __u32 vram_type; |
81c59f54 | 1107 | /** video memory bit width*/ |
2ce9dde0 | 1108 | __u32 vram_bit_width; |
fa92754e | 1109 | /* vce harvesting instance */ |
2ce9dde0 | 1110 | __u32 vce_harvest_config; |
df6e2c4a JZ |
1111 | /* gfx double offchip LDS buffers */ |
1112 | __u32 gc_double_offchip_lds_buf; | |
bce23e00 AD |
1113 | /* NGG Primitive Buffer */ |
1114 | __u64 prim_buf_gpu_addr; | |
1115 | /* NGG Position Buffer */ | |
1116 | __u64 pos_buf_gpu_addr; | |
1117 | /* NGG Control Sideband */ | |
1118 | __u64 cntl_sb_buf_gpu_addr; | |
1119 | /* NGG Parameter Cache */ | |
1120 | __u64 param_buf_gpu_addr; | |
408bfe7c JZ |
1121 | __u32 prim_buf_size; |
1122 | __u32 pos_buf_size; | |
1123 | __u32 cntl_sb_buf_size; | |
1124 | __u32 param_buf_size; | |
1125 | /* wavefront size*/ | |
1126 | __u32 wave_front_size; | |
1127 | /* shader visible vgprs*/ | |
1128 | __u32 num_shader_visible_vgprs; | |
1129 | /* CU per shader array*/ | |
1130 | __u32 num_cu_per_sh; | |
1131 | /* number of tcc blocks*/ | |
1132 | __u32 num_tcc_blocks; | |
1133 | /* gs vgt table depth*/ | |
1134 | __u32 gs_vgt_table_depth; | |
1135 | /* gs primitive buffer depth*/ | |
1136 | __u32 gs_prim_buffer_depth; | |
1137 | /* max gs wavefront per vgt*/ | |
1138 | __u32 max_gs_waves_per_vgt; | |
e3e84b0a MO |
1139 | /* PCIe number of lanes (the smaller of the GPU and the CPU/motherboard) */ |
1140 | __u32 pcie_num_lanes; | |
dbfe85ea FC |
1141 | /* always on cu bitmap */ |
1142 | __u32 cu_ao_bitmap[4][4]; | |
5b565e0e CK |
1143 | /** Starting high virtual address for UMDs. */ |
1144 | __u64 high_va_offset; | |
1145 | /** The maximum high virtual address */ | |
1146 | __u64 high_va_max; | |
22e96fa6 HZ |
1147 | /* gfx10 pa_sc_tile_steering_override */ |
1148 | __u32 pa_sc_tile_steering_override; | |
cf21e76a MO |
1149 | /* disabled TCCs */ |
1150 | __u64 tcc_disabled_mask; | |
88347fa1 EQ |
1151 | __u64 min_engine_clock; |
1152 | __u64 min_memory_clock; | |
b299221f MO |
1153 | /* The following fields are only set on gfx11+, older chips set 0. */ |
1154 | __u32 tcp_cache_size; /* AKA GL0, VMEM cache */ | |
1155 | __u32 num_sqc_per_wgp; | |
1156 | __u32 sqc_data_cache_size; /* AKA SMEM cache */ | |
1157 | __u32 sqc_inst_cache_size; | |
1158 | __u32 gl1c_cache_size; | |
1159 | __u32 gl2c_cache_size; | |
1160 | __u64 mall_size; /* AKA infinity cache */ | |
1161 | /* high 32 bits of the rb pipes mask */ | |
1162 | __u32 enabled_rb_pipes_mask_hi; | |
edd90380 AD |
1163 | /* shadow area size for gfx11 */ |
1164 | __u32 shadow_size; | |
1165 | /* shadow area base virtual alignment for gfx11 */ | |
1166 | __u32 shadow_alignment; | |
1167 | /* context save area size for gfx11 */ | |
1168 | __u32 csa_size; | |
1169 | /* context save area base virtual alignment for gfx11 */ | |
1170 | __u32 csa_alignment; | |
81629cba AD |
1171 | }; |
1172 | ||
1173 | struct drm_amdgpu_info_hw_ip { | |
1174 | /** Version of h/w IP */ | |
2ce9dde0 MR |
1175 | __u32 hw_ip_version_major; |
1176 | __u32 hw_ip_version_minor; | |
81629cba | 1177 | /** Capabilities */ |
2ce9dde0 | 1178 | __u64 capabilities_flags; |
71062f43 | 1179 | /** command buffer address start alignment*/ |
2ce9dde0 | 1180 | __u32 ib_start_alignment; |
71062f43 | 1181 | /** command buffer size alignment*/ |
2ce9dde0 | 1182 | __u32 ib_size_alignment; |
81629cba | 1183 | /** Bitmask of available rings. Bit 0 means ring 0, etc. */ |
2ce9dde0 | 1184 | __u32 available_rings; |
af14e7c2 AD |
1185 | /** version info: bits 23:16 major, 15:8 minor, 7:0 revision */ |
1186 | __u32 ip_discovery_version; | |
81629cba AD |
1187 | }; |
1188 | ||
44879b62 AN |
1189 | struct drm_amdgpu_info_num_handles { |
1190 | /** Max handles as supported by firmware for UVD */ | |
1191 | __u32 uvd_max_handles; | |
1192 | /** Handles currently in use for UVD */ | |
1193 | __u32 uvd_used_handles; | |
1194 | }; | |
1195 | ||
bbe87974 AD |
1196 | #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 |
1197 | ||
1198 | struct drm_amdgpu_info_vce_clock_table_entry { | |
1199 | /** System clock */ | |
1200 | __u32 sclk; | |
1201 | /** Memory clock */ | |
1202 | __u32 mclk; | |
1203 | /** VCE clock */ | |
1204 | __u32 eclk; | |
1205 | __u32 pad; | |
1206 | }; | |
1207 | ||
1208 | struct drm_amdgpu_info_vce_clock_table { | |
1209 | struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; | |
1210 | __u32 num_valid_entries; | |
1211 | __u32 pad; | |
1212 | }; | |
1213 | ||
f35e9bdb AD |
1214 | /* query video encode/decode caps */ |
1215 | #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0 | |
1216 | #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1 | |
1217 | #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2 | |
1218 | #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3 | |
1219 | #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4 | |
1220 | #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5 | |
1221 | #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6 | |
1222 | #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7 | |
1223 | #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8 | |
1224 | ||
1225 | struct drm_amdgpu_info_video_codec_info { | |
1226 | __u32 valid; | |
1227 | __u32 max_width; | |
1228 | __u32 max_height; | |
1229 | __u32 max_pixels_per_frame; | |
1230 | __u32 max_level; | |
1231 | __u32 pad; | |
1232 | }; | |
1233 | ||
1234 | struct drm_amdgpu_info_video_caps { | |
1235 | struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT]; | |
1236 | }; | |
1237 | ||
7a41ed8b AD |
1238 | #define AMDGPU_VMHUB_TYPE_MASK 0xff |
1239 | #define AMDGPU_VMHUB_TYPE_SHIFT 0 | |
1240 | #define AMDGPU_VMHUB_TYPE_GFX 0 | |
1241 | #define AMDGPU_VMHUB_TYPE_MM0 1 | |
1242 | #define AMDGPU_VMHUB_TYPE_MM1 2 | |
1243 | #define AMDGPU_VMHUB_IDX_MASK 0xff00 | |
1244 | #define AMDGPU_VMHUB_IDX_SHIFT 8 | |
1245 | ||
1246 | struct drm_amdgpu_info_gpuvm_fault { | |
1247 | __u64 addr; | |
1248 | __u32 status; | |
1249 | __u32 vmhub; | |
1250 | }; | |
1251 | ||
81629cba AD |
1252 | /* |
1253 | * Supported GPU families | |
1254 | */ | |
1255 | #define AMDGPU_FAMILY_UNKNOWN 0 | |
295d0daf | 1256 | #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ |
81629cba AD |
1257 | #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ |
1258 | #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ | |
1259 | #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ | |
39bb0c92 | 1260 | #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ |
a8f1f1ce | 1261 | #define AMDGPU_FAMILY_AI 141 /* Vega10 */ |
2ca8a5d2 | 1262 | #define AMDGPU_FAMILY_RV 142 /* Raven */ |
107c34bc | 1263 | #define AMDGPU_FAMILY_NV 143 /* Navi10 */ |
f7b2cdb2 | 1264 | #define AMDGPU_FAMILY_VGH 144 /* Van Gogh */ |
5eca8379 | 1265 | #define AMDGPU_FAMILY_GC_11_0_0 145 /* GC 11.0.0 */ |
90a187d2 | 1266 | #define AMDGPU_FAMILY_YC 146 /* Yellow Carp */ |
cbe757ec | 1267 | #define AMDGPU_FAMILY_GC_11_0_1 148 /* GC 11.0.1 */ |
874bfdfa | 1268 | #define AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */ |
a65dbf7c | 1269 | #define AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */ |
2c8a7ca1 | 1270 | #define AMDGPU_FAMILY_GC_11_5_0 150 /* GC 11.5.0 */ |
81629cba | 1271 | |
cfa7152f EV |
1272 | #if defined(__cplusplus) |
1273 | } | |
1274 | #endif | |
1275 | ||
81629cba | 1276 | #endif |