[linux-2.6-block.git] / include / sound / sof / topology.h

/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
/*
 * This file is provided under a dual BSD/GPLv2 license.  When using or
 * redistributing this file, you may do so under either license.
 *
 * Copyright(c) 2018 Intel Corporation
 */

#ifndef __INCLUDE_SOUND_SOF_TOPOLOGY_H__
#define __INCLUDE_SOUND_SOF_TOPOLOGY_H__

#include <sound/sof/header.h>

/*
 * Component
 */

/* types of component */
enum sof_comp_type {
	SOF_COMP_NONE = 0,
	SOF_COMP_HOST,
	SOF_COMP_DAI,
	SOF_COMP_SG_HOST,	/**< scatter gather variant */
	SOF_COMP_SG_DAI,	/**< scatter gather variant */
	SOF_COMP_VOLUME,
	SOF_COMP_MIXER,
	SOF_COMP_MUX,
	SOF_COMP_SRC,
	SOF_COMP_DEPRECATED0, /* Formerly SOF_COMP_SPLITTER */
	SOF_COMP_TONE,
	SOF_COMP_DEPRECATED1, /* Formerly SOF_COMP_SWITCH */
	SOF_COMP_BUFFER,
	SOF_COMP_EQ_IIR,
	SOF_COMP_EQ_FIR,
	SOF_COMP_KEYWORD_DETECT,
	SOF_COMP_KPB,			/* A key phrase buffer component */
	SOF_COMP_SELECTOR,		/**< channel selector component */
	SOF_COMP_DEMUX,
	SOF_COMP_ASRC,		/**< Asynchronous sample rate converter */
	SOF_COMP_DCBLOCK,
	SOF_COMP_SMART_AMP,             /**< smart amplifier component */
	SOF_COMP_MODULE_ADAPTER,		/**< module adapter */
	/* keep FILEREAD/FILEWRITE as the last ones */
	SOF_COMP_FILEREAD = 10000,	/**< host test based file IO */
	SOF_COMP_FILEWRITE = 10001,	/**< host test based file IO */
};

/* XRUN action for component */
#define SOF_XRUN_STOP		1	/**< stop stream */
#define SOF_XRUN_UNDER_ZERO	2	/**< send 0s to sink */
#define SOF_XRUN_OVER_NULL	4	/**< send data to NULL */

/* create new generic component - SOF_IPC_TPLG_COMP_NEW */
struct sof_ipc_comp {
	struct sof_ipc_cmd_hdr hdr;
	uint32_t id;
	enum sof_comp_type type;
	uint32_t pipeline_id;
	uint32_t core;

	/* extended data length, 0 if no extended data */
	uint32_t ext_data_length;
} __packed __aligned(4);

/*
 * Component Buffers
 */

/*
 * SOF memory capabilities, add new ones at the end
 */
#define SOF_MEM_CAPS_RAM		BIT(0)
#define SOF_MEM_CAPS_ROM		BIT(1)
#define SOF_MEM_CAPS_EXT		BIT(2) /**< external */
#define SOF_MEM_CAPS_LP			BIT(3) /**< low power */
#define SOF_MEM_CAPS_HP			BIT(4) /**< high performance */
#define SOF_MEM_CAPS_DMA		BIT(5) /**< DMA'able */
#define SOF_MEM_CAPS_CACHE		BIT(6) /**< cacheable */
#define SOF_MEM_CAPS_EXEC		BIT(7) /**< executable */
#define SOF_MEM_CAPS_L3			BIT(8) /**< L3 memory */

/*
 * overrun will cause ring buffer overwrite, instead of XRUN.
 */
#define SOF_BUF_OVERRUN_PERMITTED	BIT(0)

/*
 * underrun will cause readback of 0s, instead of XRUN.
 */
#define SOF_BUF_UNDERRUN_PERMITTED	BIT(1)

/* the UUID size in bytes, shared between FW and host */
#define SOF_UUID_SIZE	16

/* create new component buffer - SOF_IPC_TPLG_BUFFER_NEW */
struct sof_ipc_buffer {
	struct sof_ipc_comp comp;
	uint32_t size;		/**< buffer size in bytes */
	uint32_t caps;		/**< SOF_MEM_CAPS_ */
	uint32_t flags;		/**< SOF_BUF_ flags defined above */
	uint32_t reserved;	/**< reserved for future use */
} __packed __aligned(4);

/* generic component config data - must always be after struct sof_ipc_comp */
struct sof_ipc_comp_config {
	struct sof_ipc_cmd_hdr hdr;
	uint32_t periods_sink;	/**< 0 means variable */
	uint32_t periods_source;/**< 0 means variable */
	uint32_t reserved1;	/**< reserved */
	uint32_t frame_fmt;	/**< SOF_IPC_FRAME_ */
	uint32_t xrun_action;

	/* reserved for future use */
	uint32_t reserved[2];
} __packed __aligned(4);

/* generic host component */
struct sof_ipc_comp_host {
	struct sof_ipc_comp comp;
	struct sof_ipc_comp_config config;
	uint32_t direction;	/**< SOF_IPC_STREAM_ */
	uint32_t no_irq;	/**< don't send periodic IRQ to host/DSP */
	uint32_t dmac_config; /**< DMA engine specific */
} __packed __aligned(4);

/* generic DAI component */
struct sof_ipc_comp_dai {
	struct sof_ipc_comp comp;
	struct sof_ipc_comp_config config;
	uint32_t direction;	/**< SOF_IPC_STREAM_ */
	uint32_t dai_index;	/**< index of this type dai */
	uint32_t type;		/**< DAI type - SOF_DAI_ */
	uint32_t reserved;	/**< reserved */
} __packed __aligned(4);

/* generic mixer component */
struct sof_ipc_comp_mixer {
	struct sof_ipc_comp comp;
	struct sof_ipc_comp_config config;
} __packed __aligned(4);

/* volume ramping types */
enum sof_volume_ramp {
	SOF_VOLUME_LINEAR	= 0,
	SOF_VOLUME_LOG,
	SOF_VOLUME_LINEAR_ZC,
	SOF_VOLUME_LOG_ZC,
	SOF_VOLUME_WINDOWS_FADE,
	SOF_VOLUME_WINDOWS_NO_FADE,
};

/* generic volume component */
struct sof_ipc_comp_volume {
	struct sof_ipc_comp comp;
	struct sof_ipc_comp_config config;
	uint32_t channels;
	uint32_t min_value;
	uint32_t max_value;
	uint32_t ramp;		/**< SOF_VOLUME_ */
	uint32_t initial_ramp;	/**< ramp space in ms */
} __packed __aligned(4);

/* generic SRC component */
struct sof_ipc_comp_src {
	struct sof_ipc_comp comp;
	struct sof_ipc_comp_config config;
	/* either source or sink rate must be non zero */
	uint32_t source_rate;	/**< source rate or 0 for variable */
	uint32_t sink_rate;	/**< sink rate or 0 for variable */
	uint32_t rate_mask;	/**< SOF_RATE_ supported rates */
} __packed __aligned(4);

/* generic ASRC component */
struct sof_ipc_comp_asrc {
	struct sof_ipc_comp comp;
	struct sof_ipc_comp_config config;
	/* either source or sink rate must be non zero */
	uint32_t source_rate;		/**< Define fixed source rate or */
					/**< use 0 to indicate need to get */
					/**< the rate from stream */
	uint32_t sink_rate;		/**< Define fixed sink rate or */
					/**< use 0 to indicate need to get */
					/**< the rate from stream */
	uint32_t asynchronous_mode;	/**< synchronous 0, asynchronous 1 */
					/**< When 1 the ASRC tracks and */
					/**< compensates for drift. */
	uint32_t operation_mode;	/**< push 0, pull 1, In push mode the */
					/**< ASRC consumes a defined number */
					/**< of frames at input, with varying */
					/**< number of frames at output. */
					/**< In pull mode the ASRC outputs */
					/**< a defined number of frames while */
					/**< number of input frames varies. */

	/* reserved for future use */
	uint32_t reserved[4];
} __packed __aligned(4);

/* generic MUX component */
struct sof_ipc_comp_mux {
	struct sof_ipc_comp comp;
	struct sof_ipc_comp_config config;
} __packed __aligned(4);

/* generic tone generator component */
struct sof_ipc_comp_tone {
	struct sof_ipc_comp comp;
	struct sof_ipc_comp_config config;
	int32_t sample_rate;
	int32_t frequency;
	int32_t amplitude;
	int32_t freq_mult;
	int32_t ampl_mult;
	int32_t length;
	int32_t period;
	int32_t repeats;
	int32_t ramp_step;
} __packed __aligned(4);

/** \brief Types of processing components */
enum sof_ipc_process_type {
	SOF_PROCESS_NONE = 0,		/**< None */
	SOF_PROCESS_EQFIR,		/**< Intel FIR */
	SOF_PROCESS_EQIIR,		/**< Intel IIR */
	SOF_PROCESS_KEYWORD_DETECT,	/**< Keyword Detection */
	SOF_PROCESS_KPB,		/**< KeyPhrase Buffer Manager */
	SOF_PROCESS_CHAN_SELECTOR,	/**< Channel Selector */
	SOF_PROCESS_MUX,
	SOF_PROCESS_DEMUX,
	SOF_PROCESS_DCBLOCK,
	SOF_PROCESS_SMART_AMP,	/**< Smart Amplifier */
};

/* generic "effect", "codec" or proprietary processing component */
struct sof_ipc_comp_process {
	struct sof_ipc_comp comp;
	struct sof_ipc_comp_config config;
	uint32_t size;	/**< size of bespoke data section in bytes */
	uint32_t type;	/**< sof_ipc_process_type */

	/* reserved for future use */
	uint32_t reserved[7];

	unsigned char data[];
} __packed __aligned(4);

/* frees components, buffers and pipelines
 * SOF_IPC_TPLG_COMP_FREE, SOF_IPC_TPLG_PIPE_FREE, SOF_IPC_TPLG_BUFFER_FREE
 */
struct sof_ipc_free {
	struct sof_ipc_cmd_hdr hdr;
	uint32_t id;
} __packed __aligned(4);

struct sof_ipc_comp_reply {
	struct sof_ipc_reply rhdr;
	uint32_t id;
	uint32_t offset;
} __packed __aligned(4);

/*
 * Pipeline
 */

/** \brief Types of pipeline scheduling time domains */
enum sof_ipc_pipe_sched_time_domain {
	SOF_TIME_DOMAIN_DMA = 0,	/**< DMA interrupt */
	SOF_TIME_DOMAIN_TIMER,		/**< Timer interrupt */
};

/* new pipeline - SOF_IPC_TPLG_PIPE_NEW */
struct sof_ipc_pipe_new {
	struct sof_ipc_cmd_hdr hdr;
	uint32_t comp_id;	/**< component id for pipeline */
	uint32_t pipeline_id;	/**< pipeline id */
	uint32_t sched_id;	/**< Scheduling component id */
	uint32_t core;		/**< core we run on */
	uint32_t period;	/**< execution period in us*/
	uint32_t priority;	/**< priority level 0 (low) to 10 (max) */
	uint32_t period_mips;	/**< worst case instruction count per period */
	uint32_t frames_per_sched;/**< output frames of pipeline, 0 is variable */
	uint32_t xrun_limit_usecs; /**< report xruns greater than limit */
	uint32_t time_domain;	/**< scheduling time domain */
} __packed __aligned(4);

/* pipeline construction complete - SOF_IPC_TPLG_PIPE_COMPLETE */
struct sof_ipc_pipe_ready {
	struct sof_ipc_cmd_hdr hdr;
	uint32_t comp_id;
} __packed __aligned(4);

struct sof_ipc_pipe_free {
	struct sof_ipc_cmd_hdr hdr;
	uint32_t comp_id;
} __packed __aligned(4);

/* connect two components in pipeline - SOF_IPC_TPLG_COMP_CONNECT */
struct sof_ipc_pipe_comp_connect {
	struct sof_ipc_cmd_hdr hdr;
	uint32_t source_id;
	uint32_t sink_id;
} __packed __aligned(4);

/* external events */
enum sof_event_types {
	SOF_EVENT_NONE = 0,
	SOF_KEYWORD_DETECT_DAPM_EVENT,
};

#endif
Commit	Line	Data
e149ca29	1	/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
311ce4fe LG	2	/*
	3	* This file is provided under a dual BSD/GPLv2 license. When using or
	4	* redistributing this file, you may do so under either license.
	5	*
ea89a742	6	* Copyright(c) 2018 Intel Corporation
311ce4fe LG	7	*/
	8
	9	#ifndef __INCLUDE_SOUND_SOF_TOPOLOGY_H__
	10	#define __INCLUDE_SOUND_SOF_TOPOLOGY_H__
	11
	12	#include <sound/sof/header.h>
	13
	14	/*
	15	* Component
	16	*/
	17
	18	/* types of component */
	19	enum sof_comp_type {
	20	SOF_COMP_NONE = 0,
	21	SOF_COMP_HOST,
	22	SOF_COMP_DAI,
	23	SOF_COMP_SG_HOST, /*< scatter gather variant /
	24	SOF_COMP_SG_DAI, /*< scatter gather variant /
	25	SOF_COMP_VOLUME,
	26	SOF_COMP_MIXER,
	27	SOF_COMP_MUX,
	28	SOF_COMP_SRC,
8dc97ccf	29	SOF_COMP_DEPRECATED0, /* Formerly SOF_COMP_SPLITTER */
311ce4fe	30	SOF_COMP_TONE,
8dc97ccf	31	SOF_COMP_DEPRECATED1, /* Formerly SOF_COMP_SWITCH */
311ce4fe LG	32	SOF_COMP_BUFFER,
	33	SOF_COMP_EQ_IIR,
	34	SOF_COMP_EQ_FIR,
	35	SOF_COMP_KEYWORD_DETECT,
	36	SOF_COMP_KPB, /* A key phrase buffer component */
	37	SOF_COMP_SELECTOR, /*< channel selector component /
66358069	38	SOF_COMP_DEMUX,
433363e7	39	SOF_COMP_ASRC, /*< Asynchronous sample rate converter /
542adb2a	40	SOF_COMP_DCBLOCK,
82e8c00f	41	SOF_COMP_SMART_AMP, /*< smart amplifier component /
6c4df324	42	SOF_COMP_MODULE_ADAPTER, /*< module adapter /
311ce4fe LG	43	/* keep FILEREAD/FILEWRITE as the last ones */
	44	SOF_COMP_FILEREAD = 10000, /*< host test based file IO /
	45	SOF_COMP_FILEWRITE = 10001, /*< host test based file IO /
	46	};
	47
	48	/* XRUN action for component */
	49	#define SOF_XRUN_STOP 1 /*< stop stream /
	50	#define SOF_XRUN_UNDER_ZERO 2 /*< send 0s to sink /
	51	#define SOF_XRUN_OVER_NULL 4 /*< send data to NULL /
	52
	53	/* create new generic component - SOF_IPC_TPLG_COMP_NEW */
	54	struct sof_ipc_comp {
	55	struct sof_ipc_cmd_hdr hdr;
	56	uint32_t id;
	57	enum sof_comp_type type;
	58	uint32_t pipeline_id;
1a2289fd	59	uint32_t core;
311ce4fe	60
50b55fd4 KJ	61	/* extended data length, 0 if no extended data */
50b55fd4 KJ	62	uint32_t ext_data_length;
8ec56af3	63	} __packed __aligned(4);
311ce4fe LG	64
	65	/*
	66	* Component Buffers
	67	*/
	68
	69	/*
	70	* SOF memory capabilities, add new ones at the end
	71	*/
6c4df324 BT	72	#define SOF_MEM_CAPS_RAM BIT(0)
	73	#define SOF_MEM_CAPS_ROM BIT(1)
	74	#define SOF_MEM_CAPS_EXT BIT(2) /*< external /
	75	#define SOF_MEM_CAPS_LP BIT(3) /*< low power /
	76	#define SOF_MEM_CAPS_HP BIT(4) /*< high performance /
	77	#define SOF_MEM_CAPS_DMA BIT(5) /*< DMA'able /
	78	#define SOF_MEM_CAPS_CACHE BIT(6) /*< cacheable /
	79	#define SOF_MEM_CAPS_EXEC BIT(7) /*< executable /
	80	#define SOF_MEM_CAPS_L3 BIT(8) /*< L3 memory /
311ce4fe	81
7893df67 AK	82	/*
	83	* overrun will cause ring buffer overwrite, instead of XRUN.
	84	*/
	85	#define SOF_BUF_OVERRUN_PERMITTED BIT(0)
	86
	87	/*
	88	* underrun will cause readback of 0s, instead of XRUN.
	89	*/
	90	#define SOF_BUF_UNDERRUN_PERMITTED BIT(1)
	91
6c4df324 BT	92	/* the UUID size in bytes, shared between FW and host */
	93	#define SOF_UUID_SIZE 16
	94
311ce4fe LG	95	/* create new component buffer - SOF_IPC_TPLG_BUFFER_NEW */
	96	struct sof_ipc_buffer {
	97	struct sof_ipc_comp comp;
	98	uint32_t size; /*< buffer size in bytes /
	99	uint32_t caps; /*< SOF_MEM_CAPS_ /
7893df67 AK	100	uint32_t flags; /*< SOF_BUF_ flags defined above /
7893df67 AK	101	uint32_t reserved; /*< reserved for future use /
8ec56af3	102	} __packed __aligned(4);
311ce4fe LG	103
	104	/* generic component config data - must always be after struct sof_ipc_comp */
	105	struct sof_ipc_comp_config {
	106	struct sof_ipc_cmd_hdr hdr;
	107	uint32_t periods_sink; /*< 0 means variable /
b943f798	108	uint32_t periods_source;/*< 0 means variable /
311ce4fe	109	uint32_t reserved1; /*< reserved /
b943f798	110	uint32_t frame_fmt; /*< SOF_IPC_FRAME_ /
311ce4fe LG	111	uint32_t xrun_action;
	112
	113	/* reserved for future use */
	114	uint32_t reserved[2];
8ec56af3	115	} __packed __aligned(4);
311ce4fe LG	116
	117	/* generic host component */
	118	struct sof_ipc_comp_host {
	119	struct sof_ipc_comp comp;
	120	struct sof_ipc_comp_config config;
	121	uint32_t direction; /*< SOF_IPC_STREAM_ /
	122	uint32_t no_irq; /*< don't send periodic IRQ to host/DSP /
	123	uint32_t dmac_config; /*< DMA engine specific /
8ec56af3	124	} __packed __aligned(4);
311ce4fe LG	125
	126	/* generic DAI component */
	127	struct sof_ipc_comp_dai {
	128	struct sof_ipc_comp comp;
	129	struct sof_ipc_comp_config config;
	130	uint32_t direction; /*< SOF_IPC_STREAM_ /
	131	uint32_t dai_index; /*< index of this type dai /
	132	uint32_t type; /*< DAI type - SOF_DAI_ /
	133	uint32_t reserved; /*< reserved /
8ec56af3	134	} __packed __aligned(4);
311ce4fe LG	135
	136	/* generic mixer component */
	137	struct sof_ipc_comp_mixer {
	138	struct sof_ipc_comp comp;
	139	struct sof_ipc_comp_config config;
8ec56af3	140	} __packed __aligned(4);
311ce4fe LG	141
	142	/* volume ramping types */
	143	enum sof_volume_ramp {
	144	SOF_VOLUME_LINEAR = 0,
	145	SOF_VOLUME_LOG,
	146	SOF_VOLUME_LINEAR_ZC,
	147	SOF_VOLUME_LOG_ZC,
6c4df324 BT	148	SOF_VOLUME_WINDOWS_FADE,
6c4df324 BT	149	SOF_VOLUME_WINDOWS_NO_FADE,
311ce4fe LG	150	};
	151
	152	/* generic volume component */
	153	struct sof_ipc_comp_volume {
	154	struct sof_ipc_comp comp;
	155	struct sof_ipc_comp_config config;
	156	uint32_t channels;
	157	uint32_t min_value;
	158	uint32_t max_value;
	159	uint32_t ramp; /*< SOF_VOLUME_ /
	160	uint32_t initial_ramp; /*< ramp space in ms /
8ec56af3	161	} __packed __aligned(4);
311ce4fe LG	162
	163	/* generic SRC component */
	164	struct sof_ipc_comp_src {
	165	struct sof_ipc_comp comp;
	166	struct sof_ipc_comp_config config;
	167	/* either source or sink rate must be non zero */
	168	uint32_t source_rate; /*< source rate or 0 for variable /
	169	uint32_t sink_rate; /*< sink rate or 0 for variable /
	170	uint32_t rate_mask; /*< SOF_RATE_ supported rates /
8ec56af3	171	} __packed __aligned(4);
311ce4fe	172
433363e7 SI	173	/* generic ASRC component */
	174	struct sof_ipc_comp_asrc {
	175	struct sof_ipc_comp comp;
	176	struct sof_ipc_comp_config config;
	177	/* either source or sink rate must be non zero */
	178	uint32_t source_rate; /*< Define fixed source rate or /
	179	/*< use 0 to indicate need to get /
	180	/*< the rate from stream /
	181	uint32_t sink_rate; /*< Define fixed sink rate or /
	182	/*< use 0 to indicate need to get /
	183	/*< the rate from stream /
	184	uint32_t asynchronous_mode; /*< synchronous 0, asynchronous 1 /
	185	/*< When 1 the ASRC tracks and /
	186	/*< compensates for drift. /
	187	uint32_t operation_mode; /*< push 0, pull 1, In push mode the /
	188	/*< ASRC consumes a defined number /
	189	/*< of frames at input, with varying /
	190	/*< number of frames at output. /
	191	/*< In pull mode the ASRC outputs /
	192	/*< a defined number of frames while /
	193	/*< number of input frames varies. /
	194
	195	/* reserved for future use */
	196	uint32_t reserved[4];
8ec56af3	197	} __packed __aligned(4);
433363e7	198
311ce4fe LG	199	/* generic MUX component */
	200	struct sof_ipc_comp_mux {
	201	struct sof_ipc_comp comp;
	202	struct sof_ipc_comp_config config;
8ec56af3	203	} __packed __aligned(4);
311ce4fe LG	204
	205	/* generic tone generator component */
	206	struct sof_ipc_comp_tone {
	207	struct sof_ipc_comp comp;
	208	struct sof_ipc_comp_config config;
	209	int32_t sample_rate;
	210	int32_t frequency;
	211	int32_t amplitude;
	212	int32_t freq_mult;
	213	int32_t ampl_mult;
	214	int32_t length;
	215	int32_t period;
	216	int32_t repeats;
	217	int32_t ramp_step;
8ec56af3	218	} __packed __aligned(4);
311ce4fe LG	219
	220	/** \brief Types of processing components */
	221	enum sof_ipc_process_type {
	222	SOF_PROCESS_NONE = 0, /*< None /
	223	SOF_PROCESS_EQFIR, /*< Intel FIR /
	224	SOF_PROCESS_EQIIR, /*< Intel IIR /
	225	SOF_PROCESS_KEYWORD_DETECT, /*< Keyword Detection /
	226	SOF_PROCESS_KPB, /*< KeyPhrase Buffer Manager /
	227	SOF_PROCESS_CHAN_SELECTOR, /*< Channel Selector /
66358069 JU	228	SOF_PROCESS_MUX,
66358069 JU	229	SOF_PROCESS_DEMUX,
542adb2a	230	SOF_PROCESS_DCBLOCK,
82e8c00f	231	SOF_PROCESS_SMART_AMP, /*< Smart Amplifier /
311ce4fe LG	232	};
	233
	234	/* generic "effect", "codec" or proprietary processing component */
	235	struct sof_ipc_comp_process {
	236	struct sof_ipc_comp comp;
	237	struct sof_ipc_comp_config config;
	238	uint32_t size; /*< size of bespoke data section in bytes /
	239	uint32_t type; /*< sof_ipc_process_type /
	240
	241	/* reserved for future use */
	242	uint32_t reserved[7];
	243
6c4df324	244	unsigned char data[];
8ec56af3	245	} __packed __aligned(4);
311ce4fe LG	246
	247	/* frees components, buffers and pipelines
	248	* SOF_IPC_TPLG_COMP_FREE, SOF_IPC_TPLG_PIPE_FREE, SOF_IPC_TPLG_BUFFER_FREE
	249	*/
	250	struct sof_ipc_free {
	251	struct sof_ipc_cmd_hdr hdr;
	252	uint32_t id;
8ec56af3	253	} __packed __aligned(4);
311ce4fe LG	254
	255	struct sof_ipc_comp_reply {
	256	struct sof_ipc_reply rhdr;
	257	uint32_t id;
	258	uint32_t offset;
8ec56af3	259	} __packed __aligned(4);
311ce4fe LG	260
	261	/*
	262	* Pipeline
	263	*/
	264
	265	/** \brief Types of pipeline scheduling time domains */
	266	enum sof_ipc_pipe_sched_time_domain {
	267	SOF_TIME_DOMAIN_DMA = 0, /*< DMA interrupt /
	268	SOF_TIME_DOMAIN_TIMER, /*< Timer interrupt /
	269	};
	270
	271	/* new pipeline - SOF_IPC_TPLG_PIPE_NEW */
	272	struct sof_ipc_pipe_new {
	273	struct sof_ipc_cmd_hdr hdr;
	274	uint32_t comp_id; /*< component id for pipeline /
	275	uint32_t pipeline_id; /*< pipeline id /
	276	uint32_t sched_id; /*< Scheduling component id /
	277	uint32_t core; /*< core we run on /
	278	uint32_t period; /*< execution period in us/
	279	uint32_t priority; /*< priority level 0 (low) to 10 (max) /
	280	uint32_t period_mips; /*< worst case instruction count per period /
	281	uint32_t frames_per_sched;/*< output frames of pipeline, 0 is variable /
	282	uint32_t xrun_limit_usecs; /*< report xruns greater than limit /
	283	uint32_t time_domain; /*< scheduling time domain /
8ec56af3	284	} __packed __aligned(4);
311ce4fe LG	285
	286	/* pipeline construction complete - SOF_IPC_TPLG_PIPE_COMPLETE */
	287	struct sof_ipc_pipe_ready {
	288	struct sof_ipc_cmd_hdr hdr;
	289	uint32_t comp_id;
8ec56af3	290	} __packed __aligned(4);
311ce4fe LG	291
	292	struct sof_ipc_pipe_free {
	293	struct sof_ipc_cmd_hdr hdr;
	294	uint32_t comp_id;
8ec56af3	295	} __packed __aligned(4);
311ce4fe LG	296
	297	/* connect two components in pipeline - SOF_IPC_TPLG_COMP_CONNECT */
	298	struct sof_ipc_pipe_comp_connect {
	299	struct sof_ipc_cmd_hdr hdr;
	300	uint32_t source_id;
	301	uint32_t sink_id;
8ec56af3	302	} __packed __aligned(4);
311ce4fe LG	303
	304	/* external events */
	305	enum sof_event_types {
	306	SOF_EVENT_NONE = 0,
	307	SOF_KEYWORD_DETECT_DAPM_EVENT,
	308	};
	309
	310	#endif