Commit | Line | Data |
---|---|---|
b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
e3d280fc TI |
2 | /* |
3 | * HD-audio core stuff | |
4 | */ | |
5 | ||
6 | #ifndef __SOUND_HDAUDIO_H | |
7 | #define __SOUND_HDAUDIO_H | |
8 | ||
9 | #include <linux/device.h> | |
14752412 | 10 | #include <linux/interrupt.h> |
feb20fae | 11 | #include <linux/pm_runtime.h> |
14752412 TI |
12 | #include <linux/timecounter.h> |
13 | #include <sound/core.h> | |
a6ea5fe9 | 14 | #include <sound/pcm.h> |
14752412 | 15 | #include <sound/memalloc.h> |
d068ebc2 | 16 | #include <sound/hda_verbs.h> |
98d8fc6c | 17 | #include <drm/i915_component.h> |
d068ebc2 | 18 | |
7639a06c TI |
19 | /* codec node id */ |
20 | typedef u16 hda_nid_t; | |
21 | ||
d068ebc2 | 22 | struct hdac_bus; |
14752412 | 23 | struct hdac_stream; |
d068ebc2 TI |
24 | struct hdac_device; |
25 | struct hdac_driver; | |
3256be65 | 26 | struct hdac_widget_tree; |
da23ac1e | 27 | struct hda_device_id; |
e3d280fc TI |
28 | |
29 | /* | |
30 | * exported bus type | |
31 | */ | |
32 | extern struct bus_type snd_hda_bus_type; | |
33 | ||
71fc4c7e TI |
34 | /* |
35 | * generic arrays | |
36 | */ | |
37 | struct snd_array { | |
38 | unsigned int used; | |
39 | unsigned int alloced; | |
40 | unsigned int elem_size; | |
41 | unsigned int alloc_align; | |
42 | void *list; | |
43 | }; | |
44 | ||
e3d280fc TI |
45 | /* |
46 | * HD-audio codec base device | |
47 | */ | |
48 | struct hdac_device { | |
49 | struct device dev; | |
50 | int type; | |
d068ebc2 TI |
51 | struct hdac_bus *bus; |
52 | unsigned int addr; /* codec address */ | |
53 | struct list_head list; /* list point for bus codec_list */ | |
7639a06c TI |
54 | |
55 | hda_nid_t afg; /* AFG node id */ | |
56 | hda_nid_t mfg; /* MFG node id */ | |
57 | ||
58 | /* ids */ | |
59 | unsigned int vendor_id; | |
60 | unsigned int subsystem_id; | |
61 | unsigned int revision_id; | |
62 | unsigned int afg_function_id; | |
63 | unsigned int mfg_function_id; | |
64 | unsigned int afg_unsol:1; | |
65 | unsigned int mfg_unsol:1; | |
66 | ||
67 | unsigned int power_caps; /* FG power caps */ | |
68 | ||
69 | const char *vendor_name; /* codec vendor name */ | |
70 | const char *chip_name; /* codec chip name */ | |
71 | ||
05852448 TI |
72 | /* verb exec op override */ |
73 | int (*exec_verb)(struct hdac_device *dev, unsigned int cmd, | |
74 | unsigned int flags, unsigned int *res); | |
75 | ||
7639a06c TI |
76 | /* widgets */ |
77 | unsigned int num_nodes; | |
78 | hda_nid_t start_nid, end_nid; | |
79 | ||
80 | /* misc flags */ | |
81 | atomic_t in_pm; /* suspend/resume being performed */ | |
3256be65 TI |
82 | |
83 | /* sysfs */ | |
84 | struct hdac_widget_tree *widgets; | |
4d75faa0 TI |
85 | |
86 | /* regmap */ | |
87 | struct regmap *regmap; | |
5e56bcea | 88 | struct snd_array vendor_verbs; |
4d75faa0 | 89 | bool lazy_cache:1; /* don't wake up for writes */ |
faa75f8a | 90 | bool caps_overwriting:1; /* caps overwrite being in process */ |
40ba66a7 | 91 | bool cache_coef:1; /* cache COEF read/write too */ |
e3d280fc TI |
92 | }; |
93 | ||
94 | /* device/driver type used for matching */ | |
95 | enum { | |
96 | HDA_DEV_CORE, | |
97 | HDA_DEV_LEGACY, | |
c1cc18b1 | 98 | HDA_DEV_ASOC, |
e3d280fc TI |
99 | }; |
100 | ||
d82b51c8 PLB |
101 | enum { |
102 | SND_SKL_PCI_BIND_AUTO, /* automatic selection based on pci class */ | |
103 | SND_SKL_PCI_BIND_LEGACY,/* bind only with legacy driver */ | |
104 | SND_SKL_PCI_BIND_ASOC /* bind only with ASoC driver */ | |
105 | }; | |
106 | ||
7639a06c TI |
107 | /* direction */ |
108 | enum { | |
109 | HDA_INPUT, HDA_OUTPUT | |
110 | }; | |
111 | ||
e3d280fc TI |
112 | #define dev_to_hdac_dev(_dev) container_of(_dev, struct hdac_device, dev) |
113 | ||
7639a06c TI |
114 | int snd_hdac_device_init(struct hdac_device *dev, struct hdac_bus *bus, |
115 | const char *name, unsigned int addr); | |
116 | void snd_hdac_device_exit(struct hdac_device *dev); | |
3256be65 TI |
117 | int snd_hdac_device_register(struct hdac_device *codec); |
118 | void snd_hdac_device_unregister(struct hdac_device *codec); | |
ded255be | 119 | int snd_hdac_device_set_chip_name(struct hdac_device *codec, const char *name); |
4f9e0c38 | 120 | int snd_hdac_codec_modalias(struct hdac_device *hdac, char *buf, size_t size); |
7639a06c | 121 | |
9780ded3 | 122 | int snd_hdac_refresh_widgets(struct hdac_device *codec, bool sysfs); |
7639a06c TI |
123 | |
124 | unsigned int snd_hdac_make_cmd(struct hdac_device *codec, hda_nid_t nid, | |
125 | unsigned int verb, unsigned int parm); | |
05852448 TI |
126 | int snd_hdac_exec_verb(struct hdac_device *codec, unsigned int cmd, |
127 | unsigned int flags, unsigned int *res); | |
7639a06c TI |
128 | int snd_hdac_read(struct hdac_device *codec, hda_nid_t nid, |
129 | unsigned int verb, unsigned int parm, unsigned int *res); | |
01ed3c06 TI |
130 | int _snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid, int parm, |
131 | unsigned int *res); | |
9ba17b4d TI |
132 | int snd_hdac_read_parm_uncached(struct hdac_device *codec, hda_nid_t nid, |
133 | int parm); | |
faa75f8a TI |
134 | int snd_hdac_override_parm(struct hdac_device *codec, hda_nid_t nid, |
135 | unsigned int parm, unsigned int val); | |
7639a06c TI |
136 | int snd_hdac_get_connections(struct hdac_device *codec, hda_nid_t nid, |
137 | hda_nid_t *conn_list, int max_conns); | |
138 | int snd_hdac_get_sub_nodes(struct hdac_device *codec, hda_nid_t nid, | |
139 | hda_nid_t *start_id); | |
b7d023e1 TI |
140 | unsigned int snd_hdac_calc_stream_format(unsigned int rate, |
141 | unsigned int channels, | |
a6ea5fe9 | 142 | snd_pcm_format_t format, |
b7d023e1 TI |
143 | unsigned int maxbps, |
144 | unsigned short spdif_ctls); | |
145 | int snd_hdac_query_supported_pcm(struct hdac_device *codec, hda_nid_t nid, | |
146 | u32 *ratesp, u64 *formatsp, unsigned int *bpsp); | |
147 | bool snd_hdac_is_supported_format(struct hdac_device *codec, hda_nid_t nid, | |
148 | unsigned int format); | |
7639a06c | 149 | |
1b5e6167 SP |
150 | int snd_hdac_codec_read(struct hdac_device *hdac, hda_nid_t nid, |
151 | int flags, unsigned int verb, unsigned int parm); | |
152 | int snd_hdac_codec_write(struct hdac_device *hdac, hda_nid_t nid, | |
153 | int flags, unsigned int verb, unsigned int parm); | |
154 | bool snd_hdac_check_power_state(struct hdac_device *hdac, | |
155 | hda_nid_t nid, unsigned int target_state); | |
09787492 AK |
156 | unsigned int snd_hdac_sync_power_state(struct hdac_device *hdac, |
157 | hda_nid_t nid, unsigned int target_state); | |
01ed3c06 TI |
158 | /** |
159 | * snd_hdac_read_parm - read a codec parameter | |
160 | * @codec: the codec object | |
161 | * @nid: NID to read a parameter | |
162 | * @parm: parameter to read | |
163 | * | |
164 | * Returns -1 for error. If you need to distinguish the error more | |
165 | * strictly, use _snd_hdac_read_parm() directly. | |
166 | */ | |
167 | static inline int snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid, | |
168 | int parm) | |
169 | { | |
170 | unsigned int val; | |
171 | ||
172 | return _snd_hdac_read_parm(codec, nid, parm, &val) < 0 ? -1 : val; | |
173 | } | |
174 | ||
7639a06c | 175 | #ifdef CONFIG_PM |
fbce23a0 TI |
176 | int snd_hdac_power_up(struct hdac_device *codec); |
177 | int snd_hdac_power_down(struct hdac_device *codec); | |
178 | int snd_hdac_power_up_pm(struct hdac_device *codec); | |
179 | int snd_hdac_power_down_pm(struct hdac_device *codec); | |
fc4f000b | 180 | int snd_hdac_keep_power_up(struct hdac_device *codec); |
feb20fae TI |
181 | |
182 | /* call this at entering into suspend/resume callbacks in codec driver */ | |
183 | static inline void snd_hdac_enter_pm(struct hdac_device *codec) | |
184 | { | |
185 | atomic_inc(&codec->in_pm); | |
186 | } | |
187 | ||
188 | /* call this at leaving from suspend/resume callbacks in codec driver */ | |
189 | static inline void snd_hdac_leave_pm(struct hdac_device *codec) | |
190 | { | |
191 | atomic_dec(&codec->in_pm); | |
192 | } | |
193 | ||
194 | static inline bool snd_hdac_is_in_pm(struct hdac_device *codec) | |
195 | { | |
196 | return atomic_read(&codec->in_pm); | |
197 | } | |
198 | ||
199 | static inline bool snd_hdac_is_power_on(struct hdac_device *codec) | |
200 | { | |
201 | return !pm_runtime_suspended(&codec->dev); | |
202 | } | |
7639a06c | 203 | #else |
fbce23a0 TI |
204 | static inline int snd_hdac_power_up(struct hdac_device *codec) { return 0; } |
205 | static inline int snd_hdac_power_down(struct hdac_device *codec) { return 0; } | |
206 | static inline int snd_hdac_power_up_pm(struct hdac_device *codec) { return 0; } | |
207 | static inline int snd_hdac_power_down_pm(struct hdac_device *codec) { return 0; } | |
fc4f000b | 208 | static inline int snd_hdac_keep_power_up(struct hdac_device *codec) { return 0; } |
feb20fae TI |
209 | static inline void snd_hdac_enter_pm(struct hdac_device *codec) {} |
210 | static inline void snd_hdac_leave_pm(struct hdac_device *codec) {} | |
211 | static inline bool snd_hdac_is_in_pm(struct hdac_device *codec) { return 0; } | |
212 | static inline bool snd_hdac_is_power_on(struct hdac_device *codec) { return 1; } | |
7639a06c TI |
213 | #endif |
214 | ||
e3d280fc TI |
215 | /* |
216 | * HD-audio codec base driver | |
217 | */ | |
218 | struct hdac_driver { | |
219 | struct device_driver driver; | |
220 | int type; | |
ec71efc9 | 221 | const struct hda_device_id *id_table; |
e3d280fc | 222 | int (*match)(struct hdac_device *dev, struct hdac_driver *drv); |
d068ebc2 | 223 | void (*unsol_event)(struct hdac_device *dev, unsigned int event); |
e1df9317 RU |
224 | |
225 | /* fields used by ext bus APIs */ | |
226 | int (*probe)(struct hdac_device *dev); | |
227 | int (*remove)(struct hdac_device *dev); | |
228 | void (*shutdown)(struct hdac_device *dev); | |
e3d280fc TI |
229 | }; |
230 | ||
231 | #define drv_to_hdac_driver(_drv) container_of(_drv, struct hdac_driver, driver) | |
232 | ||
ec71efc9 VK |
233 | const struct hda_device_id * |
234 | hdac_get_device_id(struct hdac_device *hdev, struct hdac_driver *drv); | |
235 | ||
d068ebc2 | 236 | /* |
14752412 | 237 | * Bus verb operators |
d068ebc2 TI |
238 | */ |
239 | struct hdac_bus_ops { | |
240 | /* send a single command */ | |
241 | int (*command)(struct hdac_bus *bus, unsigned int cmd); | |
242 | /* get a response from the last command */ | |
243 | int (*get_response)(struct hdac_bus *bus, unsigned int addr, | |
244 | unsigned int *res); | |
245 | }; | |
246 | ||
cb04ba33 RU |
247 | /* |
248 | * ops used for ASoC HDA codec drivers | |
249 | */ | |
250 | struct hdac_ext_bus_ops { | |
251 | int (*hdev_attach)(struct hdac_device *hdev); | |
252 | int (*hdev_detach)(struct hdac_device *hdev); | |
253 | }; | |
254 | ||
14752412 TI |
255 | /* |
256 | * Lowlevel I/O operators | |
257 | */ | |
258 | struct hdac_io_ops { | |
259 | /* mapped register accesses */ | |
260 | void (*reg_writel)(u32 value, u32 __iomem *addr); | |
261 | u32 (*reg_readl)(u32 __iomem *addr); | |
262 | void (*reg_writew)(u16 value, u16 __iomem *addr); | |
263 | u16 (*reg_readw)(u16 __iomem *addr); | |
264 | void (*reg_writeb)(u8 value, u8 __iomem *addr); | |
265 | u8 (*reg_readb)(u8 __iomem *addr); | |
8f3f600b TI |
266 | /* Allocation ops */ |
267 | int (*dma_alloc_pages)(struct hdac_bus *bus, int type, size_t size, | |
268 | struct snd_dma_buffer *buf); | |
269 | void (*dma_free_pages)(struct hdac_bus *bus, | |
270 | struct snd_dma_buffer *buf); | |
14752412 TI |
271 | }; |
272 | ||
d068ebc2 | 273 | #define HDA_UNSOL_QUEUE_SIZE 64 |
14752412 TI |
274 | #define HDA_MAX_CODECS 8 /* limit by controller side */ |
275 | ||
14752412 TI |
276 | /* |
277 | * CORB/RIRB | |
278 | * | |
279 | * Each CORB entry is 4byte, RIRB is 8byte | |
280 | */ | |
281 | struct hdac_rb { | |
282 | __le32 *buf; /* virtual address of CORB/RIRB buffer */ | |
283 | dma_addr_t addr; /* physical address of CORB/RIRB buffer */ | |
284 | unsigned short rp, wp; /* RIRB read/write pointers */ | |
285 | int cmds[HDA_MAX_CODECS]; /* number of pending requests */ | |
286 | u32 res[HDA_MAX_CODECS]; /* last read value */ | |
287 | }; | |
d068ebc2 | 288 | |
14752412 TI |
289 | /* |
290 | * HD-audio bus base driver | |
6720b384 VK |
291 | * |
292 | * @ppcap: pp capabilities pointer | |
293 | * @spbcap: SPIB capabilities pointer | |
294 | * @mlcap: MultiLink capabilities pointer | |
295 | * @gtscap: gts capabilities pointer | |
296 | * @drsmcap: dma resume capabilities pointer | |
76f56fae RU |
297 | * @num_streams: streams supported |
298 | * @idx: HDA link index | |
299 | * @hlink_list: link list of HDA links | |
300 | * @lock: lock for link mgmt | |
301 | * @cmd_dma_state: state of cmd DMAs: CORB and RIRB | |
14752412 | 302 | */ |
d068ebc2 TI |
303 | struct hdac_bus { |
304 | struct device *dev; | |
305 | const struct hdac_bus_ops *ops; | |
14752412 | 306 | const struct hdac_io_ops *io_ops; |
cb04ba33 | 307 | const struct hdac_ext_bus_ops *ext_ops; |
14752412 TI |
308 | |
309 | /* h/w resources */ | |
310 | unsigned long addr; | |
311 | void __iomem *remap_addr; | |
312 | int irq; | |
d068ebc2 | 313 | |
6720b384 VK |
314 | void __iomem *ppcap; |
315 | void __iomem *spbcap; | |
316 | void __iomem *mlcap; | |
317 | void __iomem *gtscap; | |
318 | void __iomem *drsmcap; | |
319 | ||
d068ebc2 TI |
320 | /* codec linked list */ |
321 | struct list_head codec_list; | |
322 | unsigned int num_codecs; | |
323 | ||
324 | /* link caddr -> codec */ | |
325 | struct hdac_device *caddr_tbl[HDA_MAX_CODEC_ADDRESS + 1]; | |
326 | ||
327 | /* unsolicited event queue */ | |
328 | u32 unsol_queue[HDA_UNSOL_QUEUE_SIZE * 2]; /* ring buffer */ | |
329 | unsigned int unsol_rp, unsol_wp; | |
330 | struct work_struct unsol_work; | |
331 | ||
14752412 TI |
332 | /* bit flags of detected codecs */ |
333 | unsigned long codec_mask; | |
334 | ||
d068ebc2 TI |
335 | /* bit flags of powered codecs */ |
336 | unsigned long codec_powered; | |
337 | ||
14752412 TI |
338 | /* CORB/RIRB */ |
339 | struct hdac_rb corb; | |
340 | struct hdac_rb rirb; | |
341 | unsigned int last_cmd[HDA_MAX_CODECS]; /* last sent command */ | |
342 | ||
343 | /* CORB/RIRB and position buffers */ | |
344 | struct snd_dma_buffer rb; | |
345 | struct snd_dma_buffer posbuf; | |
346 | ||
347 | /* hdac_stream linked list */ | |
348 | struct list_head stream_list; | |
349 | ||
350 | /* operation state */ | |
351 | bool chip_init:1; /* h/w initialized */ | |
352 | ||
353 | /* behavior flags */ | |
d068ebc2 | 354 | bool sync_write:1; /* sync after verb write */ |
14752412 TI |
355 | bool use_posbuf:1; /* use position buffer */ |
356 | bool snoop:1; /* enable snooping */ | |
357 | bool align_bdle_4k:1; /* BDLE align 4K boundary */ | |
358 | bool reverse_assign:1; /* assign devices in reverse order */ | |
359 | bool corbrp_self_clear:1; /* CORBRP clears itself after reset */ | |
360 | ||
361 | int bdl_pos_adj; /* BDL position adjustment */ | |
d068ebc2 TI |
362 | |
363 | /* locks */ | |
14752412 | 364 | spinlock_t reg_lock; |
d068ebc2 | 365 | struct mutex cmd_mutex; |
98d8fc6c | 366 | |
ae891abe TI |
367 | /* DRM component interface */ |
368 | struct drm_audio_component *audio_component; | |
029d92c2 TI |
369 | long display_power_status; |
370 | bool display_power_active; | |
76f56fae RU |
371 | |
372 | /* parameters required for enhanced capabilities */ | |
373 | int num_streams; | |
374 | int idx; | |
375 | ||
376 | struct list_head hlink_list; | |
377 | ||
378 | struct mutex lock; | |
379 | bool cmd_dma_state; | |
380 | ||
d068ebc2 TI |
381 | }; |
382 | ||
383 | int snd_hdac_bus_init(struct hdac_bus *bus, struct device *dev, | |
14752412 TI |
384 | const struct hdac_bus_ops *ops, |
385 | const struct hdac_io_ops *io_ops); | |
d068ebc2 TI |
386 | void snd_hdac_bus_exit(struct hdac_bus *bus); |
387 | int snd_hdac_bus_exec_verb(struct hdac_bus *bus, unsigned int addr, | |
388 | unsigned int cmd, unsigned int *res); | |
389 | int snd_hdac_bus_exec_verb_unlocked(struct hdac_bus *bus, unsigned int addr, | |
390 | unsigned int cmd, unsigned int *res); | |
391 | void snd_hdac_bus_queue_event(struct hdac_bus *bus, u32 res, u32 res_ex); | |
392 | ||
393 | int snd_hdac_bus_add_device(struct hdac_bus *bus, struct hdac_device *codec); | |
394 | void snd_hdac_bus_remove_device(struct hdac_bus *bus, | |
395 | struct hdac_device *codec); | |
18d43c9b | 396 | void snd_hdac_bus_process_unsol_events(struct work_struct *work); |
d068ebc2 | 397 | |
7639a06c TI |
398 | static inline void snd_hdac_codec_link_up(struct hdac_device *codec) |
399 | { | |
400 | set_bit(codec->addr, &codec->bus->codec_powered); | |
401 | } | |
402 | ||
403 | static inline void snd_hdac_codec_link_down(struct hdac_device *codec) | |
404 | { | |
405 | clear_bit(codec->addr, &codec->bus->codec_powered); | |
406 | } | |
407 | ||
14752412 TI |
408 | int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val); |
409 | int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr, | |
410 | unsigned int *res); | |
6720b384 | 411 | int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus); |
14752412 TI |
412 | |
413 | bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset); | |
414 | void snd_hdac_bus_stop_chip(struct hdac_bus *bus); | |
415 | void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus); | |
416 | void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus); | |
417 | void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus); | |
418 | void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus); | |
75383f8d | 419 | int snd_hdac_bus_reset_link(struct hdac_bus *bus, bool full_reset); |
14752412 TI |
420 | |
421 | void snd_hdac_bus_update_rirb(struct hdac_bus *bus); | |
473f4145 | 422 | int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status, |
14752412 TI |
423 | void (*ack)(struct hdac_bus *, |
424 | struct hdac_stream *)); | |
425 | ||
304dad30 JK |
426 | int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus); |
427 | void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus); | |
428 | ||
14752412 TI |
429 | /* |
430 | * macros for easy use | |
431 | */ | |
2c1f8138 TI |
432 | #define _snd_hdac_chip_writeb(chip, reg, value) \ |
433 | ((chip)->io_ops->reg_writeb(value, (chip)->remap_addr + (reg))) | |
434 | #define _snd_hdac_chip_readb(chip, reg) \ | |
435 | ((chip)->io_ops->reg_readb((chip)->remap_addr + (reg))) | |
436 | #define _snd_hdac_chip_writew(chip, reg, value) \ | |
437 | ((chip)->io_ops->reg_writew(value, (chip)->remap_addr + (reg))) | |
438 | #define _snd_hdac_chip_readw(chip, reg) \ | |
439 | ((chip)->io_ops->reg_readw((chip)->remap_addr + (reg))) | |
440 | #define _snd_hdac_chip_writel(chip, reg, value) \ | |
441 | ((chip)->io_ops->reg_writel(value, (chip)->remap_addr + (reg))) | |
442 | #define _snd_hdac_chip_readl(chip, reg) \ | |
443 | ((chip)->io_ops->reg_readl((chip)->remap_addr + (reg))) | |
14752412 TI |
444 | |
445 | /* read/write a register, pass without AZX_REG_ prefix */ | |
446 | #define snd_hdac_chip_writel(chip, reg, value) \ | |
2c1f8138 | 447 | _snd_hdac_chip_writel(chip, AZX_REG_ ## reg, value) |
14752412 | 448 | #define snd_hdac_chip_writew(chip, reg, value) \ |
2c1f8138 | 449 | _snd_hdac_chip_writew(chip, AZX_REG_ ## reg, value) |
14752412 | 450 | #define snd_hdac_chip_writeb(chip, reg, value) \ |
2c1f8138 | 451 | _snd_hdac_chip_writeb(chip, AZX_REG_ ## reg, value) |
14752412 | 452 | #define snd_hdac_chip_readl(chip, reg) \ |
2c1f8138 | 453 | _snd_hdac_chip_readl(chip, AZX_REG_ ## reg) |
14752412 | 454 | #define snd_hdac_chip_readw(chip, reg) \ |
2c1f8138 | 455 | _snd_hdac_chip_readw(chip, AZX_REG_ ## reg) |
14752412 | 456 | #define snd_hdac_chip_readb(chip, reg) \ |
2c1f8138 | 457 | _snd_hdac_chip_readb(chip, AZX_REG_ ## reg) |
14752412 TI |
458 | |
459 | /* update a register, pass without AZX_REG_ prefix */ | |
460 | #define snd_hdac_chip_updatel(chip, reg, mask, val) \ | |
461 | snd_hdac_chip_writel(chip, reg, \ | |
462 | (snd_hdac_chip_readl(chip, reg) & ~(mask)) | (val)) | |
463 | #define snd_hdac_chip_updatew(chip, reg, mask, val) \ | |
464 | snd_hdac_chip_writew(chip, reg, \ | |
465 | (snd_hdac_chip_readw(chip, reg) & ~(mask)) | (val)) | |
466 | #define snd_hdac_chip_updateb(chip, reg, mask, val) \ | |
467 | snd_hdac_chip_writeb(chip, reg, \ | |
468 | (snd_hdac_chip_readb(chip, reg) & ~(mask)) | (val)) | |
469 | ||
470 | /* | |
471 | * HD-audio stream | |
472 | */ | |
473 | struct hdac_stream { | |
474 | struct hdac_bus *bus; | |
475 | struct snd_dma_buffer bdl; /* BDL buffer */ | |
476 | __le32 *posbuf; /* position buffer pointer */ | |
477 | int direction; /* playback / capture (SNDRV_PCM_STREAM_*) */ | |
478 | ||
479 | unsigned int bufsize; /* size of the play buffer in bytes */ | |
480 | unsigned int period_bytes; /* size of the period in bytes */ | |
481 | unsigned int frags; /* number for period in the play buffer */ | |
482 | unsigned int fifo_size; /* FIFO size */ | |
483 | ||
484 | void __iomem *sd_addr; /* stream descriptor pointer */ | |
485 | ||
486 | u32 sd_int_sta_mask; /* stream int status mask */ | |
487 | ||
488 | /* pcm support */ | |
489 | struct snd_pcm_substream *substream; /* assigned substream, | |
490 | * set in PCM open | |
491 | */ | |
492 | unsigned int format_val; /* format value to be set in the | |
493 | * controller and the codec | |
494 | */ | |
495 | unsigned char stream_tag; /* assigned stream */ | |
496 | unsigned char index; /* stream index */ | |
497 | int assigned_key; /* last device# key assigned to */ | |
498 | ||
499 | bool opened:1; | |
500 | bool running:1; | |
6d23c8f5 | 501 | bool prepared:1; |
14752412 | 502 | bool no_period_wakeup:1; |
8f3f600b | 503 | bool locked:1; |
14752412 TI |
504 | |
505 | /* timestamp */ | |
506 | unsigned long start_wallclk; /* start + minimum wallclk */ | |
507 | unsigned long period_wallclk; /* wallclk for period */ | |
508 | struct timecounter tc; | |
509 | struct cyclecounter cc; | |
510 | int delay_negative_threshold; | |
511 | ||
512 | struct list_head list; | |
8f3f600b TI |
513 | #ifdef CONFIG_SND_HDA_DSP_LOADER |
514 | /* DSP access mutex */ | |
515 | struct mutex dsp_mutex; | |
516 | #endif | |
14752412 TI |
517 | }; |
518 | ||
519 | void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev, | |
520 | int idx, int direction, int tag); | |
521 | struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus, | |
522 | struct snd_pcm_substream *substream); | |
523 | void snd_hdac_stream_release(struct hdac_stream *azx_dev); | |
4308c9b0 JK |
524 | struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus, |
525 | int dir, int stream_tag); | |
14752412 TI |
526 | |
527 | int snd_hdac_stream_setup(struct hdac_stream *azx_dev); | |
528 | void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev); | |
529 | int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev); | |
86f6501b JK |
530 | int snd_hdac_stream_set_params(struct hdac_stream *azx_dev, |
531 | unsigned int format_val); | |
14752412 TI |
532 | void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start); |
533 | void snd_hdac_stream_clear(struct hdac_stream *azx_dev); | |
534 | void snd_hdac_stream_stop(struct hdac_stream *azx_dev); | |
535 | void snd_hdac_stream_reset(struct hdac_stream *azx_dev); | |
536 | void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set, | |
537 | unsigned int streams, unsigned int reg); | |
538 | void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start, | |
539 | unsigned int streams); | |
540 | void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev, | |
541 | unsigned int streams); | |
5dd3d271 SP |
542 | int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus, |
543 | struct snd_pcm_substream *substream); | |
544 | ||
14752412 TI |
545 | /* |
546 | * macros for easy use | |
547 | */ | |
548 | #define _snd_hdac_stream_write(type, dev, reg, value) \ | |
549 | ((dev)->bus->io_ops->reg_write ## type(value, (dev)->sd_addr + (reg))) | |
550 | #define _snd_hdac_stream_read(type, dev, reg) \ | |
551 | ((dev)->bus->io_ops->reg_read ## type((dev)->sd_addr + (reg))) | |
552 | ||
553 | /* read/write a register, pass without AZX_REG_ prefix */ | |
554 | #define snd_hdac_stream_writel(dev, reg, value) \ | |
555 | _snd_hdac_stream_write(l, dev, AZX_REG_ ## reg, value) | |
556 | #define snd_hdac_stream_writew(dev, reg, value) \ | |
557 | _snd_hdac_stream_write(w, dev, AZX_REG_ ## reg, value) | |
558 | #define snd_hdac_stream_writeb(dev, reg, value) \ | |
559 | _snd_hdac_stream_write(b, dev, AZX_REG_ ## reg, value) | |
560 | #define snd_hdac_stream_readl(dev, reg) \ | |
561 | _snd_hdac_stream_read(l, dev, AZX_REG_ ## reg) | |
562 | #define snd_hdac_stream_readw(dev, reg) \ | |
563 | _snd_hdac_stream_read(w, dev, AZX_REG_ ## reg) | |
564 | #define snd_hdac_stream_readb(dev, reg) \ | |
565 | _snd_hdac_stream_read(b, dev, AZX_REG_ ## reg) | |
566 | ||
567 | /* update a register, pass without AZX_REG_ prefix */ | |
568 | #define snd_hdac_stream_updatel(dev, reg, mask, val) \ | |
569 | snd_hdac_stream_writel(dev, reg, \ | |
570 | (snd_hdac_stream_readl(dev, reg) & \ | |
571 | ~(mask)) | (val)) | |
572 | #define snd_hdac_stream_updatew(dev, reg, mask, val) \ | |
573 | snd_hdac_stream_writew(dev, reg, \ | |
574 | (snd_hdac_stream_readw(dev, reg) & \ | |
575 | ~(mask)) | (val)) | |
576 | #define snd_hdac_stream_updateb(dev, reg, mask, val) \ | |
577 | snd_hdac_stream_writeb(dev, reg, \ | |
578 | (snd_hdac_stream_readb(dev, reg) & \ | |
579 | ~(mask)) | (val)) | |
580 | ||
8f3f600b TI |
581 | #ifdef CONFIG_SND_HDA_DSP_LOADER |
582 | /* DSP lock helpers */ | |
583 | #define snd_hdac_dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex) | |
584 | #define snd_hdac_dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex) | |
585 | #define snd_hdac_dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex) | |
586 | #define snd_hdac_stream_is_locked(dev) ((dev)->locked) | |
587 | /* DSP loader helpers */ | |
588 | int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format, | |
589 | unsigned int byte_size, struct snd_dma_buffer *bufp); | |
590 | void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start); | |
591 | void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev, | |
592 | struct snd_dma_buffer *dmab); | |
593 | #else /* CONFIG_SND_HDA_DSP_LOADER */ | |
594 | #define snd_hdac_dsp_lock_init(dev) do {} while (0) | |
595 | #define snd_hdac_dsp_lock(dev) do {} while (0) | |
596 | #define snd_hdac_dsp_unlock(dev) do {} while (0) | |
597 | #define snd_hdac_stream_is_locked(dev) 0 | |
598 | ||
599 | static inline int | |
600 | snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format, | |
601 | unsigned int byte_size, struct snd_dma_buffer *bufp) | |
602 | { | |
603 | return 0; | |
604 | } | |
605 | ||
606 | static inline void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start) | |
607 | { | |
608 | } | |
609 | ||
610 | static inline void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev, | |
611 | struct snd_dma_buffer *dmab) | |
612 | { | |
613 | } | |
614 | #endif /* CONFIG_SND_HDA_DSP_LOADER */ | |
615 | ||
616 | ||
71fc4c7e TI |
617 | /* |
618 | * generic array helpers | |
619 | */ | |
620 | void *snd_array_new(struct snd_array *array); | |
621 | void snd_array_free(struct snd_array *array); | |
622 | static inline void snd_array_init(struct snd_array *array, unsigned int size, | |
623 | unsigned int align) | |
624 | { | |
625 | array->elem_size = size; | |
626 | array->alloc_align = align; | |
627 | } | |
628 | ||
629 | static inline void *snd_array_elem(struct snd_array *array, unsigned int idx) | |
630 | { | |
631 | return array->list + idx * array->elem_size; | |
632 | } | |
633 | ||
634 | static inline unsigned int snd_array_index(struct snd_array *array, void *ptr) | |
635 | { | |
636 | return (unsigned long)(ptr - array->list) / array->elem_size; | |
637 | } | |
638 | ||
a9c2dfc8 TI |
639 | /* a helper macro to iterate for each snd_array element */ |
640 | #define snd_array_for_each(array, idx, ptr) \ | |
641 | for ((idx) = 0, (ptr) = (array)->list; (idx) < (array)->used; \ | |
642 | (ptr) = snd_array_elem(array, ++(idx))) | |
643 | ||
e3d280fc | 644 | #endif /* __SOUND_HDAUDIO_H */ |