Commit | Line | Data |
---|---|---|
b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
e3d280fc TI |
2 | /* |
3 | * HD-audio core stuff | |
4 | */ | |
5 | ||
6 | #ifndef __SOUND_HDAUDIO_H | |
7 | #define __SOUND_HDAUDIO_H | |
8 | ||
9 | #include <linux/device.h> | |
14752412 | 10 | #include <linux/interrupt.h> |
feb20fae | 11 | #include <linux/pm_runtime.h> |
14752412 TI |
12 | #include <linux/timecounter.h> |
13 | #include <sound/core.h> | |
a6ea5fe9 | 14 | #include <sound/pcm.h> |
14752412 | 15 | #include <sound/memalloc.h> |
d068ebc2 | 16 | #include <sound/hda_verbs.h> |
98d8fc6c | 17 | #include <drm/i915_component.h> |
d068ebc2 | 18 | |
7639a06c TI |
19 | /* codec node id */ |
20 | typedef u16 hda_nid_t; | |
21 | ||
d068ebc2 | 22 | struct hdac_bus; |
14752412 | 23 | struct hdac_stream; |
d068ebc2 TI |
24 | struct hdac_device; |
25 | struct hdac_driver; | |
3256be65 | 26 | struct hdac_widget_tree; |
da23ac1e | 27 | struct hda_device_id; |
e3d280fc TI |
28 | |
29 | /* | |
30 | * exported bus type | |
31 | */ | |
32 | extern struct bus_type snd_hda_bus_type; | |
33 | ||
71fc4c7e TI |
34 | /* |
35 | * generic arrays | |
36 | */ | |
37 | struct snd_array { | |
38 | unsigned int used; | |
39 | unsigned int alloced; | |
40 | unsigned int elem_size; | |
41 | unsigned int alloc_align; | |
42 | void *list; | |
43 | }; | |
44 | ||
e3d280fc TI |
45 | /* |
46 | * HD-audio codec base device | |
47 | */ | |
48 | struct hdac_device { | |
49 | struct device dev; | |
50 | int type; | |
d068ebc2 TI |
51 | struct hdac_bus *bus; |
52 | unsigned int addr; /* codec address */ | |
53 | struct list_head list; /* list point for bus codec_list */ | |
7639a06c TI |
54 | |
55 | hda_nid_t afg; /* AFG node id */ | |
56 | hda_nid_t mfg; /* MFG node id */ | |
57 | ||
58 | /* ids */ | |
59 | unsigned int vendor_id; | |
60 | unsigned int subsystem_id; | |
61 | unsigned int revision_id; | |
62 | unsigned int afg_function_id; | |
63 | unsigned int mfg_function_id; | |
64 | unsigned int afg_unsol:1; | |
65 | unsigned int mfg_unsol:1; | |
66 | ||
67 | unsigned int power_caps; /* FG power caps */ | |
68 | ||
69 | const char *vendor_name; /* codec vendor name */ | |
70 | const char *chip_name; /* codec chip name */ | |
71 | ||
05852448 TI |
72 | /* verb exec op override */ |
73 | int (*exec_verb)(struct hdac_device *dev, unsigned int cmd, | |
74 | unsigned int flags, unsigned int *res); | |
75 | ||
7639a06c TI |
76 | /* widgets */ |
77 | unsigned int num_nodes; | |
78 | hda_nid_t start_nid, end_nid; | |
79 | ||
80 | /* misc flags */ | |
81 | atomic_t in_pm; /* suspend/resume being performed */ | |
3256be65 TI |
82 | |
83 | /* sysfs */ | |
ed180abb | 84 | struct mutex widget_lock; |
3256be65 | 85 | struct hdac_widget_tree *widgets; |
4d75faa0 TI |
86 | |
87 | /* regmap */ | |
88 | struct regmap *regmap; | |
5e56bcea | 89 | struct snd_array vendor_verbs; |
4d75faa0 | 90 | bool lazy_cache:1; /* don't wake up for writes */ |
faa75f8a | 91 | bool caps_overwriting:1; /* caps overwrite being in process */ |
40ba66a7 | 92 | bool cache_coef:1; /* cache COEF read/write too */ |
e3d280fc TI |
93 | }; |
94 | ||
95 | /* device/driver type used for matching */ | |
96 | enum { | |
97 | HDA_DEV_CORE, | |
98 | HDA_DEV_LEGACY, | |
c1cc18b1 | 99 | HDA_DEV_ASOC, |
e3d280fc TI |
100 | }; |
101 | ||
d82b51c8 PLB |
102 | enum { |
103 | SND_SKL_PCI_BIND_AUTO, /* automatic selection based on pci class */ | |
104 | SND_SKL_PCI_BIND_LEGACY,/* bind only with legacy driver */ | |
105 | SND_SKL_PCI_BIND_ASOC /* bind only with ASoC driver */ | |
106 | }; | |
107 | ||
7639a06c TI |
108 | /* direction */ |
109 | enum { | |
110 | HDA_INPUT, HDA_OUTPUT | |
111 | }; | |
112 | ||
e3d280fc TI |
113 | #define dev_to_hdac_dev(_dev) container_of(_dev, struct hdac_device, dev) |
114 | ||
7639a06c TI |
115 | int snd_hdac_device_init(struct hdac_device *dev, struct hdac_bus *bus, |
116 | const char *name, unsigned int addr); | |
117 | void snd_hdac_device_exit(struct hdac_device *dev); | |
3256be65 TI |
118 | int snd_hdac_device_register(struct hdac_device *codec); |
119 | void snd_hdac_device_unregister(struct hdac_device *codec); | |
ded255be | 120 | int snd_hdac_device_set_chip_name(struct hdac_device *codec, const char *name); |
4f9e0c38 | 121 | int snd_hdac_codec_modalias(struct hdac_device *hdac, char *buf, size_t size); |
7639a06c | 122 | |
774a075a | 123 | int snd_hdac_refresh_widgets(struct hdac_device *codec); |
7639a06c TI |
124 | |
125 | unsigned int snd_hdac_make_cmd(struct hdac_device *codec, hda_nid_t nid, | |
126 | unsigned int verb, unsigned int parm); | |
05852448 TI |
127 | int snd_hdac_exec_verb(struct hdac_device *codec, unsigned int cmd, |
128 | unsigned int flags, unsigned int *res); | |
7639a06c TI |
129 | int snd_hdac_read(struct hdac_device *codec, hda_nid_t nid, |
130 | unsigned int verb, unsigned int parm, unsigned int *res); | |
01ed3c06 TI |
131 | int _snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid, int parm, |
132 | unsigned int *res); | |
9ba17b4d TI |
133 | int snd_hdac_read_parm_uncached(struct hdac_device *codec, hda_nid_t nid, |
134 | int parm); | |
faa75f8a TI |
135 | int snd_hdac_override_parm(struct hdac_device *codec, hda_nid_t nid, |
136 | unsigned int parm, unsigned int val); | |
7639a06c TI |
137 | int snd_hdac_get_connections(struct hdac_device *codec, hda_nid_t nid, |
138 | hda_nid_t *conn_list, int max_conns); | |
139 | int snd_hdac_get_sub_nodes(struct hdac_device *codec, hda_nid_t nid, | |
140 | hda_nid_t *start_id); | |
b7d023e1 TI |
141 | unsigned int snd_hdac_calc_stream_format(unsigned int rate, |
142 | unsigned int channels, | |
a6ea5fe9 | 143 | snd_pcm_format_t format, |
b7d023e1 TI |
144 | unsigned int maxbps, |
145 | unsigned short spdif_ctls); | |
146 | int snd_hdac_query_supported_pcm(struct hdac_device *codec, hda_nid_t nid, | |
147 | u32 *ratesp, u64 *formatsp, unsigned int *bpsp); | |
148 | bool snd_hdac_is_supported_format(struct hdac_device *codec, hda_nid_t nid, | |
149 | unsigned int format); | |
7639a06c | 150 | |
1b5e6167 SP |
151 | int snd_hdac_codec_read(struct hdac_device *hdac, hda_nid_t nid, |
152 | int flags, unsigned int verb, unsigned int parm); | |
153 | int snd_hdac_codec_write(struct hdac_device *hdac, hda_nid_t nid, | |
154 | int flags, unsigned int verb, unsigned int parm); | |
155 | bool snd_hdac_check_power_state(struct hdac_device *hdac, | |
156 | hda_nid_t nid, unsigned int target_state); | |
09787492 AK |
157 | unsigned int snd_hdac_sync_power_state(struct hdac_device *hdac, |
158 | hda_nid_t nid, unsigned int target_state); | |
01ed3c06 TI |
159 | /** |
160 | * snd_hdac_read_parm - read a codec parameter | |
161 | * @codec: the codec object | |
162 | * @nid: NID to read a parameter | |
163 | * @parm: parameter to read | |
164 | * | |
165 | * Returns -1 for error. If you need to distinguish the error more | |
166 | * strictly, use _snd_hdac_read_parm() directly. | |
167 | */ | |
168 | static inline int snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid, | |
169 | int parm) | |
170 | { | |
171 | unsigned int val; | |
172 | ||
173 | return _snd_hdac_read_parm(codec, nid, parm, &val) < 0 ? -1 : val; | |
174 | } | |
175 | ||
7639a06c | 176 | #ifdef CONFIG_PM |
fbce23a0 TI |
177 | int snd_hdac_power_up(struct hdac_device *codec); |
178 | int snd_hdac_power_down(struct hdac_device *codec); | |
179 | int snd_hdac_power_up_pm(struct hdac_device *codec); | |
180 | int snd_hdac_power_down_pm(struct hdac_device *codec); | |
fc4f000b | 181 | int snd_hdac_keep_power_up(struct hdac_device *codec); |
feb20fae TI |
182 | |
183 | /* call this at entering into suspend/resume callbacks in codec driver */ | |
184 | static inline void snd_hdac_enter_pm(struct hdac_device *codec) | |
185 | { | |
186 | atomic_inc(&codec->in_pm); | |
187 | } | |
188 | ||
189 | /* call this at leaving from suspend/resume callbacks in codec driver */ | |
190 | static inline void snd_hdac_leave_pm(struct hdac_device *codec) | |
191 | { | |
192 | atomic_dec(&codec->in_pm); | |
193 | } | |
194 | ||
195 | static inline bool snd_hdac_is_in_pm(struct hdac_device *codec) | |
196 | { | |
197 | return atomic_read(&codec->in_pm); | |
198 | } | |
199 | ||
200 | static inline bool snd_hdac_is_power_on(struct hdac_device *codec) | |
201 | { | |
202 | return !pm_runtime_suspended(&codec->dev); | |
203 | } | |
7639a06c | 204 | #else |
fbce23a0 TI |
205 | static inline int snd_hdac_power_up(struct hdac_device *codec) { return 0; } |
206 | static inline int snd_hdac_power_down(struct hdac_device *codec) { return 0; } | |
207 | static inline int snd_hdac_power_up_pm(struct hdac_device *codec) { return 0; } | |
208 | static inline int snd_hdac_power_down_pm(struct hdac_device *codec) { return 0; } | |
fc4f000b | 209 | static inline int snd_hdac_keep_power_up(struct hdac_device *codec) { return 0; } |
feb20fae TI |
210 | static inline void snd_hdac_enter_pm(struct hdac_device *codec) {} |
211 | static inline void snd_hdac_leave_pm(struct hdac_device *codec) {} | |
212 | static inline bool snd_hdac_is_in_pm(struct hdac_device *codec) { return 0; } | |
213 | static inline bool snd_hdac_is_power_on(struct hdac_device *codec) { return 1; } | |
7639a06c TI |
214 | #endif |
215 | ||
e3d280fc TI |
216 | /* |
217 | * HD-audio codec base driver | |
218 | */ | |
219 | struct hdac_driver { | |
220 | struct device_driver driver; | |
221 | int type; | |
ec71efc9 | 222 | const struct hda_device_id *id_table; |
e3d280fc | 223 | int (*match)(struct hdac_device *dev, struct hdac_driver *drv); |
d068ebc2 | 224 | void (*unsol_event)(struct hdac_device *dev, unsigned int event); |
e1df9317 RU |
225 | |
226 | /* fields used by ext bus APIs */ | |
227 | int (*probe)(struct hdac_device *dev); | |
228 | int (*remove)(struct hdac_device *dev); | |
229 | void (*shutdown)(struct hdac_device *dev); | |
e3d280fc TI |
230 | }; |
231 | ||
232 | #define drv_to_hdac_driver(_drv) container_of(_drv, struct hdac_driver, driver) | |
233 | ||
ec71efc9 VK |
234 | const struct hda_device_id * |
235 | hdac_get_device_id(struct hdac_device *hdev, struct hdac_driver *drv); | |
236 | ||
d068ebc2 | 237 | /* |
14752412 | 238 | * Bus verb operators |
d068ebc2 TI |
239 | */ |
240 | struct hdac_bus_ops { | |
241 | /* send a single command */ | |
242 | int (*command)(struct hdac_bus *bus, unsigned int cmd); | |
243 | /* get a response from the last command */ | |
244 | int (*get_response)(struct hdac_bus *bus, unsigned int addr, | |
245 | unsigned int *res); | |
246 | }; | |
247 | ||
cb04ba33 RU |
248 | /* |
249 | * ops used for ASoC HDA codec drivers | |
250 | */ | |
251 | struct hdac_ext_bus_ops { | |
252 | int (*hdev_attach)(struct hdac_device *hdev); | |
253 | int (*hdev_detach)(struct hdac_device *hdev); | |
254 | }; | |
255 | ||
d068ebc2 | 256 | #define HDA_UNSOL_QUEUE_SIZE 64 |
14752412 TI |
257 | #define HDA_MAX_CODECS 8 /* limit by controller side */ |
258 | ||
14752412 TI |
259 | /* |
260 | * CORB/RIRB | |
261 | * | |
262 | * Each CORB entry is 4byte, RIRB is 8byte | |
263 | */ | |
264 | struct hdac_rb { | |
265 | __le32 *buf; /* virtual address of CORB/RIRB buffer */ | |
266 | dma_addr_t addr; /* physical address of CORB/RIRB buffer */ | |
267 | unsigned short rp, wp; /* RIRB read/write pointers */ | |
268 | int cmds[HDA_MAX_CODECS]; /* number of pending requests */ | |
269 | u32 res[HDA_MAX_CODECS]; /* last read value */ | |
270 | }; | |
d068ebc2 | 271 | |
14752412 TI |
272 | /* |
273 | * HD-audio bus base driver | |
6720b384 VK |
274 | * |
275 | * @ppcap: pp capabilities pointer | |
276 | * @spbcap: SPIB capabilities pointer | |
277 | * @mlcap: MultiLink capabilities pointer | |
278 | * @gtscap: gts capabilities pointer | |
279 | * @drsmcap: dma resume capabilities pointer | |
76f56fae RU |
280 | * @num_streams: streams supported |
281 | * @idx: HDA link index | |
282 | * @hlink_list: link list of HDA links | |
e61ab9f0 | 283 | * @lock: lock for link and display power mgmt |
76f56fae | 284 | * @cmd_dma_state: state of cmd DMAs: CORB and RIRB |
14752412 | 285 | */ |
d068ebc2 TI |
286 | struct hdac_bus { |
287 | struct device *dev; | |
288 | const struct hdac_bus_ops *ops; | |
cb04ba33 | 289 | const struct hdac_ext_bus_ops *ext_ops; |
14752412 TI |
290 | |
291 | /* h/w resources */ | |
292 | unsigned long addr; | |
293 | void __iomem *remap_addr; | |
294 | int irq; | |
d068ebc2 | 295 | |
6720b384 VK |
296 | void __iomem *ppcap; |
297 | void __iomem *spbcap; | |
298 | void __iomem *mlcap; | |
299 | void __iomem *gtscap; | |
300 | void __iomem *drsmcap; | |
301 | ||
d068ebc2 TI |
302 | /* codec linked list */ |
303 | struct list_head codec_list; | |
304 | unsigned int num_codecs; | |
305 | ||
306 | /* link caddr -> codec */ | |
307 | struct hdac_device *caddr_tbl[HDA_MAX_CODEC_ADDRESS + 1]; | |
308 | ||
309 | /* unsolicited event queue */ | |
310 | u32 unsol_queue[HDA_UNSOL_QUEUE_SIZE * 2]; /* ring buffer */ | |
311 | unsigned int unsol_rp, unsol_wp; | |
312 | struct work_struct unsol_work; | |
313 | ||
14752412 TI |
314 | /* bit flags of detected codecs */ |
315 | unsigned long codec_mask; | |
316 | ||
d068ebc2 TI |
317 | /* bit flags of powered codecs */ |
318 | unsigned long codec_powered; | |
319 | ||
14752412 TI |
320 | /* CORB/RIRB */ |
321 | struct hdac_rb corb; | |
322 | struct hdac_rb rirb; | |
323 | unsigned int last_cmd[HDA_MAX_CODECS]; /* last sent command */ | |
324 | ||
325 | /* CORB/RIRB and position buffers */ | |
326 | struct snd_dma_buffer rb; | |
327 | struct snd_dma_buffer posbuf; | |
619a1f19 | 328 | int dma_type; /* SNDRV_DMA_TYPE_XXX for CORB/RIRB */ |
14752412 TI |
329 | |
330 | /* hdac_stream linked list */ | |
331 | struct list_head stream_list; | |
332 | ||
333 | /* operation state */ | |
334 | bool chip_init:1; /* h/w initialized */ | |
335 | ||
336 | /* behavior flags */ | |
d068ebc2 | 337 | bool sync_write:1; /* sync after verb write */ |
14752412 TI |
338 | bool use_posbuf:1; /* use position buffer */ |
339 | bool snoop:1; /* enable snooping */ | |
340 | bool align_bdle_4k:1; /* BDLE align 4K boundary */ | |
341 | bool reverse_assign:1; /* assign devices in reverse order */ | |
342 | bool corbrp_self_clear:1; /* CORBRP clears itself after reset */ | |
8af42130 BL |
343 | bool polling_mode:1; |
344 | ||
345 | int poll_count; | |
14752412 TI |
346 | |
347 | int bdl_pos_adj; /* BDL position adjustment */ | |
d068ebc2 TI |
348 | |
349 | /* locks */ | |
14752412 | 350 | spinlock_t reg_lock; |
d068ebc2 | 351 | struct mutex cmd_mutex; |
e61ab9f0 | 352 | struct mutex lock; |
98d8fc6c | 353 | |
ae891abe TI |
354 | /* DRM component interface */ |
355 | struct drm_audio_component *audio_component; | |
029d92c2 | 356 | long display_power_status; |
d31c85fc | 357 | unsigned long display_power_active; |
76f56fae RU |
358 | |
359 | /* parameters required for enhanced capabilities */ | |
360 | int num_streams; | |
361 | int idx; | |
362 | ||
e61ab9f0 | 363 | /* link management */ |
76f56fae | 364 | struct list_head hlink_list; |
76f56fae | 365 | bool cmd_dma_state; |
d068ebc2 TI |
366 | }; |
367 | ||
368 | int snd_hdac_bus_init(struct hdac_bus *bus, struct device *dev, | |
19abfefd | 369 | const struct hdac_bus_ops *ops); |
d068ebc2 TI |
370 | void snd_hdac_bus_exit(struct hdac_bus *bus); |
371 | int snd_hdac_bus_exec_verb(struct hdac_bus *bus, unsigned int addr, | |
372 | unsigned int cmd, unsigned int *res); | |
373 | int snd_hdac_bus_exec_verb_unlocked(struct hdac_bus *bus, unsigned int addr, | |
374 | unsigned int cmd, unsigned int *res); | |
375 | void snd_hdac_bus_queue_event(struct hdac_bus *bus, u32 res, u32 res_ex); | |
376 | ||
18d43c9b | 377 | void snd_hdac_bus_process_unsol_events(struct work_struct *work); |
d068ebc2 | 378 | |
7639a06c TI |
379 | static inline void snd_hdac_codec_link_up(struct hdac_device *codec) |
380 | { | |
381 | set_bit(codec->addr, &codec->bus->codec_powered); | |
382 | } | |
383 | ||
384 | static inline void snd_hdac_codec_link_down(struct hdac_device *codec) | |
385 | { | |
386 | clear_bit(codec->addr, &codec->bus->codec_powered); | |
387 | } | |
388 | ||
14752412 TI |
389 | int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val); |
390 | int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr, | |
391 | unsigned int *res); | |
6720b384 | 392 | int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus); |
14752412 TI |
393 | |
394 | bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset); | |
395 | void snd_hdac_bus_stop_chip(struct hdac_bus *bus); | |
396 | void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus); | |
397 | void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus); | |
398 | void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus); | |
399 | void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus); | |
75383f8d | 400 | int snd_hdac_bus_reset_link(struct hdac_bus *bus, bool full_reset); |
14752412 TI |
401 | |
402 | void snd_hdac_bus_update_rirb(struct hdac_bus *bus); | |
473f4145 | 403 | int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status, |
14752412 TI |
404 | void (*ack)(struct hdac_bus *, |
405 | struct hdac_stream *)); | |
406 | ||
304dad30 JK |
407 | int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus); |
408 | void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus); | |
409 | ||
19abfefd TI |
410 | #ifdef CONFIG_SND_HDA_ALIGNED_MMIO |
411 | unsigned int snd_hdac_aligned_read(void __iomem *addr, unsigned int mask); | |
412 | void snd_hdac_aligned_write(unsigned int val, void __iomem *addr, | |
413 | unsigned int mask); | |
414 | #define snd_hdac_reg_writeb(v, addr) snd_hdac_aligned_write(v, addr, 0xff) | |
415 | #define snd_hdac_reg_writew(v, addr) snd_hdac_aligned_write(v, addr, 0xffff) | |
416 | #define snd_hdac_reg_readb(addr) snd_hdac_aligned_read(addr, 0xff) | |
417 | #define snd_hdac_reg_readw(addr) snd_hdac_aligned_read(addr, 0xffff) | |
418 | #else /* CONFIG_SND_HDA_ALIGNED_MMIO */ | |
419 | #define snd_hdac_reg_writeb(val, addr) writeb(val, addr) | |
420 | #define snd_hdac_reg_writew(val, addr) writew(val, addr) | |
421 | #define snd_hdac_reg_readb(addr) readb(addr) | |
422 | #define snd_hdac_reg_readw(addr) readw(addr) | |
423 | #endif /* CONFIG_SND_HDA_ALIGNED_MMIO */ | |
424 | #define snd_hdac_reg_writel(val, addr) writel(val, addr) | |
425 | #define snd_hdac_reg_readl(addr) readl(addr) | |
426 | ||
14752412 TI |
427 | /* |
428 | * macros for easy use | |
429 | */ | |
2c1f8138 | 430 | #define _snd_hdac_chip_writeb(chip, reg, value) \ |
19abfefd | 431 | snd_hdac_reg_writeb(value, (chip)->remap_addr + (reg)) |
2c1f8138 | 432 | #define _snd_hdac_chip_readb(chip, reg) \ |
19abfefd | 433 | snd_hdac_reg_readb((chip)->remap_addr + (reg)) |
2c1f8138 | 434 | #define _snd_hdac_chip_writew(chip, reg, value) \ |
19abfefd | 435 | snd_hdac_reg_writew(value, (chip)->remap_addr + (reg)) |
2c1f8138 | 436 | #define _snd_hdac_chip_readw(chip, reg) \ |
19abfefd | 437 | snd_hdac_reg_readw((chip)->remap_addr + (reg)) |
2c1f8138 | 438 | #define _snd_hdac_chip_writel(chip, reg, value) \ |
19abfefd | 439 | snd_hdac_reg_writel(value, (chip)->remap_addr + (reg)) |
2c1f8138 | 440 | #define _snd_hdac_chip_readl(chip, reg) \ |
19abfefd | 441 | snd_hdac_reg_readl((chip)->remap_addr + (reg)) |
14752412 TI |
442 | |
443 | /* read/write a register, pass without AZX_REG_ prefix */ | |
444 | #define snd_hdac_chip_writel(chip, reg, value) \ | |
2c1f8138 | 445 | _snd_hdac_chip_writel(chip, AZX_REG_ ## reg, value) |
14752412 | 446 | #define snd_hdac_chip_writew(chip, reg, value) \ |
2c1f8138 | 447 | _snd_hdac_chip_writew(chip, AZX_REG_ ## reg, value) |
14752412 | 448 | #define snd_hdac_chip_writeb(chip, reg, value) \ |
2c1f8138 | 449 | _snd_hdac_chip_writeb(chip, AZX_REG_ ## reg, value) |
14752412 | 450 | #define snd_hdac_chip_readl(chip, reg) \ |
2c1f8138 | 451 | _snd_hdac_chip_readl(chip, AZX_REG_ ## reg) |
14752412 | 452 | #define snd_hdac_chip_readw(chip, reg) \ |
2c1f8138 | 453 | _snd_hdac_chip_readw(chip, AZX_REG_ ## reg) |
14752412 | 454 | #define snd_hdac_chip_readb(chip, reg) \ |
2c1f8138 | 455 | _snd_hdac_chip_readb(chip, AZX_REG_ ## reg) |
14752412 TI |
456 | |
457 | /* update a register, pass without AZX_REG_ prefix */ | |
458 | #define snd_hdac_chip_updatel(chip, reg, mask, val) \ | |
459 | snd_hdac_chip_writel(chip, reg, \ | |
460 | (snd_hdac_chip_readl(chip, reg) & ~(mask)) | (val)) | |
461 | #define snd_hdac_chip_updatew(chip, reg, mask, val) \ | |
462 | snd_hdac_chip_writew(chip, reg, \ | |
463 | (snd_hdac_chip_readw(chip, reg) & ~(mask)) | (val)) | |
464 | #define snd_hdac_chip_updateb(chip, reg, mask, val) \ | |
465 | snd_hdac_chip_writeb(chip, reg, \ | |
466 | (snd_hdac_chip_readb(chip, reg) & ~(mask)) | (val)) | |
467 | ||
468 | /* | |
469 | * HD-audio stream | |
470 | */ | |
471 | struct hdac_stream { | |
472 | struct hdac_bus *bus; | |
473 | struct snd_dma_buffer bdl; /* BDL buffer */ | |
474 | __le32 *posbuf; /* position buffer pointer */ | |
475 | int direction; /* playback / capture (SNDRV_PCM_STREAM_*) */ | |
476 | ||
477 | unsigned int bufsize; /* size of the play buffer in bytes */ | |
478 | unsigned int period_bytes; /* size of the period in bytes */ | |
479 | unsigned int frags; /* number for period in the play buffer */ | |
480 | unsigned int fifo_size; /* FIFO size */ | |
481 | ||
482 | void __iomem *sd_addr; /* stream descriptor pointer */ | |
483 | ||
484 | u32 sd_int_sta_mask; /* stream int status mask */ | |
485 | ||
486 | /* pcm support */ | |
487 | struct snd_pcm_substream *substream; /* assigned substream, | |
488 | * set in PCM open | |
489 | */ | |
490 | unsigned int format_val; /* format value to be set in the | |
491 | * controller and the codec | |
492 | */ | |
493 | unsigned char stream_tag; /* assigned stream */ | |
494 | unsigned char index; /* stream index */ | |
495 | int assigned_key; /* last device# key assigned to */ | |
496 | ||
497 | bool opened:1; | |
498 | bool running:1; | |
6d23c8f5 | 499 | bool prepared:1; |
14752412 | 500 | bool no_period_wakeup:1; |
8f3f600b | 501 | bool locked:1; |
14752412 TI |
502 | |
503 | /* timestamp */ | |
504 | unsigned long start_wallclk; /* start + minimum wallclk */ | |
505 | unsigned long period_wallclk; /* wallclk for period */ | |
506 | struct timecounter tc; | |
507 | struct cyclecounter cc; | |
508 | int delay_negative_threshold; | |
509 | ||
510 | struct list_head list; | |
8f3f600b TI |
511 | #ifdef CONFIG_SND_HDA_DSP_LOADER |
512 | /* DSP access mutex */ | |
513 | struct mutex dsp_mutex; | |
514 | #endif | |
14752412 TI |
515 | }; |
516 | ||
517 | void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev, | |
518 | int idx, int direction, int tag); | |
519 | struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus, | |
520 | struct snd_pcm_substream *substream); | |
521 | void snd_hdac_stream_release(struct hdac_stream *azx_dev); | |
4308c9b0 JK |
522 | struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus, |
523 | int dir, int stream_tag); | |
14752412 TI |
524 | |
525 | int snd_hdac_stream_setup(struct hdac_stream *azx_dev); | |
526 | void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev); | |
527 | int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev); | |
86f6501b JK |
528 | int snd_hdac_stream_set_params(struct hdac_stream *azx_dev, |
529 | unsigned int format_val); | |
14752412 TI |
530 | void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start); |
531 | void snd_hdac_stream_clear(struct hdac_stream *azx_dev); | |
532 | void snd_hdac_stream_stop(struct hdac_stream *azx_dev); | |
533 | void snd_hdac_stream_reset(struct hdac_stream *azx_dev); | |
534 | void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set, | |
535 | unsigned int streams, unsigned int reg); | |
536 | void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start, | |
537 | unsigned int streams); | |
538 | void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev, | |
539 | unsigned int streams); | |
5dd3d271 SP |
540 | int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus, |
541 | struct snd_pcm_substream *substream); | |
542 | ||
14752412 TI |
543 | /* |
544 | * macros for easy use | |
545 | */ | |
14752412 TI |
546 | /* read/write a register, pass without AZX_REG_ prefix */ |
547 | #define snd_hdac_stream_writel(dev, reg, value) \ | |
19abfefd | 548 | snd_hdac_reg_writel(value, (dev)->sd_addr + AZX_REG_ ## reg) |
14752412 | 549 | #define snd_hdac_stream_writew(dev, reg, value) \ |
19abfefd | 550 | snd_hdac_reg_writew(value, (dev)->sd_addr + AZX_REG_ ## reg) |
14752412 | 551 | #define snd_hdac_stream_writeb(dev, reg, value) \ |
19abfefd | 552 | snd_hdac_reg_writeb(value, (dev)->sd_addr + AZX_REG_ ## reg) |
14752412 | 553 | #define snd_hdac_stream_readl(dev, reg) \ |
19abfefd | 554 | snd_hdac_reg_readl((dev)->sd_addr + AZX_REG_ ## reg) |
14752412 | 555 | #define snd_hdac_stream_readw(dev, reg) \ |
19abfefd | 556 | snd_hdac_reg_readw((dev)->sd_addr + AZX_REG_ ## reg) |
14752412 | 557 | #define snd_hdac_stream_readb(dev, reg) \ |
19abfefd | 558 | snd_hdac_reg_readb((dev)->sd_addr + AZX_REG_ ## reg) |
14752412 TI |
559 | |
560 | /* update a register, pass without AZX_REG_ prefix */ | |
561 | #define snd_hdac_stream_updatel(dev, reg, mask, val) \ | |
562 | snd_hdac_stream_writel(dev, reg, \ | |
563 | (snd_hdac_stream_readl(dev, reg) & \ | |
564 | ~(mask)) | (val)) | |
565 | #define snd_hdac_stream_updatew(dev, reg, mask, val) \ | |
566 | snd_hdac_stream_writew(dev, reg, \ | |
567 | (snd_hdac_stream_readw(dev, reg) & \ | |
568 | ~(mask)) | (val)) | |
569 | #define snd_hdac_stream_updateb(dev, reg, mask, val) \ | |
570 | snd_hdac_stream_writeb(dev, reg, \ | |
571 | (snd_hdac_stream_readb(dev, reg) & \ | |
572 | ~(mask)) | (val)) | |
573 | ||
8f3f600b TI |
574 | #ifdef CONFIG_SND_HDA_DSP_LOADER |
575 | /* DSP lock helpers */ | |
576 | #define snd_hdac_dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex) | |
577 | #define snd_hdac_dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex) | |
578 | #define snd_hdac_dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex) | |
579 | #define snd_hdac_stream_is_locked(dev) ((dev)->locked) | |
580 | /* DSP loader helpers */ | |
581 | int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format, | |
582 | unsigned int byte_size, struct snd_dma_buffer *bufp); | |
583 | void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start); | |
584 | void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev, | |
585 | struct snd_dma_buffer *dmab); | |
586 | #else /* CONFIG_SND_HDA_DSP_LOADER */ | |
587 | #define snd_hdac_dsp_lock_init(dev) do {} while (0) | |
588 | #define snd_hdac_dsp_lock(dev) do {} while (0) | |
589 | #define snd_hdac_dsp_unlock(dev) do {} while (0) | |
590 | #define snd_hdac_stream_is_locked(dev) 0 | |
591 | ||
592 | static inline int | |
593 | snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format, | |
594 | unsigned int byte_size, struct snd_dma_buffer *bufp) | |
595 | { | |
596 | return 0; | |
597 | } | |
598 | ||
599 | static inline void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start) | |
600 | { | |
601 | } | |
602 | ||
603 | static inline void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev, | |
604 | struct snd_dma_buffer *dmab) | |
605 | { | |
606 | } | |
607 | #endif /* CONFIG_SND_HDA_DSP_LOADER */ | |
608 | ||
609 | ||
71fc4c7e TI |
610 | /* |
611 | * generic array helpers | |
612 | */ | |
613 | void *snd_array_new(struct snd_array *array); | |
614 | void snd_array_free(struct snd_array *array); | |
615 | static inline void snd_array_init(struct snd_array *array, unsigned int size, | |
616 | unsigned int align) | |
617 | { | |
618 | array->elem_size = size; | |
619 | array->alloc_align = align; | |
620 | } | |
621 | ||
622 | static inline void *snd_array_elem(struct snd_array *array, unsigned int idx) | |
623 | { | |
624 | return array->list + idx * array->elem_size; | |
625 | } | |
626 | ||
627 | static inline unsigned int snd_array_index(struct snd_array *array, void *ptr) | |
628 | { | |
629 | return (unsigned long)(ptr - array->list) / array->elem_size; | |
630 | } | |
631 | ||
a9c2dfc8 TI |
632 | /* a helper macro to iterate for each snd_array element */ |
633 | #define snd_array_for_each(array, idx, ptr) \ | |
634 | for ((idx) = 0, (ptr) = (array)->list; (idx) < (array)->used; \ | |
635 | (ptr) = snd_array_elem(array, ++(idx))) | |
636 | ||
e3d280fc | 637 | #endif /* __SOUND_HDAUDIO_H */ |