Commit | Line | Data |
---|---|---|
e3d280fc TI |
1 | /* |
2 | * HD-audio core stuff | |
3 | */ | |
4 | ||
5 | #ifndef __SOUND_HDAUDIO_H | |
6 | #define __SOUND_HDAUDIO_H | |
7 | ||
8 | #include <linux/device.h> | |
14752412 TI |
9 | #include <linux/interrupt.h> |
10 | #include <linux/timecounter.h> | |
11 | #include <sound/core.h> | |
12 | #include <sound/memalloc.h> | |
d068ebc2 | 13 | #include <sound/hda_verbs.h> |
98d8fc6c | 14 | #include <drm/i915_component.h> |
d068ebc2 | 15 | |
7639a06c TI |
16 | /* codec node id */ |
17 | typedef u16 hda_nid_t; | |
18 | ||
d068ebc2 | 19 | struct hdac_bus; |
14752412 | 20 | struct hdac_stream; |
d068ebc2 TI |
21 | struct hdac_device; |
22 | struct hdac_driver; | |
3256be65 | 23 | struct hdac_widget_tree; |
e3d280fc TI |
24 | |
25 | /* | |
26 | * exported bus type | |
27 | */ | |
28 | extern struct bus_type snd_hda_bus_type; | |
29 | ||
ec71efc9 VK |
30 | /* |
31 | * HDA device table | |
32 | */ | |
33 | struct hda_device_id { | |
34 | __u32 vendor_id; | |
35 | __u32 rev_id; | |
36 | const char *name; | |
37 | unsigned long driver_data; | |
38 | }; | |
39 | ||
71fc4c7e TI |
40 | /* |
41 | * generic arrays | |
42 | */ | |
43 | struct snd_array { | |
44 | unsigned int used; | |
45 | unsigned int alloced; | |
46 | unsigned int elem_size; | |
47 | unsigned int alloc_align; | |
48 | void *list; | |
49 | }; | |
50 | ||
e3d280fc TI |
51 | /* |
52 | * HD-audio codec base device | |
53 | */ | |
54 | struct hdac_device { | |
55 | struct device dev; | |
56 | int type; | |
d068ebc2 TI |
57 | struct hdac_bus *bus; |
58 | unsigned int addr; /* codec address */ | |
59 | struct list_head list; /* list point for bus codec_list */ | |
7639a06c TI |
60 | |
61 | hda_nid_t afg; /* AFG node id */ | |
62 | hda_nid_t mfg; /* MFG node id */ | |
63 | ||
64 | /* ids */ | |
65 | unsigned int vendor_id; | |
66 | unsigned int subsystem_id; | |
67 | unsigned int revision_id; | |
68 | unsigned int afg_function_id; | |
69 | unsigned int mfg_function_id; | |
70 | unsigned int afg_unsol:1; | |
71 | unsigned int mfg_unsol:1; | |
72 | ||
73 | unsigned int power_caps; /* FG power caps */ | |
74 | ||
75 | const char *vendor_name; /* codec vendor name */ | |
76 | const char *chip_name; /* codec chip name */ | |
77 | ||
05852448 TI |
78 | /* verb exec op override */ |
79 | int (*exec_verb)(struct hdac_device *dev, unsigned int cmd, | |
80 | unsigned int flags, unsigned int *res); | |
81 | ||
7639a06c TI |
82 | /* widgets */ |
83 | unsigned int num_nodes; | |
84 | hda_nid_t start_nid, end_nid; | |
85 | ||
86 | /* misc flags */ | |
87 | atomic_t in_pm; /* suspend/resume being performed */ | |
a5e7e07c | 88 | bool link_power_control:1; |
3256be65 TI |
89 | |
90 | /* sysfs */ | |
91 | struct hdac_widget_tree *widgets; | |
4d75faa0 TI |
92 | |
93 | /* regmap */ | |
94 | struct regmap *regmap; | |
5e56bcea | 95 | struct snd_array vendor_verbs; |
4d75faa0 | 96 | bool lazy_cache:1; /* don't wake up for writes */ |
faa75f8a | 97 | bool caps_overwriting:1; /* caps overwrite being in process */ |
40ba66a7 | 98 | bool cache_coef:1; /* cache COEF read/write too */ |
e3d280fc TI |
99 | }; |
100 | ||
101 | /* device/driver type used for matching */ | |
102 | enum { | |
103 | HDA_DEV_CORE, | |
104 | HDA_DEV_LEGACY, | |
c1cc18b1 | 105 | HDA_DEV_ASOC, |
e3d280fc TI |
106 | }; |
107 | ||
7639a06c TI |
108 | /* direction */ |
109 | enum { | |
110 | HDA_INPUT, HDA_OUTPUT | |
111 | }; | |
112 | ||
e3d280fc TI |
113 | #define dev_to_hdac_dev(_dev) container_of(_dev, struct hdac_device, dev) |
114 | ||
7639a06c TI |
115 | int snd_hdac_device_init(struct hdac_device *dev, struct hdac_bus *bus, |
116 | const char *name, unsigned int addr); | |
117 | void snd_hdac_device_exit(struct hdac_device *dev); | |
3256be65 TI |
118 | int snd_hdac_device_register(struct hdac_device *codec); |
119 | void snd_hdac_device_unregister(struct hdac_device *codec); | |
7639a06c TI |
120 | |
121 | int snd_hdac_refresh_widgets(struct hdac_device *codec); | |
18dfd79d | 122 | int snd_hdac_refresh_widget_sysfs(struct hdac_device *codec); |
7639a06c TI |
123 | |
124 | unsigned int snd_hdac_make_cmd(struct hdac_device *codec, hda_nid_t nid, | |
125 | unsigned int verb, unsigned int parm); | |
05852448 TI |
126 | int snd_hdac_exec_verb(struct hdac_device *codec, unsigned int cmd, |
127 | unsigned int flags, unsigned int *res); | |
7639a06c TI |
128 | int snd_hdac_read(struct hdac_device *codec, hda_nid_t nid, |
129 | unsigned int verb, unsigned int parm, unsigned int *res); | |
01ed3c06 TI |
130 | int _snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid, int parm, |
131 | unsigned int *res); | |
9ba17b4d TI |
132 | int snd_hdac_read_parm_uncached(struct hdac_device *codec, hda_nid_t nid, |
133 | int parm); | |
faa75f8a TI |
134 | int snd_hdac_override_parm(struct hdac_device *codec, hda_nid_t nid, |
135 | unsigned int parm, unsigned int val); | |
7639a06c TI |
136 | int snd_hdac_get_connections(struct hdac_device *codec, hda_nid_t nid, |
137 | hda_nid_t *conn_list, int max_conns); | |
138 | int snd_hdac_get_sub_nodes(struct hdac_device *codec, hda_nid_t nid, | |
139 | hda_nid_t *start_id); | |
b7d023e1 TI |
140 | unsigned int snd_hdac_calc_stream_format(unsigned int rate, |
141 | unsigned int channels, | |
142 | unsigned int format, | |
143 | unsigned int maxbps, | |
144 | unsigned short spdif_ctls); | |
145 | int snd_hdac_query_supported_pcm(struct hdac_device *codec, hda_nid_t nid, | |
146 | u32 *ratesp, u64 *formatsp, unsigned int *bpsp); | |
147 | bool snd_hdac_is_supported_format(struct hdac_device *codec, hda_nid_t nid, | |
148 | unsigned int format); | |
7639a06c | 149 | |
1b5e6167 SP |
150 | int snd_hdac_codec_read(struct hdac_device *hdac, hda_nid_t nid, |
151 | int flags, unsigned int verb, unsigned int parm); | |
152 | int snd_hdac_codec_write(struct hdac_device *hdac, hda_nid_t nid, | |
153 | int flags, unsigned int verb, unsigned int parm); | |
154 | bool snd_hdac_check_power_state(struct hdac_device *hdac, | |
155 | hda_nid_t nid, unsigned int target_state); | |
01ed3c06 TI |
156 | /** |
157 | * snd_hdac_read_parm - read a codec parameter | |
158 | * @codec: the codec object | |
159 | * @nid: NID to read a parameter | |
160 | * @parm: parameter to read | |
161 | * | |
162 | * Returns -1 for error. If you need to distinguish the error more | |
163 | * strictly, use _snd_hdac_read_parm() directly. | |
164 | */ | |
165 | static inline int snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid, | |
166 | int parm) | |
167 | { | |
168 | unsigned int val; | |
169 | ||
170 | return _snd_hdac_read_parm(codec, nid, parm, &val) < 0 ? -1 : val; | |
171 | } | |
172 | ||
7639a06c | 173 | #ifdef CONFIG_PM |
fbce23a0 TI |
174 | int snd_hdac_power_up(struct hdac_device *codec); |
175 | int snd_hdac_power_down(struct hdac_device *codec); | |
176 | int snd_hdac_power_up_pm(struct hdac_device *codec); | |
177 | int snd_hdac_power_down_pm(struct hdac_device *codec); | |
7639a06c | 178 | #else |
fbce23a0 TI |
179 | static inline int snd_hdac_power_up(struct hdac_device *codec) { return 0; } |
180 | static inline int snd_hdac_power_down(struct hdac_device *codec) { return 0; } | |
181 | static inline int snd_hdac_power_up_pm(struct hdac_device *codec) { return 0; } | |
182 | static inline int snd_hdac_power_down_pm(struct hdac_device *codec) { return 0; } | |
7639a06c TI |
183 | #endif |
184 | ||
e3d280fc TI |
185 | /* |
186 | * HD-audio codec base driver | |
187 | */ | |
188 | struct hdac_driver { | |
189 | struct device_driver driver; | |
190 | int type; | |
ec71efc9 | 191 | const struct hda_device_id *id_table; |
e3d280fc | 192 | int (*match)(struct hdac_device *dev, struct hdac_driver *drv); |
d068ebc2 | 193 | void (*unsol_event)(struct hdac_device *dev, unsigned int event); |
e3d280fc TI |
194 | }; |
195 | ||
196 | #define drv_to_hdac_driver(_drv) container_of(_drv, struct hdac_driver, driver) | |
197 | ||
ec71efc9 VK |
198 | const struct hda_device_id * |
199 | hdac_get_device_id(struct hdac_device *hdev, struct hdac_driver *drv); | |
200 | ||
d068ebc2 | 201 | /* |
14752412 | 202 | * Bus verb operators |
d068ebc2 TI |
203 | */ |
204 | struct hdac_bus_ops { | |
205 | /* send a single command */ | |
206 | int (*command)(struct hdac_bus *bus, unsigned int cmd); | |
207 | /* get a response from the last command */ | |
208 | int (*get_response)(struct hdac_bus *bus, unsigned int addr, | |
209 | unsigned int *res); | |
a5e7e07c ML |
210 | /* control the link power */ |
211 | int (*link_power)(struct hdac_bus *bus, bool enable); | |
d068ebc2 TI |
212 | }; |
213 | ||
14752412 TI |
214 | /* |
215 | * Lowlevel I/O operators | |
216 | */ | |
217 | struct hdac_io_ops { | |
218 | /* mapped register accesses */ | |
219 | void (*reg_writel)(u32 value, u32 __iomem *addr); | |
220 | u32 (*reg_readl)(u32 __iomem *addr); | |
221 | void (*reg_writew)(u16 value, u16 __iomem *addr); | |
222 | u16 (*reg_readw)(u16 __iomem *addr); | |
223 | void (*reg_writeb)(u8 value, u8 __iomem *addr); | |
224 | u8 (*reg_readb)(u8 __iomem *addr); | |
8f3f600b TI |
225 | /* Allocation ops */ |
226 | int (*dma_alloc_pages)(struct hdac_bus *bus, int type, size_t size, | |
227 | struct snd_dma_buffer *buf); | |
228 | void (*dma_free_pages)(struct hdac_bus *bus, | |
229 | struct snd_dma_buffer *buf); | |
14752412 TI |
230 | }; |
231 | ||
d068ebc2 | 232 | #define HDA_UNSOL_QUEUE_SIZE 64 |
14752412 TI |
233 | #define HDA_MAX_CODECS 8 /* limit by controller side */ |
234 | ||
235 | /* HD Audio class code */ | |
236 | #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403 | |
237 | ||
238 | /* | |
239 | * CORB/RIRB | |
240 | * | |
241 | * Each CORB entry is 4byte, RIRB is 8byte | |
242 | */ | |
243 | struct hdac_rb { | |
244 | __le32 *buf; /* virtual address of CORB/RIRB buffer */ | |
245 | dma_addr_t addr; /* physical address of CORB/RIRB buffer */ | |
246 | unsigned short rp, wp; /* RIRB read/write pointers */ | |
247 | int cmds[HDA_MAX_CODECS]; /* number of pending requests */ | |
248 | u32 res[HDA_MAX_CODECS]; /* last read value */ | |
249 | }; | |
d068ebc2 | 250 | |
14752412 TI |
251 | /* |
252 | * HD-audio bus base driver | |
253 | */ | |
d068ebc2 TI |
254 | struct hdac_bus { |
255 | struct device *dev; | |
256 | const struct hdac_bus_ops *ops; | |
14752412 TI |
257 | const struct hdac_io_ops *io_ops; |
258 | ||
259 | /* h/w resources */ | |
260 | unsigned long addr; | |
261 | void __iomem *remap_addr; | |
262 | int irq; | |
d068ebc2 TI |
263 | |
264 | /* codec linked list */ | |
265 | struct list_head codec_list; | |
266 | unsigned int num_codecs; | |
267 | ||
268 | /* link caddr -> codec */ | |
269 | struct hdac_device *caddr_tbl[HDA_MAX_CODEC_ADDRESS + 1]; | |
270 | ||
271 | /* unsolicited event queue */ | |
272 | u32 unsol_queue[HDA_UNSOL_QUEUE_SIZE * 2]; /* ring buffer */ | |
273 | unsigned int unsol_rp, unsol_wp; | |
274 | struct work_struct unsol_work; | |
275 | ||
14752412 TI |
276 | /* bit flags of detected codecs */ |
277 | unsigned long codec_mask; | |
278 | ||
d068ebc2 TI |
279 | /* bit flags of powered codecs */ |
280 | unsigned long codec_powered; | |
281 | ||
14752412 TI |
282 | /* CORB/RIRB */ |
283 | struct hdac_rb corb; | |
284 | struct hdac_rb rirb; | |
285 | unsigned int last_cmd[HDA_MAX_CODECS]; /* last sent command */ | |
286 | ||
287 | /* CORB/RIRB and position buffers */ | |
288 | struct snd_dma_buffer rb; | |
289 | struct snd_dma_buffer posbuf; | |
290 | ||
291 | /* hdac_stream linked list */ | |
292 | struct list_head stream_list; | |
293 | ||
294 | /* operation state */ | |
295 | bool chip_init:1; /* h/w initialized */ | |
296 | ||
297 | /* behavior flags */ | |
d068ebc2 | 298 | bool sync_write:1; /* sync after verb write */ |
14752412 TI |
299 | bool use_posbuf:1; /* use position buffer */ |
300 | bool snoop:1; /* enable snooping */ | |
301 | bool align_bdle_4k:1; /* BDLE align 4K boundary */ | |
302 | bool reverse_assign:1; /* assign devices in reverse order */ | |
303 | bool corbrp_self_clear:1; /* CORBRP clears itself after reset */ | |
304 | ||
305 | int bdl_pos_adj; /* BDL position adjustment */ | |
d068ebc2 TI |
306 | |
307 | /* locks */ | |
14752412 | 308 | spinlock_t reg_lock; |
d068ebc2 | 309 | struct mutex cmd_mutex; |
98d8fc6c ML |
310 | |
311 | /* i915 component interface */ | |
312 | struct i915_audio_component *audio_component; | |
313 | int i915_power_refcount; | |
d068ebc2 TI |
314 | }; |
315 | ||
316 | int snd_hdac_bus_init(struct hdac_bus *bus, struct device *dev, | |
14752412 TI |
317 | const struct hdac_bus_ops *ops, |
318 | const struct hdac_io_ops *io_ops); | |
d068ebc2 TI |
319 | void snd_hdac_bus_exit(struct hdac_bus *bus); |
320 | int snd_hdac_bus_exec_verb(struct hdac_bus *bus, unsigned int addr, | |
321 | unsigned int cmd, unsigned int *res); | |
322 | int snd_hdac_bus_exec_verb_unlocked(struct hdac_bus *bus, unsigned int addr, | |
323 | unsigned int cmd, unsigned int *res); | |
324 | void snd_hdac_bus_queue_event(struct hdac_bus *bus, u32 res, u32 res_ex); | |
325 | ||
326 | int snd_hdac_bus_add_device(struct hdac_bus *bus, struct hdac_device *codec); | |
327 | void snd_hdac_bus_remove_device(struct hdac_bus *bus, | |
328 | struct hdac_device *codec); | |
329 | ||
7639a06c TI |
330 | static inline void snd_hdac_codec_link_up(struct hdac_device *codec) |
331 | { | |
332 | set_bit(codec->addr, &codec->bus->codec_powered); | |
333 | } | |
334 | ||
335 | static inline void snd_hdac_codec_link_down(struct hdac_device *codec) | |
336 | { | |
337 | clear_bit(codec->addr, &codec->bus->codec_powered); | |
338 | } | |
339 | ||
14752412 TI |
340 | int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val); |
341 | int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr, | |
342 | unsigned int *res); | |
a5e7e07c | 343 | int snd_hdac_link_power(struct hdac_device *codec, bool enable); |
14752412 TI |
344 | |
345 | bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset); | |
346 | void snd_hdac_bus_stop_chip(struct hdac_bus *bus); | |
347 | void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus); | |
348 | void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus); | |
349 | void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus); | |
350 | void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus); | |
351 | ||
352 | void snd_hdac_bus_update_rirb(struct hdac_bus *bus); | |
353 | void snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status, | |
354 | void (*ack)(struct hdac_bus *, | |
355 | struct hdac_stream *)); | |
356 | ||
304dad30 JK |
357 | int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus); |
358 | void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus); | |
359 | ||
14752412 TI |
360 | /* |
361 | * macros for easy use | |
362 | */ | |
363 | #define _snd_hdac_chip_write(type, chip, reg, value) \ | |
364 | ((chip)->io_ops->reg_write ## type(value, (chip)->remap_addr + (reg))) | |
365 | #define _snd_hdac_chip_read(type, chip, reg) \ | |
366 | ((chip)->io_ops->reg_read ## type((chip)->remap_addr + (reg))) | |
367 | ||
368 | /* read/write a register, pass without AZX_REG_ prefix */ | |
369 | #define snd_hdac_chip_writel(chip, reg, value) \ | |
370 | _snd_hdac_chip_write(l, chip, AZX_REG_ ## reg, value) | |
371 | #define snd_hdac_chip_writew(chip, reg, value) \ | |
372 | _snd_hdac_chip_write(w, chip, AZX_REG_ ## reg, value) | |
373 | #define snd_hdac_chip_writeb(chip, reg, value) \ | |
374 | _snd_hdac_chip_write(b, chip, AZX_REG_ ## reg, value) | |
375 | #define snd_hdac_chip_readl(chip, reg) \ | |
376 | _snd_hdac_chip_read(l, chip, AZX_REG_ ## reg) | |
377 | #define snd_hdac_chip_readw(chip, reg) \ | |
378 | _snd_hdac_chip_read(w, chip, AZX_REG_ ## reg) | |
379 | #define snd_hdac_chip_readb(chip, reg) \ | |
380 | _snd_hdac_chip_read(b, chip, AZX_REG_ ## reg) | |
381 | ||
382 | /* update a register, pass without AZX_REG_ prefix */ | |
383 | #define snd_hdac_chip_updatel(chip, reg, mask, val) \ | |
384 | snd_hdac_chip_writel(chip, reg, \ | |
385 | (snd_hdac_chip_readl(chip, reg) & ~(mask)) | (val)) | |
386 | #define snd_hdac_chip_updatew(chip, reg, mask, val) \ | |
387 | snd_hdac_chip_writew(chip, reg, \ | |
388 | (snd_hdac_chip_readw(chip, reg) & ~(mask)) | (val)) | |
389 | #define snd_hdac_chip_updateb(chip, reg, mask, val) \ | |
390 | snd_hdac_chip_writeb(chip, reg, \ | |
391 | (snd_hdac_chip_readb(chip, reg) & ~(mask)) | (val)) | |
392 | ||
393 | /* | |
394 | * HD-audio stream | |
395 | */ | |
396 | struct hdac_stream { | |
397 | struct hdac_bus *bus; | |
398 | struct snd_dma_buffer bdl; /* BDL buffer */ | |
399 | __le32 *posbuf; /* position buffer pointer */ | |
400 | int direction; /* playback / capture (SNDRV_PCM_STREAM_*) */ | |
401 | ||
402 | unsigned int bufsize; /* size of the play buffer in bytes */ | |
403 | unsigned int period_bytes; /* size of the period in bytes */ | |
404 | unsigned int frags; /* number for period in the play buffer */ | |
405 | unsigned int fifo_size; /* FIFO size */ | |
406 | ||
407 | void __iomem *sd_addr; /* stream descriptor pointer */ | |
408 | ||
409 | u32 sd_int_sta_mask; /* stream int status mask */ | |
410 | ||
411 | /* pcm support */ | |
412 | struct snd_pcm_substream *substream; /* assigned substream, | |
413 | * set in PCM open | |
414 | */ | |
415 | unsigned int format_val; /* format value to be set in the | |
416 | * controller and the codec | |
417 | */ | |
418 | unsigned char stream_tag; /* assigned stream */ | |
419 | unsigned char index; /* stream index */ | |
420 | int assigned_key; /* last device# key assigned to */ | |
421 | ||
422 | bool opened:1; | |
423 | bool running:1; | |
6d23c8f5 | 424 | bool prepared:1; |
14752412 | 425 | bool no_period_wakeup:1; |
8f3f600b | 426 | bool locked:1; |
14752412 TI |
427 | |
428 | /* timestamp */ | |
429 | unsigned long start_wallclk; /* start + minimum wallclk */ | |
430 | unsigned long period_wallclk; /* wallclk for period */ | |
431 | struct timecounter tc; | |
432 | struct cyclecounter cc; | |
433 | int delay_negative_threshold; | |
434 | ||
435 | struct list_head list; | |
8f3f600b TI |
436 | #ifdef CONFIG_SND_HDA_DSP_LOADER |
437 | /* DSP access mutex */ | |
438 | struct mutex dsp_mutex; | |
439 | #endif | |
14752412 TI |
440 | }; |
441 | ||
442 | void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev, | |
443 | int idx, int direction, int tag); | |
444 | struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus, | |
445 | struct snd_pcm_substream *substream); | |
446 | void snd_hdac_stream_release(struct hdac_stream *azx_dev); | |
4308c9b0 JK |
447 | struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus, |
448 | int dir, int stream_tag); | |
14752412 TI |
449 | |
450 | int snd_hdac_stream_setup(struct hdac_stream *azx_dev); | |
451 | void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev); | |
452 | int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev); | |
86f6501b JK |
453 | int snd_hdac_stream_set_params(struct hdac_stream *azx_dev, |
454 | unsigned int format_val); | |
14752412 TI |
455 | void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start); |
456 | void snd_hdac_stream_clear(struct hdac_stream *azx_dev); | |
457 | void snd_hdac_stream_stop(struct hdac_stream *azx_dev); | |
458 | void snd_hdac_stream_reset(struct hdac_stream *azx_dev); | |
459 | void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set, | |
460 | unsigned int streams, unsigned int reg); | |
461 | void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start, | |
462 | unsigned int streams); | |
463 | void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev, | |
464 | unsigned int streams); | |
465 | /* | |
466 | * macros for easy use | |
467 | */ | |
468 | #define _snd_hdac_stream_write(type, dev, reg, value) \ | |
469 | ((dev)->bus->io_ops->reg_write ## type(value, (dev)->sd_addr + (reg))) | |
470 | #define _snd_hdac_stream_read(type, dev, reg) \ | |
471 | ((dev)->bus->io_ops->reg_read ## type((dev)->sd_addr + (reg))) | |
472 | ||
473 | /* read/write a register, pass without AZX_REG_ prefix */ | |
474 | #define snd_hdac_stream_writel(dev, reg, value) \ | |
475 | _snd_hdac_stream_write(l, dev, AZX_REG_ ## reg, value) | |
476 | #define snd_hdac_stream_writew(dev, reg, value) \ | |
477 | _snd_hdac_stream_write(w, dev, AZX_REG_ ## reg, value) | |
478 | #define snd_hdac_stream_writeb(dev, reg, value) \ | |
479 | _snd_hdac_stream_write(b, dev, AZX_REG_ ## reg, value) | |
480 | #define snd_hdac_stream_readl(dev, reg) \ | |
481 | _snd_hdac_stream_read(l, dev, AZX_REG_ ## reg) | |
482 | #define snd_hdac_stream_readw(dev, reg) \ | |
483 | _snd_hdac_stream_read(w, dev, AZX_REG_ ## reg) | |
484 | #define snd_hdac_stream_readb(dev, reg) \ | |
485 | _snd_hdac_stream_read(b, dev, AZX_REG_ ## reg) | |
486 | ||
487 | /* update a register, pass without AZX_REG_ prefix */ | |
488 | #define snd_hdac_stream_updatel(dev, reg, mask, val) \ | |
489 | snd_hdac_stream_writel(dev, reg, \ | |
490 | (snd_hdac_stream_readl(dev, reg) & \ | |
491 | ~(mask)) | (val)) | |
492 | #define snd_hdac_stream_updatew(dev, reg, mask, val) \ | |
493 | snd_hdac_stream_writew(dev, reg, \ | |
494 | (snd_hdac_stream_readw(dev, reg) & \ | |
495 | ~(mask)) | (val)) | |
496 | #define snd_hdac_stream_updateb(dev, reg, mask, val) \ | |
497 | snd_hdac_stream_writeb(dev, reg, \ | |
498 | (snd_hdac_stream_readb(dev, reg) & \ | |
499 | ~(mask)) | (val)) | |
500 | ||
8f3f600b TI |
501 | #ifdef CONFIG_SND_HDA_DSP_LOADER |
502 | /* DSP lock helpers */ | |
503 | #define snd_hdac_dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex) | |
504 | #define snd_hdac_dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex) | |
505 | #define snd_hdac_dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex) | |
506 | #define snd_hdac_stream_is_locked(dev) ((dev)->locked) | |
507 | /* DSP loader helpers */ | |
508 | int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format, | |
509 | unsigned int byte_size, struct snd_dma_buffer *bufp); | |
510 | void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start); | |
511 | void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev, | |
512 | struct snd_dma_buffer *dmab); | |
513 | #else /* CONFIG_SND_HDA_DSP_LOADER */ | |
514 | #define snd_hdac_dsp_lock_init(dev) do {} while (0) | |
515 | #define snd_hdac_dsp_lock(dev) do {} while (0) | |
516 | #define snd_hdac_dsp_unlock(dev) do {} while (0) | |
517 | #define snd_hdac_stream_is_locked(dev) 0 | |
518 | ||
519 | static inline int | |
520 | snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format, | |
521 | unsigned int byte_size, struct snd_dma_buffer *bufp) | |
522 | { | |
523 | return 0; | |
524 | } | |
525 | ||
526 | static inline void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start) | |
527 | { | |
528 | } | |
529 | ||
530 | static inline void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev, | |
531 | struct snd_dma_buffer *dmab) | |
532 | { | |
533 | } | |
534 | #endif /* CONFIG_SND_HDA_DSP_LOADER */ | |
535 | ||
536 | ||
71fc4c7e TI |
537 | /* |
538 | * generic array helpers | |
539 | */ | |
540 | void *snd_array_new(struct snd_array *array); | |
541 | void snd_array_free(struct snd_array *array); | |
542 | static inline void snd_array_init(struct snd_array *array, unsigned int size, | |
543 | unsigned int align) | |
544 | { | |
545 | array->elem_size = size; | |
546 | array->alloc_align = align; | |
547 | } | |
548 | ||
549 | static inline void *snd_array_elem(struct snd_array *array, unsigned int idx) | |
550 | { | |
551 | return array->list + idx * array->elem_size; | |
552 | } | |
553 | ||
554 | static inline unsigned int snd_array_index(struct snd_array *array, void *ptr) | |
555 | { | |
556 | return (unsigned long)(ptr - array->list) / array->elem_size; | |
557 | } | |
558 | ||
e3d280fc | 559 | #endif /* __SOUND_HDAUDIO_H */ |