Merge tag 'i3c/for-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux
[linux-block.git] / include / sound / hdaudio.h
CommitLineData
b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
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2/*
3 * HD-audio core stuff
4 */
5
6#ifndef __SOUND_HDAUDIO_H
7#define __SOUND_HDAUDIO_H
8
9#include <linux/device.h>
14752412 10#include <linux/interrupt.h>
4d024fe8 11#include <linux/io.h>
c19bd02e 12#include <linux/io-64-nonatomic-lo-hi.h>
3cab69d9 13#include <linux/iopoll.h>
feb20fae 14#include <linux/pm_runtime.h>
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15#include <linux/timecounter.h>
16#include <sound/core.h>
a6ea5fe9 17#include <sound/pcm.h>
14752412 18#include <sound/memalloc.h>
d068ebc2 19#include <sound/hda_verbs.h>
98d8fc6c 20#include <drm/i915_component.h>
d068ebc2 21
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22/* codec node id */
23typedef u16 hda_nid_t;
24
d068ebc2 25struct hdac_bus;
14752412 26struct hdac_stream;
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27struct hdac_device;
28struct hdac_driver;
3256be65 29struct hdac_widget_tree;
da23ac1e 30struct hda_device_id;
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31
32/*
33 * exported bus type
34 */
35extern struct bus_type snd_hda_bus_type;
36
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37/*
38 * generic arrays
39 */
40struct snd_array {
41 unsigned int used;
42 unsigned int alloced;
43 unsigned int elem_size;
44 unsigned int alloc_align;
45 void *list;
46};
47
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48/*
49 * HD-audio codec base device
50 */
51struct hdac_device {
52 struct device dev;
53 int type;
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54 struct hdac_bus *bus;
55 unsigned int addr; /* codec address */
56 struct list_head list; /* list point for bus codec_list */
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57
58 hda_nid_t afg; /* AFG node id */
59 hda_nid_t mfg; /* MFG node id */
60
61 /* ids */
62 unsigned int vendor_id;
63 unsigned int subsystem_id;
64 unsigned int revision_id;
65 unsigned int afg_function_id;
66 unsigned int mfg_function_id;
67 unsigned int afg_unsol:1;
68 unsigned int mfg_unsol:1;
69
70 unsigned int power_caps; /* FG power caps */
71
72 const char *vendor_name; /* codec vendor name */
73 const char *chip_name; /* codec chip name */
74
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75 /* verb exec op override */
76 int (*exec_verb)(struct hdac_device *dev, unsigned int cmd,
77 unsigned int flags, unsigned int *res);
78
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79 /* widgets */
80 unsigned int num_nodes;
81 hda_nid_t start_nid, end_nid;
82
83 /* misc flags */
84 atomic_t in_pm; /* suspend/resume being performed */
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85
86 /* sysfs */
ed180abb 87 struct mutex widget_lock;
3256be65 88 struct hdac_widget_tree *widgets;
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89
90 /* regmap */
91 struct regmap *regmap;
1a462be5 92 struct mutex regmap_lock;
5e56bcea 93 struct snd_array vendor_verbs;
4d75faa0 94 bool lazy_cache:1; /* don't wake up for writes */
faa75f8a 95 bool caps_overwriting:1; /* caps overwrite being in process */
40ba66a7 96 bool cache_coef:1; /* cache COEF read/write too */
e7255c00 97 unsigned int registered:1; /* codec was registered */
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98};
99
100/* device/driver type used for matching */
101enum {
102 HDA_DEV_CORE,
103 HDA_DEV_LEGACY,
c1cc18b1 104 HDA_DEV_ASOC,
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105};
106
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107enum {
108 SND_SKL_PCI_BIND_AUTO, /* automatic selection based on pci class */
109 SND_SKL_PCI_BIND_LEGACY,/* bind only with legacy driver */
110 SND_SKL_PCI_BIND_ASOC /* bind only with ASoC driver */
111};
112
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113/* direction */
114enum {
115 HDA_INPUT, HDA_OUTPUT
116};
117
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118#define dev_to_hdac_dev(_dev) container_of(_dev, struct hdac_device, dev)
119
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120int snd_hdac_device_init(struct hdac_device *dev, struct hdac_bus *bus,
121 const char *name, unsigned int addr);
122void snd_hdac_device_exit(struct hdac_device *dev);
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123int snd_hdac_device_register(struct hdac_device *codec);
124void snd_hdac_device_unregister(struct hdac_device *codec);
ded255be 125int snd_hdac_device_set_chip_name(struct hdac_device *codec, const char *name);
2a81ada3 126int snd_hdac_codec_modalias(const struct hdac_device *hdac, char *buf, size_t size);
7639a06c 127
774a075a 128int snd_hdac_refresh_widgets(struct hdac_device *codec);
7639a06c 129
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130int snd_hdac_read(struct hdac_device *codec, hda_nid_t nid,
131 unsigned int verb, unsigned int parm, unsigned int *res);
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132int _snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid, int parm,
133 unsigned int *res);
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134int snd_hdac_read_parm_uncached(struct hdac_device *codec, hda_nid_t nid,
135 int parm);
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136int snd_hdac_override_parm(struct hdac_device *codec, hda_nid_t nid,
137 unsigned int parm, unsigned int val);
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138int snd_hdac_get_connections(struct hdac_device *codec, hda_nid_t nid,
139 hda_nid_t *conn_list, int max_conns);
140int snd_hdac_get_sub_nodes(struct hdac_device *codec, hda_nid_t nid,
141 hda_nid_t *start_id);
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142unsigned int snd_hdac_calc_stream_format(unsigned int rate,
143 unsigned int channels,
a6ea5fe9 144 snd_pcm_format_t format,
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145 unsigned int maxbps,
146 unsigned short spdif_ctls);
147int snd_hdac_query_supported_pcm(struct hdac_device *codec, hda_nid_t nid,
148 u32 *ratesp, u64 *formatsp, unsigned int *bpsp);
149bool snd_hdac_is_supported_format(struct hdac_device *codec, hda_nid_t nid,
150 unsigned int format);
7639a06c 151
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152int snd_hdac_codec_read(struct hdac_device *hdac, hda_nid_t nid,
153 int flags, unsigned int verb, unsigned int parm);
154int snd_hdac_codec_write(struct hdac_device *hdac, hda_nid_t nid,
155 int flags, unsigned int verb, unsigned int parm);
156bool snd_hdac_check_power_state(struct hdac_device *hdac,
157 hda_nid_t nid, unsigned int target_state);
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158unsigned int snd_hdac_sync_power_state(struct hdac_device *hdac,
159 hda_nid_t nid, unsigned int target_state);
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160/**
161 * snd_hdac_read_parm - read a codec parameter
162 * @codec: the codec object
163 * @nid: NID to read a parameter
164 * @parm: parameter to read
165 *
166 * Returns -1 for error. If you need to distinguish the error more
167 * strictly, use _snd_hdac_read_parm() directly.
168 */
169static inline int snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid,
170 int parm)
171{
172 unsigned int val;
173
174 return _snd_hdac_read_parm(codec, nid, parm, &val) < 0 ? -1 : val;
175}
176
7639a06c 177#ifdef CONFIG_PM
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178int snd_hdac_power_up(struct hdac_device *codec);
179int snd_hdac_power_down(struct hdac_device *codec);
180int snd_hdac_power_up_pm(struct hdac_device *codec);
181int snd_hdac_power_down_pm(struct hdac_device *codec);
fc4f000b 182int snd_hdac_keep_power_up(struct hdac_device *codec);
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183
184/* call this at entering into suspend/resume callbacks in codec driver */
185static inline void snd_hdac_enter_pm(struct hdac_device *codec)
186{
187 atomic_inc(&codec->in_pm);
188}
189
190/* call this at leaving from suspend/resume callbacks in codec driver */
191static inline void snd_hdac_leave_pm(struct hdac_device *codec)
192{
193 atomic_dec(&codec->in_pm);
194}
195
196static inline bool snd_hdac_is_in_pm(struct hdac_device *codec)
197{
198 return atomic_read(&codec->in_pm);
199}
200
201static inline bool snd_hdac_is_power_on(struct hdac_device *codec)
202{
203 return !pm_runtime_suspended(&codec->dev);
204}
7639a06c 205#else
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206static inline int snd_hdac_power_up(struct hdac_device *codec) { return 0; }
207static inline int snd_hdac_power_down(struct hdac_device *codec) { return 0; }
208static inline int snd_hdac_power_up_pm(struct hdac_device *codec) { return 0; }
209static inline int snd_hdac_power_down_pm(struct hdac_device *codec) { return 0; }
fc4f000b 210static inline int snd_hdac_keep_power_up(struct hdac_device *codec) { return 0; }
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211static inline void snd_hdac_enter_pm(struct hdac_device *codec) {}
212static inline void snd_hdac_leave_pm(struct hdac_device *codec) {}
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213static inline bool snd_hdac_is_in_pm(struct hdac_device *codec) { return false; }
214static inline bool snd_hdac_is_power_on(struct hdac_device *codec) { return true; }
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215#endif
216
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217/*
218 * HD-audio codec base driver
219 */
220struct hdac_driver {
221 struct device_driver driver;
222 int type;
ec71efc9 223 const struct hda_device_id *id_table;
e3d280fc 224 int (*match)(struct hdac_device *dev, struct hdac_driver *drv);
d068ebc2 225 void (*unsol_event)(struct hdac_device *dev, unsigned int event);
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226
227 /* fields used by ext bus APIs */
228 int (*probe)(struct hdac_device *dev);
229 int (*remove)(struct hdac_device *dev);
230 void (*shutdown)(struct hdac_device *dev);
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231};
232
233#define drv_to_hdac_driver(_drv) container_of(_drv, struct hdac_driver, driver)
234
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235const struct hda_device_id *
236hdac_get_device_id(struct hdac_device *hdev, struct hdac_driver *drv);
237
d068ebc2 238/*
14752412 239 * Bus verb operators
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240 */
241struct hdac_bus_ops {
242 /* send a single command */
243 int (*command)(struct hdac_bus *bus, unsigned int cmd);
244 /* get a response from the last command */
245 int (*get_response)(struct hdac_bus *bus, unsigned int addr,
246 unsigned int *res);
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247 /* notify of codec link power-up/down */
248 void (*link_power)(struct hdac_device *hdev, bool enable);
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249};
250
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251/*
252 * ops used for ASoC HDA codec drivers
253 */
254struct hdac_ext_bus_ops {
255 int (*hdev_attach)(struct hdac_device *hdev);
256 int (*hdev_detach)(struct hdac_device *hdev);
257};
258
d068ebc2 259#define HDA_UNSOL_QUEUE_SIZE 64
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260#define HDA_MAX_CODECS 8 /* limit by controller side */
261
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262/*
263 * CORB/RIRB
264 *
265 * Each CORB entry is 4byte, RIRB is 8byte
266 */
267struct hdac_rb {
268 __le32 *buf; /* virtual address of CORB/RIRB buffer */
269 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
270 unsigned short rp, wp; /* RIRB read/write pointers */
271 int cmds[HDA_MAX_CODECS]; /* number of pending requests */
272 u32 res[HDA_MAX_CODECS]; /* last read value */
273};
d068ebc2 274
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275/*
276 * HD-audio bus base driver
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277 *
278 * @ppcap: pp capabilities pointer
279 * @spbcap: SPIB capabilities pointer
280 * @mlcap: MultiLink capabilities pointer
281 * @gtscap: gts capabilities pointer
282 * @drsmcap: dma resume capabilities pointer
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283 * @num_streams: streams supported
284 * @idx: HDA link index
285 * @hlink_list: link list of HDA links
e61ab9f0 286 * @lock: lock for link and display power mgmt
76f56fae 287 * @cmd_dma_state: state of cmd DMAs: CORB and RIRB
14752412 288 */
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289struct hdac_bus {
290 struct device *dev;
291 const struct hdac_bus_ops *ops;
cb04ba33 292 const struct hdac_ext_bus_ops *ext_ops;
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293
294 /* h/w resources */
295 unsigned long addr;
296 void __iomem *remap_addr;
297 int irq;
d068ebc2 298
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299 void __iomem *ppcap;
300 void __iomem *spbcap;
301 void __iomem *mlcap;
302 void __iomem *gtscap;
303 void __iomem *drsmcap;
304
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305 /* codec linked list */
306 struct list_head codec_list;
307 unsigned int num_codecs;
308
309 /* link caddr -> codec */
310 struct hdac_device *caddr_tbl[HDA_MAX_CODEC_ADDRESS + 1];
311
312 /* unsolicited event queue */
313 u32 unsol_queue[HDA_UNSOL_QUEUE_SIZE * 2]; /* ring buffer */
314 unsigned int unsol_rp, unsol_wp;
315 struct work_struct unsol_work;
316
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317 /* bit flags of detected codecs */
318 unsigned long codec_mask;
319
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320 /* bit flags of powered codecs */
321 unsigned long codec_powered;
322
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323 /* CORB/RIRB */
324 struct hdac_rb corb;
325 struct hdac_rb rirb;
326 unsigned int last_cmd[HDA_MAX_CODECS]; /* last sent command */
88452da9 327 wait_queue_head_t rirb_wq;
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328
329 /* CORB/RIRB and position buffers */
330 struct snd_dma_buffer rb;
331 struct snd_dma_buffer posbuf;
619a1f19 332 int dma_type; /* SNDRV_DMA_TYPE_XXX for CORB/RIRB */
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333
334 /* hdac_stream linked list */
335 struct list_head stream_list;
336
337 /* operation state */
338 bool chip_init:1; /* h/w initialized */
339
340 /* behavior flags */
4d024fe8 341 bool aligned_mmio:1; /* aligned MMIO access */
d068ebc2 342 bool sync_write:1; /* sync after verb write */
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343 bool use_posbuf:1; /* use position buffer */
344 bool snoop:1; /* enable snooping */
345 bool align_bdle_4k:1; /* BDLE align 4K boundary */
346 bool reverse_assign:1; /* assign devices in reverse order */
347 bool corbrp_self_clear:1; /* CORBRP clears itself after reset */
8af42130 348 bool polling_mode:1;
5f2cb361 349 bool needs_damn_long_delay:1;
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350
351 int poll_count;
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352
353 int bdl_pos_adj; /* BDL position adjustment */
d068ebc2 354
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355 /* delay time in us for dma stop */
356 unsigned int dma_stop_delay;
357
d068ebc2 358 /* locks */
14752412 359 spinlock_t reg_lock;
d068ebc2 360 struct mutex cmd_mutex;
e61ab9f0 361 struct mutex lock;
98d8fc6c 362
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363 /* DRM component interface */
364 struct drm_audio_component *audio_component;
029d92c2 365 long display_power_status;
d31c85fc 366 unsigned long display_power_active;
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367
368 /* parameters required for enhanced capabilities */
369 int num_streams;
370 int idx;
371
e61ab9f0 372 /* link management */
76f56fae 373 struct list_head hlink_list;
76f56fae 374 bool cmd_dma_state;
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375
376 /* factor used to derive STRIPE control value */
377 unsigned int sdo_limit;
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378};
379
380int snd_hdac_bus_init(struct hdac_bus *bus, struct device *dev,
19abfefd 381 const struct hdac_bus_ops *ops);
d068ebc2 382void snd_hdac_bus_exit(struct hdac_bus *bus);
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383int snd_hdac_bus_exec_verb_unlocked(struct hdac_bus *bus, unsigned int addr,
384 unsigned int cmd, unsigned int *res);
d068ebc2 385
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386void snd_hdac_codec_link_up(struct hdac_device *codec);
387void snd_hdac_codec_link_down(struct hdac_device *codec);
7639a06c 388
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389int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val);
390int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr,
391 unsigned int *res);
6720b384 392int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus);
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393
394bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset);
395void snd_hdac_bus_stop_chip(struct hdac_bus *bus);
396void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus);
397void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus);
398void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus);
399void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus);
75383f8d 400int snd_hdac_bus_reset_link(struct hdac_bus *bus, bool full_reset);
f9e5fd1b 401void snd_hdac_bus_link_power(struct hdac_device *hdev, bool enable);
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402
403void snd_hdac_bus_update_rirb(struct hdac_bus *bus);
473f4145 404int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status,
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405 void (*ack)(struct hdac_bus *,
406 struct hdac_stream *));
407
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408int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus);
409void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus);
410
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411#ifdef CONFIG_SND_HDA_ALIGNED_MMIO
412unsigned int snd_hdac_aligned_read(void __iomem *addr, unsigned int mask);
413void snd_hdac_aligned_write(unsigned int val, void __iomem *addr,
414 unsigned int mask);
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415#define snd_hdac_aligned_mmio(bus) (bus)->aligned_mmio
416#else
417#define snd_hdac_aligned_mmio(bus) false
418#define snd_hdac_aligned_read(addr, mask) 0
419#define snd_hdac_aligned_write(val, addr, mask) do {} while (0)
420#endif
421
422static inline void snd_hdac_reg_writeb(struct hdac_bus *bus, void __iomem *addr,
423 u8 val)
424{
425 if (snd_hdac_aligned_mmio(bus))
426 snd_hdac_aligned_write(val, addr, 0xff);
427 else
428 writeb(val, addr);
429}
430
431static inline void snd_hdac_reg_writew(struct hdac_bus *bus, void __iomem *addr,
432 u16 val)
433{
434 if (snd_hdac_aligned_mmio(bus))
435 snd_hdac_aligned_write(val, addr, 0xffff);
436 else
437 writew(val, addr);
438}
439
440static inline u8 snd_hdac_reg_readb(struct hdac_bus *bus, void __iomem *addr)
441{
442 return snd_hdac_aligned_mmio(bus) ?
443 snd_hdac_aligned_read(addr, 0xff) : readb(addr);
444}
445
446static inline u16 snd_hdac_reg_readw(struct hdac_bus *bus, void __iomem *addr)
447{
448 return snd_hdac_aligned_mmio(bus) ?
449 snd_hdac_aligned_read(addr, 0xffff) : readw(addr);
450}
451
452#define snd_hdac_reg_writel(bus, addr, val) writel(val, addr)
453#define snd_hdac_reg_readl(bus, addr) readl(addr)
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454#define snd_hdac_reg_writeq(bus, addr, val) writeq(val, addr)
455#define snd_hdac_reg_readq(bus, addr) readq(addr)
19abfefd 456
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457/*
458 * macros for easy use
459 */
2c1f8138 460#define _snd_hdac_chip_writeb(chip, reg, value) \
4d024fe8 461 snd_hdac_reg_writeb(chip, (chip)->remap_addr + (reg), value)
2c1f8138 462#define _snd_hdac_chip_readb(chip, reg) \
4d024fe8 463 snd_hdac_reg_readb(chip, (chip)->remap_addr + (reg))
2c1f8138 464#define _snd_hdac_chip_writew(chip, reg, value) \
4d024fe8 465 snd_hdac_reg_writew(chip, (chip)->remap_addr + (reg), value)
2c1f8138 466#define _snd_hdac_chip_readw(chip, reg) \
4d024fe8 467 snd_hdac_reg_readw(chip, (chip)->remap_addr + (reg))
2c1f8138 468#define _snd_hdac_chip_writel(chip, reg, value) \
4d024fe8 469 snd_hdac_reg_writel(chip, (chip)->remap_addr + (reg), value)
2c1f8138 470#define _snd_hdac_chip_readl(chip, reg) \
4d024fe8 471 snd_hdac_reg_readl(chip, (chip)->remap_addr + (reg))
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472
473/* read/write a register, pass without AZX_REG_ prefix */
474#define snd_hdac_chip_writel(chip, reg, value) \
2c1f8138 475 _snd_hdac_chip_writel(chip, AZX_REG_ ## reg, value)
14752412 476#define snd_hdac_chip_writew(chip, reg, value) \
2c1f8138 477 _snd_hdac_chip_writew(chip, AZX_REG_ ## reg, value)
14752412 478#define snd_hdac_chip_writeb(chip, reg, value) \
2c1f8138 479 _snd_hdac_chip_writeb(chip, AZX_REG_ ## reg, value)
14752412 480#define snd_hdac_chip_readl(chip, reg) \
2c1f8138 481 _snd_hdac_chip_readl(chip, AZX_REG_ ## reg)
14752412 482#define snd_hdac_chip_readw(chip, reg) \
2c1f8138 483 _snd_hdac_chip_readw(chip, AZX_REG_ ## reg)
14752412 484#define snd_hdac_chip_readb(chip, reg) \
2c1f8138 485 _snd_hdac_chip_readb(chip, AZX_REG_ ## reg)
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486
487/* update a register, pass without AZX_REG_ prefix */
488#define snd_hdac_chip_updatel(chip, reg, mask, val) \
489 snd_hdac_chip_writel(chip, reg, \
490 (snd_hdac_chip_readl(chip, reg) & ~(mask)) | (val))
491#define snd_hdac_chip_updatew(chip, reg, mask, val) \
492 snd_hdac_chip_writew(chip, reg, \
493 (snd_hdac_chip_readw(chip, reg) & ~(mask)) | (val))
494#define snd_hdac_chip_updateb(chip, reg, mask, val) \
495 snd_hdac_chip_writeb(chip, reg, \
496 (snd_hdac_chip_readb(chip, reg) & ~(mask)) | (val))
497
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498/* update register macro */
499#define snd_hdac_updatel(addr, reg, mask, val) \
500 writel(((readl(addr + reg) & ~(mask)) | (val)), addr + reg)
501
502#define snd_hdac_updatew(addr, reg, mask, val) \
503 writew(((readw(addr + reg) & ~(mask)) | (val)), addr + reg)
504
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505/*
506 * HD-audio stream
507 */
508struct hdac_stream {
509 struct hdac_bus *bus;
510 struct snd_dma_buffer bdl; /* BDL buffer */
511 __le32 *posbuf; /* position buffer pointer */
512 int direction; /* playback / capture (SNDRV_PCM_STREAM_*) */
513
514 unsigned int bufsize; /* size of the play buffer in bytes */
515 unsigned int period_bytes; /* size of the period in bytes */
516 unsigned int frags; /* number for period in the play buffer */
517 unsigned int fifo_size; /* FIFO size */
518
519 void __iomem *sd_addr; /* stream descriptor pointer */
520
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521 void __iomem *spib_addr; /* software position in buffers stream pointer */
522 void __iomem *fifo_addr; /* software position Max fifos stream pointer */
523
524 void __iomem *dpibr_addr; /* DMA position in buffer resume pointer */
525 u32 dpib; /* DMA position in buffer */
526 u32 lpib; /* Linear position in buffer */
527
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528 u32 sd_int_sta_mask; /* stream int status mask */
529
530 /* pcm support */
531 struct snd_pcm_substream *substream; /* assigned substream,
532 * set in PCM open
533 */
4a9ce6e4 534 struct snd_compr_stream *cstream;
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535 unsigned int format_val; /* format value to be set in the
536 * controller and the codec
537 */
538 unsigned char stream_tag; /* assigned stream */
539 unsigned char index; /* stream index */
540 int assigned_key; /* last device# key assigned to */
541
542 bool opened:1;
543 bool running:1;
6d23c8f5 544 bool prepared:1;
14752412 545 bool no_period_wakeup:1;
8f3f600b 546 bool locked:1;
e38e486d 547 bool stripe:1; /* apply stripe control */
14752412 548
4a9ce6e4 549 u64 curr_pos;
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550 /* timestamp */
551 unsigned long start_wallclk; /* start + minimum wallclk */
552 unsigned long period_wallclk; /* wallclk for period */
553 struct timecounter tc;
554 struct cyclecounter cc;
555 int delay_negative_threshold;
556
557 struct list_head list;
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558#ifdef CONFIG_SND_HDA_DSP_LOADER
559 /* DSP access mutex */
560 struct mutex dsp_mutex;
561#endif
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562};
563
564void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,
565 int idx, int direction, int tag);
566struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,
567 struct snd_pcm_substream *substream);
ac3467ad 568void snd_hdac_stream_release_locked(struct hdac_stream *azx_dev);
14752412 569void snd_hdac_stream_release(struct hdac_stream *azx_dev);
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570struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus,
571 int dir, int stream_tag);
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572
573int snd_hdac_stream_setup(struct hdac_stream *azx_dev);
574void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev);
575int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev);
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576int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
577 unsigned int format_val);
4fe20d62 578void snd_hdac_stream_start(struct hdac_stream *azx_dev);
14752412 579void snd_hdac_stream_stop(struct hdac_stream *azx_dev);
24ad3835 580void snd_hdac_stop_streams(struct hdac_bus *bus);
12054f0c 581void snd_hdac_stop_streams_and_chip(struct hdac_bus *bus);
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582void snd_hdac_stream_reset(struct hdac_stream *azx_dev);
583void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
584 unsigned int streams, unsigned int reg);
585void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
586 unsigned int streams);
587void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
588 unsigned int streams);
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589int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus,
590 struct snd_pcm_substream *substream);
591
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592void snd_hdac_stream_spbcap_enable(struct hdac_bus *chip,
593 bool enable, int index);
594int snd_hdac_stream_set_spib(struct hdac_bus *bus,
595 struct hdac_stream *azx_dev, u32 value);
596int snd_hdac_stream_get_spbmaxfifo(struct hdac_bus *bus,
597 struct hdac_stream *azx_dev);
598void snd_hdac_stream_drsm_enable(struct hdac_bus *bus,
599 bool enable, int index);
efffb014 600int snd_hdac_stream_wait_drsm(struct hdac_stream *azx_dev);
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601int snd_hdac_stream_set_dpibr(struct hdac_bus *bus,
602 struct hdac_stream *azx_dev, u32 value);
603int snd_hdac_stream_set_lpib(struct hdac_stream *azx_dev, u32 value);
604
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605/*
606 * macros for easy use
607 */
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608/* read/write a register, pass without AZX_REG_ prefix */
609#define snd_hdac_stream_writel(dev, reg, value) \
4d024fe8 610 snd_hdac_reg_writel((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value)
14752412 611#define snd_hdac_stream_writew(dev, reg, value) \
4d024fe8 612 snd_hdac_reg_writew((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value)
14752412 613#define snd_hdac_stream_writeb(dev, reg, value) \
4d024fe8 614 snd_hdac_reg_writeb((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value)
14752412 615#define snd_hdac_stream_readl(dev, reg) \
4d024fe8 616 snd_hdac_reg_readl((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)
14752412 617#define snd_hdac_stream_readw(dev, reg) \
4d024fe8 618 snd_hdac_reg_readw((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)
14752412 619#define snd_hdac_stream_readb(dev, reg) \
4d024fe8 620 snd_hdac_reg_readb((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)
3cab69d9 621#define snd_hdac_stream_readb_poll(dev, reg, val, cond, delay_us, timeout_us) \
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622 read_poll_timeout_atomic(snd_hdac_reg_readb, val, cond, delay_us, timeout_us, \
623 false, (dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)
3cab69d9 624#define snd_hdac_stream_readl_poll(dev, reg, val, cond, delay_us, timeout_us) \
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625 read_poll_timeout_atomic(snd_hdac_reg_readl, val, cond, delay_us, timeout_us, \
626 false, (dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)
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627
628/* update a register, pass without AZX_REG_ prefix */
629#define snd_hdac_stream_updatel(dev, reg, mask, val) \
630 snd_hdac_stream_writel(dev, reg, \
631 (snd_hdac_stream_readl(dev, reg) & \
632 ~(mask)) | (val))
633#define snd_hdac_stream_updatew(dev, reg, mask, val) \
634 snd_hdac_stream_writew(dev, reg, \
635 (snd_hdac_stream_readw(dev, reg) & \
636 ~(mask)) | (val))
637#define snd_hdac_stream_updateb(dev, reg, mask, val) \
638 snd_hdac_stream_writeb(dev, reg, \
639 (snd_hdac_stream_readb(dev, reg) & \
640 ~(mask)) | (val))
641
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642#ifdef CONFIG_SND_HDA_DSP_LOADER
643/* DSP lock helpers */
644#define snd_hdac_dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex)
645#define snd_hdac_dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex)
646#define snd_hdac_dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex)
647#define snd_hdac_stream_is_locked(dev) ((dev)->locked)
648/* DSP loader helpers */
649int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
650 unsigned int byte_size, struct snd_dma_buffer *bufp);
651void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start);
652void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
653 struct snd_dma_buffer *dmab);
654#else /* CONFIG_SND_HDA_DSP_LOADER */
655#define snd_hdac_dsp_lock_init(dev) do {} while (0)
656#define snd_hdac_dsp_lock(dev) do {} while (0)
657#define snd_hdac_dsp_unlock(dev) do {} while (0)
658#define snd_hdac_stream_is_locked(dev) 0
659
660static inline int
661snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
662 unsigned int byte_size, struct snd_dma_buffer *bufp)
663{
664 return 0;
665}
666
667static inline void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)
668{
669}
670
671static inline void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
672 struct snd_dma_buffer *dmab)
673{
674}
675#endif /* CONFIG_SND_HDA_DSP_LOADER */
676
677
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678/*
679 * generic array helpers
680 */
681void *snd_array_new(struct snd_array *array);
682void snd_array_free(struct snd_array *array);
683static inline void snd_array_init(struct snd_array *array, unsigned int size,
684 unsigned int align)
685{
686 array->elem_size = size;
687 array->alloc_align = align;
688}
689
690static inline void *snd_array_elem(struct snd_array *array, unsigned int idx)
691{
692 return array->list + idx * array->elem_size;
693}
694
695static inline unsigned int snd_array_index(struct snd_array *array, void *ptr)
696{
697 return (unsigned long)(ptr - array->list) / array->elem_size;
698}
699
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700/* a helper macro to iterate for each snd_array element */
701#define snd_array_for_each(array, idx, ptr) \
702 for ((idx) = 0, (ptr) = (array)->list; (idx) < (array)->used; \
703 (ptr) = snd_array_elem(array, ++(idx)))
704
e3d280fc 705#endif /* __SOUND_HDAUDIO_H */