Commit | Line | Data |
---|---|---|
b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
e3d280fc TI |
2 | /* |
3 | * HD-audio core stuff | |
4 | */ | |
5 | ||
6 | #ifndef __SOUND_HDAUDIO_H | |
7 | #define __SOUND_HDAUDIO_H | |
8 | ||
9 | #include <linux/device.h> | |
14752412 | 10 | #include <linux/interrupt.h> |
4d024fe8 | 11 | #include <linux/io.h> |
c19bd02e | 12 | #include <linux/io-64-nonatomic-lo-hi.h> |
3cab69d9 | 13 | #include <linux/iopoll.h> |
feb20fae | 14 | #include <linux/pm_runtime.h> |
14752412 TI |
15 | #include <linux/timecounter.h> |
16 | #include <sound/core.h> | |
a6ea5fe9 | 17 | #include <sound/pcm.h> |
14752412 | 18 | #include <sound/memalloc.h> |
d068ebc2 | 19 | #include <sound/hda_verbs.h> |
98d8fc6c | 20 | #include <drm/i915_component.h> |
d068ebc2 | 21 | |
7639a06c TI |
22 | /* codec node id */ |
23 | typedef u16 hda_nid_t; | |
24 | ||
d068ebc2 | 25 | struct hdac_bus; |
14752412 | 26 | struct hdac_stream; |
d068ebc2 TI |
27 | struct hdac_device; |
28 | struct hdac_driver; | |
3256be65 | 29 | struct hdac_widget_tree; |
da23ac1e | 30 | struct hda_device_id; |
e3d280fc TI |
31 | |
32 | /* | |
33 | * exported bus type | |
34 | */ | |
35 | extern struct bus_type snd_hda_bus_type; | |
36 | ||
71fc4c7e TI |
37 | /* |
38 | * generic arrays | |
39 | */ | |
40 | struct snd_array { | |
41 | unsigned int used; | |
42 | unsigned int alloced; | |
43 | unsigned int elem_size; | |
44 | unsigned int alloc_align; | |
45 | void *list; | |
46 | }; | |
47 | ||
e3d280fc TI |
48 | /* |
49 | * HD-audio codec base device | |
50 | */ | |
51 | struct hdac_device { | |
52 | struct device dev; | |
53 | int type; | |
d068ebc2 TI |
54 | struct hdac_bus *bus; |
55 | unsigned int addr; /* codec address */ | |
56 | struct list_head list; /* list point for bus codec_list */ | |
7639a06c TI |
57 | |
58 | hda_nid_t afg; /* AFG node id */ | |
59 | hda_nid_t mfg; /* MFG node id */ | |
60 | ||
61 | /* ids */ | |
62 | unsigned int vendor_id; | |
63 | unsigned int subsystem_id; | |
64 | unsigned int revision_id; | |
65 | unsigned int afg_function_id; | |
66 | unsigned int mfg_function_id; | |
67 | unsigned int afg_unsol:1; | |
68 | unsigned int mfg_unsol:1; | |
69 | ||
70 | unsigned int power_caps; /* FG power caps */ | |
71 | ||
72 | const char *vendor_name; /* codec vendor name */ | |
73 | const char *chip_name; /* codec chip name */ | |
74 | ||
05852448 TI |
75 | /* verb exec op override */ |
76 | int (*exec_verb)(struct hdac_device *dev, unsigned int cmd, | |
77 | unsigned int flags, unsigned int *res); | |
78 | ||
7639a06c TI |
79 | /* widgets */ |
80 | unsigned int num_nodes; | |
81 | hda_nid_t start_nid, end_nid; | |
82 | ||
83 | /* misc flags */ | |
84 | atomic_t in_pm; /* suspend/resume being performed */ | |
3256be65 TI |
85 | |
86 | /* sysfs */ | |
ed180abb | 87 | struct mutex widget_lock; |
3256be65 | 88 | struct hdac_widget_tree *widgets; |
4d75faa0 TI |
89 | |
90 | /* regmap */ | |
91 | struct regmap *regmap; | |
1a462be5 | 92 | struct mutex regmap_lock; |
5e56bcea | 93 | struct snd_array vendor_verbs; |
4d75faa0 | 94 | bool lazy_cache:1; /* don't wake up for writes */ |
faa75f8a | 95 | bool caps_overwriting:1; /* caps overwrite being in process */ |
40ba66a7 | 96 | bool cache_coef:1; /* cache COEF read/write too */ |
e7255c00 | 97 | unsigned int registered:1; /* codec was registered */ |
e3d280fc TI |
98 | }; |
99 | ||
100 | /* device/driver type used for matching */ | |
101 | enum { | |
102 | HDA_DEV_CORE, | |
103 | HDA_DEV_LEGACY, | |
c1cc18b1 | 104 | HDA_DEV_ASOC, |
e3d280fc TI |
105 | }; |
106 | ||
d82b51c8 PLB |
107 | enum { |
108 | SND_SKL_PCI_BIND_AUTO, /* automatic selection based on pci class */ | |
109 | SND_SKL_PCI_BIND_LEGACY,/* bind only with legacy driver */ | |
110 | SND_SKL_PCI_BIND_ASOC /* bind only with ASoC driver */ | |
111 | }; | |
112 | ||
7639a06c TI |
113 | /* direction */ |
114 | enum { | |
115 | HDA_INPUT, HDA_OUTPUT | |
116 | }; | |
117 | ||
e3d280fc TI |
118 | #define dev_to_hdac_dev(_dev) container_of(_dev, struct hdac_device, dev) |
119 | ||
7639a06c TI |
120 | int snd_hdac_device_init(struct hdac_device *dev, struct hdac_bus *bus, |
121 | const char *name, unsigned int addr); | |
122 | void snd_hdac_device_exit(struct hdac_device *dev); | |
3256be65 TI |
123 | int snd_hdac_device_register(struct hdac_device *codec); |
124 | void snd_hdac_device_unregister(struct hdac_device *codec); | |
ded255be | 125 | int snd_hdac_device_set_chip_name(struct hdac_device *codec, const char *name); |
2a81ada3 | 126 | int snd_hdac_codec_modalias(const struct hdac_device *hdac, char *buf, size_t size); |
7639a06c | 127 | |
774a075a | 128 | int snd_hdac_refresh_widgets(struct hdac_device *codec); |
7639a06c | 129 | |
7639a06c TI |
130 | int snd_hdac_read(struct hdac_device *codec, hda_nid_t nid, |
131 | unsigned int verb, unsigned int parm, unsigned int *res); | |
01ed3c06 TI |
132 | int _snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid, int parm, |
133 | unsigned int *res); | |
9ba17b4d TI |
134 | int snd_hdac_read_parm_uncached(struct hdac_device *codec, hda_nid_t nid, |
135 | int parm); | |
faa75f8a TI |
136 | int snd_hdac_override_parm(struct hdac_device *codec, hda_nid_t nid, |
137 | unsigned int parm, unsigned int val); | |
7639a06c TI |
138 | int snd_hdac_get_connections(struct hdac_device *codec, hda_nid_t nid, |
139 | hda_nid_t *conn_list, int max_conns); | |
140 | int snd_hdac_get_sub_nodes(struct hdac_device *codec, hda_nid_t nid, | |
141 | hda_nid_t *start_id); | |
b7d023e1 TI |
142 | unsigned int snd_hdac_calc_stream_format(unsigned int rate, |
143 | unsigned int channels, | |
a6ea5fe9 | 144 | snd_pcm_format_t format, |
b7d023e1 TI |
145 | unsigned int maxbps, |
146 | unsigned short spdif_ctls); | |
147 | int snd_hdac_query_supported_pcm(struct hdac_device *codec, hda_nid_t nid, | |
148 | u32 *ratesp, u64 *formatsp, unsigned int *bpsp); | |
149 | bool snd_hdac_is_supported_format(struct hdac_device *codec, hda_nid_t nid, | |
150 | unsigned int format); | |
7639a06c | 151 | |
1b5e6167 SP |
152 | int snd_hdac_codec_read(struct hdac_device *hdac, hda_nid_t nid, |
153 | int flags, unsigned int verb, unsigned int parm); | |
154 | int snd_hdac_codec_write(struct hdac_device *hdac, hda_nid_t nid, | |
155 | int flags, unsigned int verb, unsigned int parm); | |
156 | bool snd_hdac_check_power_state(struct hdac_device *hdac, | |
157 | hda_nid_t nid, unsigned int target_state); | |
09787492 AK |
158 | unsigned int snd_hdac_sync_power_state(struct hdac_device *hdac, |
159 | hda_nid_t nid, unsigned int target_state); | |
01ed3c06 TI |
160 | /** |
161 | * snd_hdac_read_parm - read a codec parameter | |
162 | * @codec: the codec object | |
163 | * @nid: NID to read a parameter | |
164 | * @parm: parameter to read | |
165 | * | |
166 | * Returns -1 for error. If you need to distinguish the error more | |
167 | * strictly, use _snd_hdac_read_parm() directly. | |
168 | */ | |
169 | static inline int snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid, | |
170 | int parm) | |
171 | { | |
172 | unsigned int val; | |
173 | ||
174 | return _snd_hdac_read_parm(codec, nid, parm, &val) < 0 ? -1 : val; | |
175 | } | |
176 | ||
7639a06c | 177 | #ifdef CONFIG_PM |
fbce23a0 TI |
178 | int snd_hdac_power_up(struct hdac_device *codec); |
179 | int snd_hdac_power_down(struct hdac_device *codec); | |
180 | int snd_hdac_power_up_pm(struct hdac_device *codec); | |
181 | int snd_hdac_power_down_pm(struct hdac_device *codec); | |
fc4f000b | 182 | int snd_hdac_keep_power_up(struct hdac_device *codec); |
feb20fae TI |
183 | |
184 | /* call this at entering into suspend/resume callbacks in codec driver */ | |
185 | static inline void snd_hdac_enter_pm(struct hdac_device *codec) | |
186 | { | |
187 | atomic_inc(&codec->in_pm); | |
188 | } | |
189 | ||
190 | /* call this at leaving from suspend/resume callbacks in codec driver */ | |
191 | static inline void snd_hdac_leave_pm(struct hdac_device *codec) | |
192 | { | |
193 | atomic_dec(&codec->in_pm); | |
194 | } | |
195 | ||
196 | static inline bool snd_hdac_is_in_pm(struct hdac_device *codec) | |
197 | { | |
198 | return atomic_read(&codec->in_pm); | |
199 | } | |
200 | ||
201 | static inline bool snd_hdac_is_power_on(struct hdac_device *codec) | |
202 | { | |
203 | return !pm_runtime_suspended(&codec->dev); | |
204 | } | |
7639a06c | 205 | #else |
fbce23a0 TI |
206 | static inline int snd_hdac_power_up(struct hdac_device *codec) { return 0; } |
207 | static inline int snd_hdac_power_down(struct hdac_device *codec) { return 0; } | |
208 | static inline int snd_hdac_power_up_pm(struct hdac_device *codec) { return 0; } | |
209 | static inline int snd_hdac_power_down_pm(struct hdac_device *codec) { return 0; } | |
fc4f000b | 210 | static inline int snd_hdac_keep_power_up(struct hdac_device *codec) { return 0; } |
feb20fae TI |
211 | static inline void snd_hdac_enter_pm(struct hdac_device *codec) {} |
212 | static inline void snd_hdac_leave_pm(struct hdac_device *codec) {} | |
79263c3b JY |
213 | static inline bool snd_hdac_is_in_pm(struct hdac_device *codec) { return false; } |
214 | static inline bool snd_hdac_is_power_on(struct hdac_device *codec) { return true; } | |
7639a06c TI |
215 | #endif |
216 | ||
e3d280fc TI |
217 | /* |
218 | * HD-audio codec base driver | |
219 | */ | |
220 | struct hdac_driver { | |
221 | struct device_driver driver; | |
222 | int type; | |
ec71efc9 | 223 | const struct hda_device_id *id_table; |
e3d280fc | 224 | int (*match)(struct hdac_device *dev, struct hdac_driver *drv); |
d068ebc2 | 225 | void (*unsol_event)(struct hdac_device *dev, unsigned int event); |
e1df9317 RU |
226 | |
227 | /* fields used by ext bus APIs */ | |
228 | int (*probe)(struct hdac_device *dev); | |
229 | int (*remove)(struct hdac_device *dev); | |
230 | void (*shutdown)(struct hdac_device *dev); | |
e3d280fc TI |
231 | }; |
232 | ||
233 | #define drv_to_hdac_driver(_drv) container_of(_drv, struct hdac_driver, driver) | |
234 | ||
ec71efc9 VK |
235 | const struct hda_device_id * |
236 | hdac_get_device_id(struct hdac_device *hdev, struct hdac_driver *drv); | |
237 | ||
d068ebc2 | 238 | /* |
14752412 | 239 | * Bus verb operators |
d068ebc2 TI |
240 | */ |
241 | struct hdac_bus_ops { | |
242 | /* send a single command */ | |
243 | int (*command)(struct hdac_bus *bus, unsigned int cmd); | |
244 | /* get a response from the last command */ | |
245 | int (*get_response)(struct hdac_bus *bus, unsigned int addr, | |
246 | unsigned int *res); | |
f9e5fd1b KV |
247 | /* notify of codec link power-up/down */ |
248 | void (*link_power)(struct hdac_device *hdev, bool enable); | |
d068ebc2 TI |
249 | }; |
250 | ||
cb04ba33 RU |
251 | /* |
252 | * ops used for ASoC HDA codec drivers | |
253 | */ | |
254 | struct hdac_ext_bus_ops { | |
255 | int (*hdev_attach)(struct hdac_device *hdev); | |
256 | int (*hdev_detach)(struct hdac_device *hdev); | |
257 | }; | |
258 | ||
d068ebc2 | 259 | #define HDA_UNSOL_QUEUE_SIZE 64 |
14752412 TI |
260 | #define HDA_MAX_CODECS 8 /* limit by controller side */ |
261 | ||
14752412 TI |
262 | /* |
263 | * CORB/RIRB | |
264 | * | |
265 | * Each CORB entry is 4byte, RIRB is 8byte | |
266 | */ | |
267 | struct hdac_rb { | |
268 | __le32 *buf; /* virtual address of CORB/RIRB buffer */ | |
269 | dma_addr_t addr; /* physical address of CORB/RIRB buffer */ | |
270 | unsigned short rp, wp; /* RIRB read/write pointers */ | |
271 | int cmds[HDA_MAX_CODECS]; /* number of pending requests */ | |
272 | u32 res[HDA_MAX_CODECS]; /* last read value */ | |
273 | }; | |
d068ebc2 | 274 | |
14752412 TI |
275 | /* |
276 | * HD-audio bus base driver | |
6720b384 VK |
277 | * |
278 | * @ppcap: pp capabilities pointer | |
279 | * @spbcap: SPIB capabilities pointer | |
280 | * @mlcap: MultiLink capabilities pointer | |
281 | * @gtscap: gts capabilities pointer | |
282 | * @drsmcap: dma resume capabilities pointer | |
76f56fae RU |
283 | * @num_streams: streams supported |
284 | * @idx: HDA link index | |
285 | * @hlink_list: link list of HDA links | |
e61ab9f0 | 286 | * @lock: lock for link and display power mgmt |
76f56fae | 287 | * @cmd_dma_state: state of cmd DMAs: CORB and RIRB |
14752412 | 288 | */ |
d068ebc2 TI |
289 | struct hdac_bus { |
290 | struct device *dev; | |
291 | const struct hdac_bus_ops *ops; | |
cb04ba33 | 292 | const struct hdac_ext_bus_ops *ext_ops; |
14752412 TI |
293 | |
294 | /* h/w resources */ | |
295 | unsigned long addr; | |
296 | void __iomem *remap_addr; | |
297 | int irq; | |
d068ebc2 | 298 | |
6720b384 VK |
299 | void __iomem *ppcap; |
300 | void __iomem *spbcap; | |
301 | void __iomem *mlcap; | |
302 | void __iomem *gtscap; | |
303 | void __iomem *drsmcap; | |
304 | ||
d068ebc2 TI |
305 | /* codec linked list */ |
306 | struct list_head codec_list; | |
307 | unsigned int num_codecs; | |
308 | ||
309 | /* link caddr -> codec */ | |
310 | struct hdac_device *caddr_tbl[HDA_MAX_CODEC_ADDRESS + 1]; | |
311 | ||
312 | /* unsolicited event queue */ | |
313 | u32 unsol_queue[HDA_UNSOL_QUEUE_SIZE * 2]; /* ring buffer */ | |
314 | unsigned int unsol_rp, unsol_wp; | |
315 | struct work_struct unsol_work; | |
316 | ||
14752412 TI |
317 | /* bit flags of detected codecs */ |
318 | unsigned long codec_mask; | |
319 | ||
d068ebc2 TI |
320 | /* bit flags of powered codecs */ |
321 | unsigned long codec_powered; | |
322 | ||
14752412 TI |
323 | /* CORB/RIRB */ |
324 | struct hdac_rb corb; | |
325 | struct hdac_rb rirb; | |
326 | unsigned int last_cmd[HDA_MAX_CODECS]; /* last sent command */ | |
88452da9 | 327 | wait_queue_head_t rirb_wq; |
14752412 TI |
328 | |
329 | /* CORB/RIRB and position buffers */ | |
330 | struct snd_dma_buffer rb; | |
331 | struct snd_dma_buffer posbuf; | |
619a1f19 | 332 | int dma_type; /* SNDRV_DMA_TYPE_XXX for CORB/RIRB */ |
14752412 TI |
333 | |
334 | /* hdac_stream linked list */ | |
335 | struct list_head stream_list; | |
336 | ||
337 | /* operation state */ | |
338 | bool chip_init:1; /* h/w initialized */ | |
339 | ||
340 | /* behavior flags */ | |
4d024fe8 | 341 | bool aligned_mmio:1; /* aligned MMIO access */ |
d068ebc2 | 342 | bool sync_write:1; /* sync after verb write */ |
14752412 TI |
343 | bool use_posbuf:1; /* use position buffer */ |
344 | bool snoop:1; /* enable snooping */ | |
345 | bool align_bdle_4k:1; /* BDLE align 4K boundary */ | |
346 | bool reverse_assign:1; /* assign devices in reverse order */ | |
347 | bool corbrp_self_clear:1; /* CORBRP clears itself after reset */ | |
8af42130 | 348 | bool polling_mode:1; |
5f2cb361 | 349 | bool needs_damn_long_delay:1; |
8af42130 BL |
350 | |
351 | int poll_count; | |
14752412 TI |
352 | |
353 | int bdl_pos_adj; /* BDL position adjustment */ | |
d068ebc2 | 354 | |
4106820b MK |
355 | /* delay time in us for dma stop */ |
356 | unsigned int dma_stop_delay; | |
357 | ||
d068ebc2 | 358 | /* locks */ |
14752412 | 359 | spinlock_t reg_lock; |
d068ebc2 | 360 | struct mutex cmd_mutex; |
e61ab9f0 | 361 | struct mutex lock; |
98d8fc6c | 362 | |
ae891abe TI |
363 | /* DRM component interface */ |
364 | struct drm_audio_component *audio_component; | |
029d92c2 | 365 | long display_power_status; |
d31c85fc | 366 | unsigned long display_power_active; |
76f56fae RU |
367 | |
368 | /* parameters required for enhanced capabilities */ | |
369 | int num_streams; | |
370 | int idx; | |
371 | ||
e61ab9f0 | 372 | /* link management */ |
76f56fae | 373 | struct list_head hlink_list; |
76f56fae | 374 | bool cmd_dma_state; |
67ae482a SP |
375 | |
376 | /* factor used to derive STRIPE control value */ | |
377 | unsigned int sdo_limit; | |
d068ebc2 TI |
378 | }; |
379 | ||
380 | int snd_hdac_bus_init(struct hdac_bus *bus, struct device *dev, | |
19abfefd | 381 | const struct hdac_bus_ops *ops); |
d068ebc2 | 382 | void snd_hdac_bus_exit(struct hdac_bus *bus); |
d068ebc2 TI |
383 | int snd_hdac_bus_exec_verb_unlocked(struct hdac_bus *bus, unsigned int addr, |
384 | unsigned int cmd, unsigned int *res); | |
d068ebc2 | 385 | |
f9e5fd1b KV |
386 | void snd_hdac_codec_link_up(struct hdac_device *codec); |
387 | void snd_hdac_codec_link_down(struct hdac_device *codec); | |
7639a06c | 388 | |
14752412 TI |
389 | int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val); |
390 | int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr, | |
391 | unsigned int *res); | |
6720b384 | 392 | int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus); |
14752412 TI |
393 | |
394 | bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset); | |
395 | void snd_hdac_bus_stop_chip(struct hdac_bus *bus); | |
396 | void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus); | |
397 | void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus); | |
398 | void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus); | |
399 | void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus); | |
75383f8d | 400 | int snd_hdac_bus_reset_link(struct hdac_bus *bus, bool full_reset); |
f9e5fd1b | 401 | void snd_hdac_bus_link_power(struct hdac_device *hdev, bool enable); |
14752412 TI |
402 | |
403 | void snd_hdac_bus_update_rirb(struct hdac_bus *bus); | |
473f4145 | 404 | int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status, |
14752412 TI |
405 | void (*ack)(struct hdac_bus *, |
406 | struct hdac_stream *)); | |
407 | ||
304dad30 JK |
408 | int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus); |
409 | void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus); | |
410 | ||
19abfefd TI |
411 | #ifdef CONFIG_SND_HDA_ALIGNED_MMIO |
412 | unsigned int snd_hdac_aligned_read(void __iomem *addr, unsigned int mask); | |
413 | void snd_hdac_aligned_write(unsigned int val, void __iomem *addr, | |
414 | unsigned int mask); | |
4d024fe8 TI |
415 | #define snd_hdac_aligned_mmio(bus) (bus)->aligned_mmio |
416 | #else | |
417 | #define snd_hdac_aligned_mmio(bus) false | |
418 | #define snd_hdac_aligned_read(addr, mask) 0 | |
419 | #define snd_hdac_aligned_write(val, addr, mask) do {} while (0) | |
420 | #endif | |
421 | ||
422 | static inline void snd_hdac_reg_writeb(struct hdac_bus *bus, void __iomem *addr, | |
423 | u8 val) | |
424 | { | |
425 | if (snd_hdac_aligned_mmio(bus)) | |
426 | snd_hdac_aligned_write(val, addr, 0xff); | |
427 | else | |
428 | writeb(val, addr); | |
429 | } | |
430 | ||
431 | static inline void snd_hdac_reg_writew(struct hdac_bus *bus, void __iomem *addr, | |
432 | u16 val) | |
433 | { | |
434 | if (snd_hdac_aligned_mmio(bus)) | |
435 | snd_hdac_aligned_write(val, addr, 0xffff); | |
436 | else | |
437 | writew(val, addr); | |
438 | } | |
439 | ||
440 | static inline u8 snd_hdac_reg_readb(struct hdac_bus *bus, void __iomem *addr) | |
441 | { | |
442 | return snd_hdac_aligned_mmio(bus) ? | |
443 | snd_hdac_aligned_read(addr, 0xff) : readb(addr); | |
444 | } | |
445 | ||
446 | static inline u16 snd_hdac_reg_readw(struct hdac_bus *bus, void __iomem *addr) | |
447 | { | |
448 | return snd_hdac_aligned_mmio(bus) ? | |
449 | snd_hdac_aligned_read(addr, 0xffff) : readw(addr); | |
450 | } | |
451 | ||
452 | #define snd_hdac_reg_writel(bus, addr, val) writel(val, addr) | |
453 | #define snd_hdac_reg_readl(bus, addr) readl(addr) | |
c19bd02e CR |
454 | #define snd_hdac_reg_writeq(bus, addr, val) writeq(val, addr) |
455 | #define snd_hdac_reg_readq(bus, addr) readq(addr) | |
19abfefd | 456 | |
14752412 TI |
457 | /* |
458 | * macros for easy use | |
459 | */ | |
2c1f8138 | 460 | #define _snd_hdac_chip_writeb(chip, reg, value) \ |
4d024fe8 | 461 | snd_hdac_reg_writeb(chip, (chip)->remap_addr + (reg), value) |
2c1f8138 | 462 | #define _snd_hdac_chip_readb(chip, reg) \ |
4d024fe8 | 463 | snd_hdac_reg_readb(chip, (chip)->remap_addr + (reg)) |
2c1f8138 | 464 | #define _snd_hdac_chip_writew(chip, reg, value) \ |
4d024fe8 | 465 | snd_hdac_reg_writew(chip, (chip)->remap_addr + (reg), value) |
2c1f8138 | 466 | #define _snd_hdac_chip_readw(chip, reg) \ |
4d024fe8 | 467 | snd_hdac_reg_readw(chip, (chip)->remap_addr + (reg)) |
2c1f8138 | 468 | #define _snd_hdac_chip_writel(chip, reg, value) \ |
4d024fe8 | 469 | snd_hdac_reg_writel(chip, (chip)->remap_addr + (reg), value) |
2c1f8138 | 470 | #define _snd_hdac_chip_readl(chip, reg) \ |
4d024fe8 | 471 | snd_hdac_reg_readl(chip, (chip)->remap_addr + (reg)) |
14752412 TI |
472 | |
473 | /* read/write a register, pass without AZX_REG_ prefix */ | |
474 | #define snd_hdac_chip_writel(chip, reg, value) \ | |
2c1f8138 | 475 | _snd_hdac_chip_writel(chip, AZX_REG_ ## reg, value) |
14752412 | 476 | #define snd_hdac_chip_writew(chip, reg, value) \ |
2c1f8138 | 477 | _snd_hdac_chip_writew(chip, AZX_REG_ ## reg, value) |
14752412 | 478 | #define snd_hdac_chip_writeb(chip, reg, value) \ |
2c1f8138 | 479 | _snd_hdac_chip_writeb(chip, AZX_REG_ ## reg, value) |
14752412 | 480 | #define snd_hdac_chip_readl(chip, reg) \ |
2c1f8138 | 481 | _snd_hdac_chip_readl(chip, AZX_REG_ ## reg) |
14752412 | 482 | #define snd_hdac_chip_readw(chip, reg) \ |
2c1f8138 | 483 | _snd_hdac_chip_readw(chip, AZX_REG_ ## reg) |
14752412 | 484 | #define snd_hdac_chip_readb(chip, reg) \ |
2c1f8138 | 485 | _snd_hdac_chip_readb(chip, AZX_REG_ ## reg) |
14752412 TI |
486 | |
487 | /* update a register, pass without AZX_REG_ prefix */ | |
488 | #define snd_hdac_chip_updatel(chip, reg, mask, val) \ | |
489 | snd_hdac_chip_writel(chip, reg, \ | |
490 | (snd_hdac_chip_readl(chip, reg) & ~(mask)) | (val)) | |
491 | #define snd_hdac_chip_updatew(chip, reg, mask, val) \ | |
492 | snd_hdac_chip_writew(chip, reg, \ | |
493 | (snd_hdac_chip_readw(chip, reg) & ~(mask)) | (val)) | |
494 | #define snd_hdac_chip_updateb(chip, reg, mask, val) \ | |
495 | snd_hdac_chip_writeb(chip, reg, \ | |
496 | (snd_hdac_chip_readb(chip, reg) & ~(mask)) | (val)) | |
497 | ||
62582341 PLB |
498 | /* update register macro */ |
499 | #define snd_hdac_updatel(addr, reg, mask, val) \ | |
500 | writel(((readl(addr + reg) & ~(mask)) | (val)), addr + reg) | |
501 | ||
502 | #define snd_hdac_updatew(addr, reg, mask, val) \ | |
503 | writew(((readw(addr + reg) & ~(mask)) | (val)), addr + reg) | |
504 | ||
14752412 TI |
505 | /* |
506 | * HD-audio stream | |
507 | */ | |
508 | struct hdac_stream { | |
509 | struct hdac_bus *bus; | |
510 | struct snd_dma_buffer bdl; /* BDL buffer */ | |
511 | __le32 *posbuf; /* position buffer pointer */ | |
512 | int direction; /* playback / capture (SNDRV_PCM_STREAM_*) */ | |
513 | ||
514 | unsigned int bufsize; /* size of the play buffer in bytes */ | |
515 | unsigned int period_bytes; /* size of the period in bytes */ | |
516 | unsigned int frags; /* number for period in the play buffer */ | |
517 | unsigned int fifo_size; /* FIFO size */ | |
518 | ||
519 | void __iomem *sd_addr; /* stream descriptor pointer */ | |
520 | ||
62582341 PLB |
521 | void __iomem *spib_addr; /* software position in buffers stream pointer */ |
522 | void __iomem *fifo_addr; /* software position Max fifos stream pointer */ | |
523 | ||
524 | void __iomem *dpibr_addr; /* DMA position in buffer resume pointer */ | |
525 | u32 dpib; /* DMA position in buffer */ | |
526 | u32 lpib; /* Linear position in buffer */ | |
527 | ||
14752412 TI |
528 | u32 sd_int_sta_mask; /* stream int status mask */ |
529 | ||
530 | /* pcm support */ | |
531 | struct snd_pcm_substream *substream; /* assigned substream, | |
532 | * set in PCM open | |
533 | */ | |
4a9ce6e4 | 534 | struct snd_compr_stream *cstream; |
14752412 TI |
535 | unsigned int format_val; /* format value to be set in the |
536 | * controller and the codec | |
537 | */ | |
538 | unsigned char stream_tag; /* assigned stream */ | |
539 | unsigned char index; /* stream index */ | |
540 | int assigned_key; /* last device# key assigned to */ | |
541 | ||
542 | bool opened:1; | |
543 | bool running:1; | |
6d23c8f5 | 544 | bool prepared:1; |
14752412 | 545 | bool no_period_wakeup:1; |
8f3f600b | 546 | bool locked:1; |
e38e486d | 547 | bool stripe:1; /* apply stripe control */ |
14752412 | 548 | |
4a9ce6e4 | 549 | u64 curr_pos; |
14752412 TI |
550 | /* timestamp */ |
551 | unsigned long start_wallclk; /* start + minimum wallclk */ | |
552 | unsigned long period_wallclk; /* wallclk for period */ | |
553 | struct timecounter tc; | |
554 | struct cyclecounter cc; | |
555 | int delay_negative_threshold; | |
556 | ||
557 | struct list_head list; | |
8f3f600b TI |
558 | #ifdef CONFIG_SND_HDA_DSP_LOADER |
559 | /* DSP access mutex */ | |
560 | struct mutex dsp_mutex; | |
561 | #endif | |
14752412 TI |
562 | }; |
563 | ||
564 | void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev, | |
565 | int idx, int direction, int tag); | |
566 | struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus, | |
567 | struct snd_pcm_substream *substream); | |
ac3467ad | 568 | void snd_hdac_stream_release_locked(struct hdac_stream *azx_dev); |
14752412 | 569 | void snd_hdac_stream_release(struct hdac_stream *azx_dev); |
4308c9b0 JK |
570 | struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus, |
571 | int dir, int stream_tag); | |
14752412 TI |
572 | |
573 | int snd_hdac_stream_setup(struct hdac_stream *azx_dev); | |
574 | void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev); | |
575 | int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev); | |
86f6501b JK |
576 | int snd_hdac_stream_set_params(struct hdac_stream *azx_dev, |
577 | unsigned int format_val); | |
4fe20d62 | 578 | void snd_hdac_stream_start(struct hdac_stream *azx_dev); |
14752412 | 579 | void snd_hdac_stream_stop(struct hdac_stream *azx_dev); |
24ad3835 | 580 | void snd_hdac_stop_streams(struct hdac_bus *bus); |
12054f0c | 581 | void snd_hdac_stop_streams_and_chip(struct hdac_bus *bus); |
14752412 TI |
582 | void snd_hdac_stream_reset(struct hdac_stream *azx_dev); |
583 | void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set, | |
584 | unsigned int streams, unsigned int reg); | |
585 | void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start, | |
586 | unsigned int streams); | |
587 | void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev, | |
588 | unsigned int streams); | |
5dd3d271 SP |
589 | int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus, |
590 | struct snd_pcm_substream *substream); | |
591 | ||
62582341 PLB |
592 | void snd_hdac_stream_spbcap_enable(struct hdac_bus *chip, |
593 | bool enable, int index); | |
594 | int snd_hdac_stream_set_spib(struct hdac_bus *bus, | |
595 | struct hdac_stream *azx_dev, u32 value); | |
596 | int snd_hdac_stream_get_spbmaxfifo(struct hdac_bus *bus, | |
597 | struct hdac_stream *azx_dev); | |
598 | void snd_hdac_stream_drsm_enable(struct hdac_bus *bus, | |
599 | bool enable, int index); | |
efffb014 | 600 | int snd_hdac_stream_wait_drsm(struct hdac_stream *azx_dev); |
62582341 PLB |
601 | int snd_hdac_stream_set_dpibr(struct hdac_bus *bus, |
602 | struct hdac_stream *azx_dev, u32 value); | |
603 | int snd_hdac_stream_set_lpib(struct hdac_stream *azx_dev, u32 value); | |
604 | ||
14752412 TI |
605 | /* |
606 | * macros for easy use | |
607 | */ | |
14752412 TI |
608 | /* read/write a register, pass without AZX_REG_ prefix */ |
609 | #define snd_hdac_stream_writel(dev, reg, value) \ | |
4d024fe8 | 610 | snd_hdac_reg_writel((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value) |
14752412 | 611 | #define snd_hdac_stream_writew(dev, reg, value) \ |
4d024fe8 | 612 | snd_hdac_reg_writew((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value) |
14752412 | 613 | #define snd_hdac_stream_writeb(dev, reg, value) \ |
4d024fe8 | 614 | snd_hdac_reg_writeb((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value) |
14752412 | 615 | #define snd_hdac_stream_readl(dev, reg) \ |
4d024fe8 | 616 | snd_hdac_reg_readl((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg) |
14752412 | 617 | #define snd_hdac_stream_readw(dev, reg) \ |
4d024fe8 | 618 | snd_hdac_reg_readw((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg) |
14752412 | 619 | #define snd_hdac_stream_readb(dev, reg) \ |
4d024fe8 | 620 | snd_hdac_reg_readb((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg) |
3cab69d9 | 621 | #define snd_hdac_stream_readb_poll(dev, reg, val, cond, delay_us, timeout_us) \ |
556a11a0 AS |
622 | read_poll_timeout_atomic(snd_hdac_reg_readb, val, cond, delay_us, timeout_us, \ |
623 | false, (dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg) | |
3cab69d9 | 624 | #define snd_hdac_stream_readl_poll(dev, reg, val, cond, delay_us, timeout_us) \ |
556a11a0 AS |
625 | read_poll_timeout_atomic(snd_hdac_reg_readl, val, cond, delay_us, timeout_us, \ |
626 | false, (dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg) | |
14752412 TI |
627 | |
628 | /* update a register, pass without AZX_REG_ prefix */ | |
629 | #define snd_hdac_stream_updatel(dev, reg, mask, val) \ | |
630 | snd_hdac_stream_writel(dev, reg, \ | |
631 | (snd_hdac_stream_readl(dev, reg) & \ | |
632 | ~(mask)) | (val)) | |
633 | #define snd_hdac_stream_updatew(dev, reg, mask, val) \ | |
634 | snd_hdac_stream_writew(dev, reg, \ | |
635 | (snd_hdac_stream_readw(dev, reg) & \ | |
636 | ~(mask)) | (val)) | |
637 | #define snd_hdac_stream_updateb(dev, reg, mask, val) \ | |
638 | snd_hdac_stream_writeb(dev, reg, \ | |
639 | (snd_hdac_stream_readb(dev, reg) & \ | |
640 | ~(mask)) | (val)) | |
641 | ||
8f3f600b TI |
642 | #ifdef CONFIG_SND_HDA_DSP_LOADER |
643 | /* DSP lock helpers */ | |
644 | #define snd_hdac_dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex) | |
645 | #define snd_hdac_dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex) | |
646 | #define snd_hdac_dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex) | |
647 | #define snd_hdac_stream_is_locked(dev) ((dev)->locked) | |
648 | /* DSP loader helpers */ | |
649 | int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format, | |
650 | unsigned int byte_size, struct snd_dma_buffer *bufp); | |
651 | void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start); | |
652 | void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev, | |
653 | struct snd_dma_buffer *dmab); | |
654 | #else /* CONFIG_SND_HDA_DSP_LOADER */ | |
655 | #define snd_hdac_dsp_lock_init(dev) do {} while (0) | |
656 | #define snd_hdac_dsp_lock(dev) do {} while (0) | |
657 | #define snd_hdac_dsp_unlock(dev) do {} while (0) | |
658 | #define snd_hdac_stream_is_locked(dev) 0 | |
659 | ||
660 | static inline int | |
661 | snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format, | |
662 | unsigned int byte_size, struct snd_dma_buffer *bufp) | |
663 | { | |
664 | return 0; | |
665 | } | |
666 | ||
667 | static inline void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start) | |
668 | { | |
669 | } | |
670 | ||
671 | static inline void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev, | |
672 | struct snd_dma_buffer *dmab) | |
673 | { | |
674 | } | |
675 | #endif /* CONFIG_SND_HDA_DSP_LOADER */ | |
676 | ||
677 | ||
71fc4c7e TI |
678 | /* |
679 | * generic array helpers | |
680 | */ | |
681 | void *snd_array_new(struct snd_array *array); | |
682 | void snd_array_free(struct snd_array *array); | |
683 | static inline void snd_array_init(struct snd_array *array, unsigned int size, | |
684 | unsigned int align) | |
685 | { | |
686 | array->elem_size = size; | |
687 | array->alloc_align = align; | |
688 | } | |
689 | ||
690 | static inline void *snd_array_elem(struct snd_array *array, unsigned int idx) | |
691 | { | |
692 | return array->list + idx * array->elem_size; | |
693 | } | |
694 | ||
695 | static inline unsigned int snd_array_index(struct snd_array *array, void *ptr) | |
696 | { | |
697 | return (unsigned long)(ptr - array->list) / array->elem_size; | |
698 | } | |
699 | ||
a9c2dfc8 TI |
700 | /* a helper macro to iterate for each snd_array element */ |
701 | #define snd_array_for_each(array, idx, ptr) \ | |
702 | for ((idx) = 0, (ptr) = (array)->list; (idx) < (array)->used; \ | |
703 | (ptr) = snd_array_elem(array, ++(idx))) | |
704 | ||
e3d280fc | 705 | #endif /* __SOUND_HDAUDIO_H */ |