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1a59d1b8 | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
1da177e4 | 2 | /* |
c1017a4c | 3 | * Copyright (c) by Jaroslav Kysela <perex@perex.cz>, |
1da177e4 LT |
4 | * Creative Labs, Inc. |
5 | * Definitions for EMU10K1 (SB Live!) chips | |
1da177e4 | 6 | */ |
674e95ca DH |
7 | #ifndef __SOUND_EMU10K1_H |
8 | #define __SOUND_EMU10K1_H | |
1da177e4 | 9 | |
1da177e4 LT |
10 | |
11 | #include <sound/pcm.h> | |
12 | #include <sound/rawmidi.h> | |
13 | #include <sound/hwdep.h> | |
14 | #include <sound/ac97_codec.h> | |
15 | #include <sound/util_mem.h> | |
16 | #include <sound/pcm-indirect.h> | |
17 | #include <sound/timer.h> | |
18 | #include <linux/interrupt.h> | |
62932df8 | 19 | #include <linux/mutex.h> |
b209c4df | 20 | #include <linux/firmware.h> |
6cbbfe1c | 21 | #include <linux/io.h> |
9adfbfb6 | 22 | |
674e95ca | 23 | #include <uapi/sound/emu10k1.h> |
1da177e4 | 24 | |
1da177e4 LT |
25 | /* ------------------- DEFINES -------------------- */ |
26 | ||
27 | #define EMUPAGESIZE 4096 | |
7241ea55 PZ |
28 | #define MAXPAGES0 4096 /* 32 bit mode */ |
29 | #define MAXPAGES1 8192 /* 31 bit mode */ | |
1da177e4 | 30 | #define NUM_G 64 /* use all channels */ |
1da177e4 LT |
31 | #define NUM_EFX_PLAYBACK 16 |
32 | ||
33 | /* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */ | |
34 | #define EMU10K1_DMA_MASK 0x7fffffffUL /* 31bit */ | |
7241ea55 | 35 | #define AUDIGY_DMA_MASK 0xffffffffUL /* 32bit mode */ |
1da177e4 LT |
36 | |
37 | #define TMEMSIZE 256*1024 | |
1da177e4 LT |
38 | |
39 | #define IP_TO_CP(ip) ((ip == 0) ? 0 : (((0x00001000uL | (ip & 0x00000FFFL)) << (((ip >> 12) & 0x000FL) + 4)) & 0xFFFF0000uL)) | |
40 | ||
60571ac9 OB |
41 | // This is used to define hardware bit-fields (sub-registers) by combining |
42 | // the bit shift and count with the actual register address. The passed | |
43 | // mask must represent a single run of adjacent bits. | |
44 | // The non-concatenating (_NC) variant should be used directly only for | |
45 | // sub-registers that do not follow the <register>_<field> naming pattern. | |
46 | #define SUB_REG_NC(reg, field, mask) \ | |
47 | enum { \ | |
48 | field ## _MASK = mask, \ | |
49 | field = reg | \ | |
50 | (__builtin_ctz(mask) << 16) | \ | |
51 | (__builtin_popcount(mask) << 24), \ | |
52 | }; | |
53 | #define SUB_REG(reg, field, mask) SUB_REG_NC(reg, reg ## _ ## field, mask) | |
54 | ||
55 | // Macros for manipulating values of bit-fields declared using the above macros. | |
56 | // Best used with constant register addresses, as otherwise quite some code is | |
57 | // generated. The actual register read/write functions handle combined addresses | |
58 | // automatically, so use of these macros conveys no advantage when accessing a | |
59 | // single sub-register at a time. | |
60 | #define REG_SHIFT(r) (((r) >> 16) & 0x1f) | |
61 | #define REG_SIZE(r) (((r) >> 24) & 0x1f) | |
62 | #define REG_MASK0(r) ((1U << REG_SIZE(r)) - 1U) | |
63 | #define REG_MASK(r) (REG_MASK0(r) << REG_SHIFT(r)) | |
64 | #define REG_VAL_GET(r, v) ((v & REG_MASK(r)) >> REG_SHIFT(r)) | |
65 | #define REG_VAL_PUT(r, v) ((v) << REG_SHIFT(r)) | |
66 | ||
1da177e4 LT |
67 | // Audigy specify registers are prefixed with 'A_' |
68 | ||
69 | /************************************************************************************************/ | |
70 | /* PCI function 0 registers, address = <val> + PCIBASE0 */ | |
71 | /************************************************************************************************/ | |
72 | ||
73 | #define PTR 0x00 /* Indexed register set pointer register */ | |
74 | /* NOTE: The CHANNELNUM and ADDRESS words can */ | |
75 | /* be modified independently of each other. */ | |
76 | #define PTR_CHANNELNUM_MASK 0x0000003f /* For each per-channel register, indicates the */ | |
77 | /* channel number of the register to be */ | |
78 | /* accessed. For non per-channel registers the */ | |
79 | /* value should be set to zero. */ | |
80 | #define PTR_ADDRESS_MASK 0x07ff0000 /* Register index */ | |
81 | #define A_PTR_ADDRESS_MASK 0x0fff0000 | |
82 | ||
83 | #define DATA 0x04 /* Indexed register set data register */ | |
84 | ||
85 | #define IPR 0x08 /* Global interrupt pending register */ | |
86 | /* Clear pending interrupts by writing a 1 to */ | |
87 | /* the relevant bits and zero to the other bits */ | |
6e4abc40 JCD |
88 | #define IPR_P16V 0x80000000 /* Bit set when the CA0151 P16V chip wishes |
89 | to interrupt */ | |
145ec1fd OB |
90 | #define IPR_WATERMARK_REACHED 0x40000000 |
91 | #define IPR_A_GPIO 0x20000000 /* GPIO input pin change */ | |
1da177e4 LT |
92 | |
93 | /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */ | |
94 | #define IPR_A_MIDITRANSBUFEMPTY2 0x10000000 /* MIDI UART transmit buffer empty */ | |
95 | #define IPR_A_MIDIRECVBUFEMPTY2 0x08000000 /* MIDI UART receive buffer empty */ | |
96 | ||
97 | #define IPR_SPDIFBUFFULL 0x04000000 /* SPDIF capture related, 10k2 only? (RE) */ | |
98 | #define IPR_SPDIFBUFHALFFULL 0x02000000 /* SPDIF capture related? (RE) */ | |
99 | ||
100 | #define IPR_SAMPLERATETRACKER 0x01000000 /* Sample rate tracker lock status change */ | |
101 | #define IPR_FXDSP 0x00800000 /* Enable FX DSP interrupts */ | |
102 | #define IPR_FORCEINT 0x00400000 /* Force Sound Blaster interrupt */ | |
103 | #define IPR_PCIERROR 0x00200000 /* PCI bus error */ | |
104 | #define IPR_VOLINCR 0x00100000 /* Volume increment button pressed */ | |
105 | #define IPR_VOLDECR 0x00080000 /* Volume decrement button pressed */ | |
106 | #define IPR_MUTE 0x00040000 /* Mute button pressed */ | |
107 | #define IPR_MICBUFFULL 0x00020000 /* Microphone buffer full */ | |
108 | #define IPR_MICBUFHALFFULL 0x00010000 /* Microphone buffer half full */ | |
109 | #define IPR_ADCBUFFULL 0x00008000 /* ADC buffer full */ | |
110 | #define IPR_ADCBUFHALFFULL 0x00004000 /* ADC buffer half full */ | |
111 | #define IPR_EFXBUFFULL 0x00002000 /* Effects buffer full */ | |
112 | #define IPR_EFXBUFHALFFULL 0x00001000 /* Effects buffer half full */ | |
113 | #define IPR_GPSPDIFSTATUSCHANGE 0x00000800 /* GPSPDIF channel status change */ | |
114 | #define IPR_CDROMSTATUSCHANGE 0x00000400 /* CD-ROM channel status change */ | |
115 | #define IPR_INTERVALTIMER 0x00000200 /* Interval timer terminal count */ | |
116 | #define IPR_MIDITRANSBUFEMPTY 0x00000100 /* MIDI UART transmit buffer empty */ | |
117 | #define IPR_MIDIRECVBUFEMPTY 0x00000080 /* MIDI UART receive buffer empty */ | |
118 | #define IPR_CHANNELLOOP 0x00000040 /* Channel (half) loop interrupt(s) pending */ | |
119 | #define IPR_CHANNELNUMBERMASK 0x0000003f /* When IPR_CHANNELLOOP is set, indicates the */ | |
120 | /* highest set channel in CLIPL, CLIPH, HLIPL, */ | |
a869057c | 121 | /* or HLIPH. When IPR is written with CL set, */ |
1da177e4 | 122 | /* the bit in H/CLIPL or H/CLIPH corresponding */ |
a869057c | 123 | /* to the CN value written will be cleared. */ |
1da177e4 LT |
124 | |
125 | #define INTE 0x0c /* Interrupt enable register */ | |
126 | #define INTE_VIRTUALSB_MASK 0xc0000000 /* Virtual Soundblaster I/O port capture */ | |
127 | #define INTE_VIRTUALSB_220 0x00000000 /* Capture at I/O base address 0x220-0x22f */ | |
128 | #define INTE_VIRTUALSB_240 0x40000000 /* Capture at I/O base address 0x240 */ | |
129 | #define INTE_VIRTUALSB_260 0x80000000 /* Capture at I/O base address 0x260 */ | |
130 | #define INTE_VIRTUALSB_280 0xc0000000 /* Capture at I/O base address 0x280 */ | |
131 | #define INTE_VIRTUALMPU_MASK 0x30000000 /* Virtual MPU I/O port capture */ | |
132 | #define INTE_VIRTUALMPU_300 0x00000000 /* Capture at I/O base address 0x300-0x301 */ | |
133 | #define INTE_VIRTUALMPU_310 0x10000000 /* Capture at I/O base address 0x310 */ | |
134 | #define INTE_VIRTUALMPU_320 0x20000000 /* Capture at I/O base address 0x320 */ | |
135 | #define INTE_VIRTUALMPU_330 0x30000000 /* Capture at I/O base address 0x330 */ | |
136 | #define INTE_MASTERDMAENABLE 0x08000000 /* Master DMA emulation at 0x000-0x00f */ | |
137 | #define INTE_SLAVEDMAENABLE 0x04000000 /* Slave DMA emulation at 0x0c0-0x0df */ | |
138 | #define INTE_MASTERPICENABLE 0x02000000 /* Master PIC emulation at 0x020-0x021 */ | |
139 | #define INTE_SLAVEPICENABLE 0x01000000 /* Slave PIC emulation at 0x0a0-0x0a1 */ | |
140 | #define INTE_VSBENABLE 0x00800000 /* Enable virtual Soundblaster */ | |
141 | #define INTE_ADLIBENABLE 0x00400000 /* Enable AdLib emulation at 0x388-0x38b */ | |
142 | #define INTE_MPUENABLE 0x00200000 /* Enable virtual MPU */ | |
143 | #define INTE_FORCEINT 0x00100000 /* Continuously assert INTAN */ | |
144 | ||
145 | #define INTE_MRHANDENABLE 0x00080000 /* Enable the "Mr. Hand" logic */ | |
146 | /* NOTE: There is no reason to use this under */ | |
147 | /* Linux, and it will cause odd hardware */ | |
148 | /* behavior and possibly random segfaults and */ | |
149 | /* lockups if enabled. */ | |
150 | ||
145ec1fd OB |
151 | #define INTE_A_GPIOENABLE 0x00040000 /* Enable GPIO input change interrupts */ |
152 | ||
1da177e4 LT |
153 | /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */ |
154 | #define INTE_A_MIDITXENABLE2 0x00020000 /* Enable MIDI transmit-buffer-empty interrupts */ | |
155 | #define INTE_A_MIDIRXENABLE2 0x00010000 /* Enable MIDI receive-buffer-empty interrupts */ | |
156 | ||
145ec1fd OB |
157 | #define INTE_A_SPDIF_BUFFULL_ENABLE 0x00008000 |
158 | #define INTE_A_SPDIF_HALFBUFFULL_ENABLE 0x00004000 | |
1da177e4 LT |
159 | |
160 | #define INTE_SAMPLERATETRACKER 0x00002000 /* Enable sample rate tracker interrupts */ | |
161 | /* NOTE: This bit must always be enabled */ | |
162 | #define INTE_FXDSPENABLE 0x00001000 /* Enable FX DSP interrupts */ | |
163 | #define INTE_PCIERRORENABLE 0x00000800 /* Enable PCI bus error interrupts */ | |
164 | #define INTE_VOLINCRENABLE 0x00000400 /* Enable volume increment button interrupts */ | |
165 | #define INTE_VOLDECRENABLE 0x00000200 /* Enable volume decrement button interrupts */ | |
166 | #define INTE_MUTEENABLE 0x00000100 /* Enable mute button interrupts */ | |
167 | #define INTE_MICBUFENABLE 0x00000080 /* Enable microphone buffer interrupts */ | |
168 | #define INTE_ADCBUFENABLE 0x00000040 /* Enable ADC buffer interrupts */ | |
169 | #define INTE_EFXBUFENABLE 0x00000020 /* Enable Effects buffer interrupts */ | |
170 | #define INTE_GPSPDIFENABLE 0x00000010 /* Enable GPSPDIF status interrupts */ | |
171 | #define INTE_CDSPDIFENABLE 0x00000008 /* Enable CDSPDIF status interrupts */ | |
172 | #define INTE_INTERVALTIMERENB 0x00000004 /* Enable interval timer interrupts */ | |
173 | #define INTE_MIDITXENABLE 0x00000002 /* Enable MIDI transmit-buffer-empty interrupts */ | |
174 | #define INTE_MIDIRXENABLE 0x00000001 /* Enable MIDI receive-buffer-empty interrupts */ | |
175 | ||
176 | #define WC 0x10 /* Wall Clock register */ | |
60571ac9 OB |
177 | SUB_REG(WC, SAMPLECOUNTER, 0x03FFFFC0) /* Sample periods elapsed since reset */ |
178 | SUB_REG(WC, CURRENTCHANNEL, 0x0000003F) /* Channel [0..63] currently being serviced */ | |
1da177e4 LT |
179 | /* NOTE: Each channel takes 1/64th of a sample */ |
180 | /* period to be serviced. */ | |
181 | ||
182 | #define HCFG 0x14 /* Hardware config register */ | |
183 | /* NOTE: There is no reason to use the legacy */ | |
184 | /* SoundBlaster emulation stuff described below */ | |
185 | /* under Linux, and all kinds of weird hardware */ | |
186 | /* behavior can result if you try. Don't. */ | |
187 | #define HCFG_LEGACYFUNC_MASK 0xe0000000 /* Legacy function number */ | |
188 | #define HCFG_LEGACYFUNC_MPU 0x00000000 /* Legacy MPU */ | |
189 | #define HCFG_LEGACYFUNC_SB 0x40000000 /* Legacy SB */ | |
190 | #define HCFG_LEGACYFUNC_AD 0x60000000 /* Legacy AD */ | |
191 | #define HCFG_LEGACYFUNC_MPIC 0x80000000 /* Legacy MPIC */ | |
192 | #define HCFG_LEGACYFUNC_MDMA 0xa0000000 /* Legacy MDMA */ | |
193 | #define HCFG_LEGACYFUNC_SPCI 0xc0000000 /* Legacy SPCI */ | |
194 | #define HCFG_LEGACYFUNC_SDMA 0xe0000000 /* Legacy SDMA */ | |
195 | #define HCFG_IOCAPTUREADDR 0x1f000000 /* The 4 LSBs of the captured I/O address. */ | |
196 | #define HCFG_LEGACYWRITE 0x00800000 /* 1 = write, 0 = read */ | |
197 | #define HCFG_LEGACYWORD 0x00400000 /* 1 = word, 0 = byte */ | |
198 | #define HCFG_LEGACYINT 0x00200000 /* 1 = legacy event captured. Write 1 to clear. */ | |
199 | /* NOTE: The rest of the bits in this register */ | |
200 | /* _are_ relevant under Linux. */ | |
9f4bd5dd JCD |
201 | #define HCFG_PUSH_BUTTON_ENABLE 0x00100000 /* Enables Volume Inc/Dec and Mute functions */ |
202 | #define HCFG_BAUD_RATE 0x00080000 /* 0 = 48kHz, 1 = 44.1kHz */ | |
203 | #define HCFG_EXPANDED_MEM 0x00040000 /* 1 = any 16M of 4G addr, 0 = 32M of 2G addr */ | |
204 | #define HCFG_CODECFORMAT_MASK 0x00030000 /* CODEC format */ | |
205 | ||
206 | /* Specific to Alice2, CA0102 */ | |
a869057c | 207 | |
9f4bd5dd JCD |
208 | #define HCFG_CODECFORMAT_AC97_1 0x00000000 /* AC97 CODEC format -- Ver 1.03 */ |
209 | #define HCFG_CODECFORMAT_AC97_2 0x00010000 /* AC97 CODEC format -- Ver 2.1 */ | |
210 | #define HCFG_AUTOMUTE_ASYNC 0x00008000 /* When set, the async sample rate convertors */ | |
211 | /* will automatically mute their output when */ | |
212 | /* they are not rate-locked to the external */ | |
213 | /* async audio source */ | |
214 | #define HCFG_AUTOMUTE_SPDIF 0x00004000 /* When set, the async sample rate convertors */ | |
215 | /* will automatically mute their output when */ | |
216 | /* the SPDIF V-bit indicates invalid audio */ | |
217 | #define HCFG_EMU32_SLAVE 0x00002000 /* 0 = Master, 1 = Slave. Slave for EMU1010 */ | |
218 | #define HCFG_SLOW_RAMP 0x00001000 /* Increases Send Smoothing time constant */ | |
219 | /* 0x00000800 not used on Alice2 */ | |
220 | #define HCFG_PHASE_TRACK_MASK 0x00000700 /* When set, forces corresponding input to */ | |
221 | /* phase track the previous input. */ | |
222 | /* I2S0 can phase track the last S/PDIF input */ | |
223 | #define HCFG_I2S_ASRC_ENABLE 0x00000070 /* When set, enables asynchronous sample rate */ | |
224 | /* conversion for the corresponding */ | |
225 | /* I2S format input */ | |
226 | /* Rest of HCFG 0x0000000f same as below. LOCKSOUNDCACHE etc. */ | |
227 | ||
9f4bd5dd | 228 | /* Older chips */ |
a869057c | 229 | |
1da177e4 LT |
230 | #define HCFG_CODECFORMAT_AC97 0x00000000 /* AC97 CODEC format -- Primary Output */ |
231 | #define HCFG_CODECFORMAT_I2S 0x00010000 /* I2S CODEC format -- Secondary (Rear) Output */ | |
232 | #define HCFG_GPINPUT0 0x00004000 /* External pin112 */ | |
233 | #define HCFG_GPINPUT1 0x00002000 /* External pin110 */ | |
234 | #define HCFG_GPOUTPUT_MASK 0x00001c00 /* External pins which may be controlled */ | |
235 | #define HCFG_GPOUT0 0x00001000 /* External pin? (spdif enable on 5.1) */ | |
236 | #define HCFG_GPOUT1 0x00000800 /* External pin? (IR) */ | |
237 | #define HCFG_GPOUT2 0x00000400 /* External pin? (IR) */ | |
238 | #define HCFG_JOYENABLE 0x00000200 /* Internal joystick enable */ | |
239 | #define HCFG_PHASETRACKENABLE 0x00000100 /* Phase tracking enable */ | |
240 | /* 1 = Force all 3 async digital inputs to use */ | |
241 | /* the same async sample rate tracker (ZVIDEO) */ | |
242 | #define HCFG_AC3ENABLE_MASK 0x000000e0 /* AC3 async input control - Not implemented */ | |
243 | #define HCFG_AC3ENABLE_ZVIDEO 0x00000080 /* Channels 0 and 1 replace ZVIDEO */ | |
244 | #define HCFG_AC3ENABLE_CDSPDIF 0x00000040 /* Channels 0 and 1 replace CDSPDIF */ | |
245 | #define HCFG_AC3ENABLE_GPSPDIF 0x00000020 /* Channels 0 and 1 replace GPSPDIF */ | |
246 | #define HCFG_AUTOMUTE 0x00000010 /* When set, the async sample rate convertors */ | |
247 | /* will automatically mute their output when */ | |
248 | /* they are not rate-locked to the external */ | |
249 | /* async audio source */ | |
250 | #define HCFG_LOCKSOUNDCACHE 0x00000008 /* 1 = Cancel bustmaster accesses to soundcache */ | |
251 | /* NOTE: This should generally never be used. */ | |
60571ac9 | 252 | SUB_REG(HCFG, LOCKTANKCACHE, 0x00000004) /* 1 = Cancel bustmaster accesses to tankcache */ |
1da177e4 | 253 | /* NOTE: This should generally never be used. */ |
1da177e4 LT |
254 | #define HCFG_MUTEBUTTONENABLE 0x00000002 /* 1 = Master mute button sets AUDIOENABLE = 0. */ |
255 | /* NOTE: This is a 'cheap' way to implement a */ | |
256 | /* master mute function on the mute button, and */ | |
257 | /* in general should not be used unless a more */ | |
258 | /* sophisticated master mute function has not */ | |
259 | /* been written. */ | |
260 | #define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */ | |
261 | /* Should be set to 1 when the EMU10K1 is */ | |
262 | /* completely initialized. */ | |
263 | ||
a869057c | 264 | // On Audigy, the MPU port moved to the 0x70-0x74 ptr registers |
1da177e4 LT |
265 | |
266 | #define MUDATA 0x18 /* MPU401 data register (8 bits) */ | |
267 | ||
268 | #define MUCMD 0x19 /* MPU401 command register (8 bits) */ | |
269 | #define MUCMD_RESET 0xff /* RESET command */ | |
270 | #define MUCMD_ENTERUARTMODE 0x3f /* Enter_UART_mode command */ | |
271 | /* NOTE: All other commands are ignored */ | |
272 | ||
273 | #define MUSTAT MUCMD /* MPU401 status register (8 bits) */ | |
274 | #define MUSTAT_IRDYN 0x80 /* 0 = MIDI data or command ACK */ | |
275 | #define MUSTAT_ORDYN 0x40 /* 0 = MUDATA can accept a command or data */ | |
276 | ||
a1c87c0b | 277 | #define A_GPIO 0x18 /* GPIO on Audigy card (16bits) */ |
6fb861bb OB |
278 | #define A_GPINPUT_MASK 0xff00 /* Alice/2 has 8 input pins */ |
279 | #define A3_GPINPUT_MASK 0x3f00 /* ... while Tina/2 has only 6 */ | |
1da177e4 LT |
280 | #define A_GPOUTPUT_MASK 0x00ff |
281 | ||
a1c87c0b OB |
282 | // The GPIO port is used for I/O config on Sound Blasters; |
283 | // card-specific info can be found in the emu_chip_details table. | |
284 | // On E-MU cards the port is used as the interface to the FPGA. | |
285 | ||
1da177e4 | 286 | // Audigy output/GPIO stuff taken from the kX drivers |
a1c87c0b | 287 | #define A_IOCFG A_GPIO |
1da177e4 LT |
288 | #define A_IOCFG_GPOUT0 0x0044 /* analog/digital */ |
289 | #define A_IOCFG_DISABLE_ANALOG 0x0040 /* = 'enable' for Audigy2 (chiprev=4) */ | |
290 | #define A_IOCFG_ENABLE_DIGITAL 0x0004 | |
21fdddea | 291 | #define A_IOCFG_ENABLE_DIGITAL_AUDIGY4 0x0080 |
1da177e4 LT |
292 | #define A_IOCFG_UNKNOWN_20 0x0020 |
293 | #define A_IOCFG_DISABLE_AC97_FRONT 0x0080 /* turn off ac97 front -> front (10k2.1) */ | |
294 | #define A_IOCFG_GPOUT1 0x0002 /* IR? drive's internal bypass (?) */ | |
295 | #define A_IOCFG_GPOUT2 0x0001 /* IR */ | |
296 | #define A_IOCFG_MULTIPURPOSE_JACK 0x2000 /* center+lfe+rear_center (a2/a2ex) */ | |
297 | /* + digital for generic 10k2 */ | |
298 | #define A_IOCFG_DIGITAL_JACK 0x1000 /* digital for a2 platinum */ | |
299 | #define A_IOCFG_FRONT_JACK 0x4000 | |
300 | #define A_IOCFG_REAR_JACK 0x8000 | |
301 | #define A_IOCFG_PHONES_JACK 0x0100 /* LiveDrive */ | |
302 | ||
1da177e4 LT |
303 | #define TIMER 0x1a /* Timer terminal count register */ |
304 | /* NOTE: After the rate is changed, a maximum */ | |
305 | /* of 1024 sample periods should be allowed */ | |
306 | /* before the new rate is guaranteed accurate. */ | |
145ec1fd | 307 | #define TIMER_RATE_MASK 0x03ff /* Timer interrupt rate in sample periods */ |
1da177e4 | 308 | /* 0 == 1024 periods, [1..4] are not useful */ |
1da177e4 LT |
309 | |
310 | #define AC97DATA 0x1c /* AC97 register set data register (16 bit) */ | |
311 | ||
312 | #define AC97ADDRESS 0x1e /* AC97 register set address register (8 bit) */ | |
313 | #define AC97ADDRESS_READY 0x80 /* Read-only bit, reflects CODEC READY signal */ | |
314 | #define AC97ADDRESS_ADDRESS 0x7f /* Address of indexed AC97 register */ | |
315 | ||
316 | /* Available on the Audigy 2 and Audigy 4 only. This is the P16V chip. */ | |
317 | #define PTR2 0x20 /* Indexed register set pointer register */ | |
318 | #define DATA2 0x24 /* Indexed register set data register */ | |
319 | #define IPR2 0x28 /* P16V interrupt pending register */ | |
320 | #define IPR2_PLAYBACK_CH_0_LOOP 0x00001000 /* Playback Channel 0 loop */ | |
321 | #define IPR2_PLAYBACK_CH_0_HALF_LOOP 0x00000100 /* Playback Channel 0 half loop */ | |
322 | #define IPR2_CAPTURE_CH_0_LOOP 0x00100000 /* Capture Channel 0 loop */ | |
323 | #define IPR2_CAPTURE_CH_0_HALF_LOOP 0x00010000 /* Capture Channel 0 half loop */ | |
324 | /* 0x00000100 Playback. Only in once per period. | |
325 | * 0x00110000 Capture. Int on half buffer. | |
326 | */ | |
327 | #define INTE2 0x2c /* P16V Interrupt enable register. */ | |
328 | #define INTE2_PLAYBACK_CH_0_LOOP 0x00001000 /* Playback Channel 0 loop */ | |
329 | #define INTE2_PLAYBACK_CH_0_HALF_LOOP 0x00000100 /* Playback Channel 0 half loop */ | |
330 | #define INTE2_PLAYBACK_CH_1_LOOP 0x00002000 /* Playback Channel 1 loop */ | |
331 | #define INTE2_PLAYBACK_CH_1_HALF_LOOP 0x00000200 /* Playback Channel 1 half loop */ | |
332 | #define INTE2_PLAYBACK_CH_2_LOOP 0x00004000 /* Playback Channel 2 loop */ | |
333 | #define INTE2_PLAYBACK_CH_2_HALF_LOOP 0x00000400 /* Playback Channel 2 half loop */ | |
334 | #define INTE2_PLAYBACK_CH_3_LOOP 0x00008000 /* Playback Channel 3 loop */ | |
335 | #define INTE2_PLAYBACK_CH_3_HALF_LOOP 0x00000800 /* Playback Channel 3 half loop */ | |
336 | #define INTE2_CAPTURE_CH_0_LOOP 0x00100000 /* Capture Channel 0 loop */ | |
337 | #define INTE2_CAPTURE_CH_0_HALF_LOOP 0x00010000 /* Caputre Channel 0 half loop */ | |
338 | #define HCFG2 0x34 /* Defaults: 0, win2000 sets it to 00004201 */ | |
339 | /* 0x00000000 2-channel output. */ | |
340 | /* 0x00000200 8-channel output. */ | |
341 | /* 0x00000004 pauses stream/irq fail. */ | |
a869057c | 342 | /* Rest of bits do nothing to sound output */ |
1da177e4 LT |
343 | /* bit 0: Enable P16V audio. |
344 | * bit 1: Lock P16V record memory cache. | |
345 | * bit 2: Lock P16V playback memory cache. | |
346 | * bit 3: Dummy record insert zero samples. | |
347 | * bit 8: Record 8-channel in phase. | |
348 | * bit 9: Playback 8-channel in phase. | |
349 | * bit 11-12: Playback mixer attenuation: 0=0dB, 1=-6dB, 2=-12dB, 3=Mute. | |
350 | * bit 13: Playback mixer enable. | |
351 | * bit 14: Route SRC48 mixer output to fx engine. | |
352 | * bit 15: Enable IEEE 1394 chip. | |
353 | */ | |
354 | #define IPR3 0x38 /* Cdif interrupt pending register */ | |
355 | #define INTE3 0x3c /* Cdif interrupt enable register. */ | |
a869057c | 356 | |
1da177e4 LT |
357 | /************************************************************************************************/ |
358 | /* PCI function 1 registers, address = <val> + PCIBASE1 */ | |
359 | /************************************************************************************************/ | |
360 | ||
361 | #define JOYSTICK1 0x00 /* Analog joystick port register */ | |
362 | #define JOYSTICK2 0x01 /* Analog joystick port register */ | |
363 | #define JOYSTICK3 0x02 /* Analog joystick port register */ | |
364 | #define JOYSTICK4 0x03 /* Analog joystick port register */ | |
365 | #define JOYSTICK5 0x04 /* Analog joystick port register */ | |
366 | #define JOYSTICK6 0x05 /* Analog joystick port register */ | |
367 | #define JOYSTICK7 0x06 /* Analog joystick port register */ | |
368 | #define JOYSTICK8 0x07 /* Analog joystick port register */ | |
369 | ||
370 | /* When writing, any write causes JOYSTICK_COMPARATOR output enable to be pulsed on write. */ | |
371 | /* When reading, use these bitfields: */ | |
372 | #define JOYSTICK_BUTTONS 0x0f /* Joystick button data */ | |
373 | #define JOYSTICK_COMPARATOR 0xf0 /* Joystick comparator data */ | |
374 | ||
1da177e4 LT |
375 | /********************************************************************************************************/ |
376 | /* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers */ | |
377 | /********************************************************************************************************/ | |
378 | ||
a869057c OB |
379 | // No official documentation was released for EMU10K1, but some info |
380 | // about playback can be extrapolated from the EMU8K documents: | |
381 | // "AWE32/EMU8000 Programmer’s Guide" (emu8kpgm.pdf) - registers | |
382 | // "AWE32 Developer's Information Pack" (adip301.pdf) - high-level view | |
383 | ||
384 | // The short version: | |
385 | // - The engine has 64 playback channels, also called voices. The channels | |
386 | // operate independently, except when paired for stereo (see below). | |
387 | // - PCM samples are fetched into the cache; see description of CD0 below. | |
388 | // - Samples are consumed at the rate CPF_CURRENTPITCH. | |
389 | // - 8-bit samples are transformed upon use: cooked = (raw ^ 0x80) << 8 | |
390 | // - 8 samples are read at CCR_READADDRESS:CPF_FRACADDRESS and interpolated | |
391 | // according to CCCA_INTERPROM_*. With CCCA_INTERPROM_0 selected and a zero | |
392 | // CPF_FRACADDRESS, this results in CCR_READADDRESS[3] being used verbatim. | |
393 | // - The value is multiplied by CVCF_CURRENTVOL. | |
394 | // - The value goes through a filter with cutoff CVCF_CURRENTFILTER; | |
395 | // delay stages Z1 and Z2. | |
396 | // - The value is added by so-called `sends` to 4 (EMU10K1) / 8 (EMU10K2) | |
397 | // of the 16 (EMU10K1) / 64 (EMU10K2) FX bus accumulators via FXRT*, | |
398 | // multiplied by a per-send amount (*_FXSENDAMOUNT_*). | |
399 | // The scaling of the send amounts is exponential-ish. | |
400 | // - The DSP has a go at FXBUS* and outputs the values to EXTOUT* or EMU32OUT*. | |
401 | // - The pitch, volume, and filter cutoff can be modulated by two envelope | |
402 | // engines and two low frequency oscillators. | |
403 | // - To avoid abrupt changes to the parameters (which may cause audible | |
404 | // distortion), the modulation engine sets the target registers, towards | |
405 | // which the current registers "swerve" gradually. | |
406 | ||
77e067d0 OB |
407 | // For the odd channel in a stereo pair, these registers are meaningless: |
408 | // CPF_STEREO, CPF_CURRENTPITCH, PTRX_PITCHTARGET, CCR_CACHEINVALIDSIZE, | |
409 | // PSST_LOOPSTARTADDR, DSL_LOOPENDADDR, CCCA_CURRADDR | |
410 | // The somewhat non-obviously still meaningful ones are: | |
411 | // CPF_STOP, CPF_FRACADDRESS, CCR_READADDRESS (!), | |
412 | // CCCA_INTERPROM, CCCA_8BITSELECT (!) | |
413 | // (The envelope engine is ignored here, as stereo matters only for verbatim playback.) | |
414 | ||
1da177e4 | 415 | #define CPF 0x00 /* Current pitch and fraction register */ |
60571ac9 | 416 | SUB_REG(CPF, CURRENTPITCH, 0xffff0000) /* Current pitch (linear, 0x4000 == unity pitch shift) */ |
1da177e4 LT |
417 | #define CPF_STEREO_MASK 0x00008000 /* 1 = Even channel interleave, odd channel locked */ |
418 | #define CPF_STOP_MASK 0x00004000 /* 1 = Current pitch forced to 0 */ | |
419 | #define CPF_FRACADDRESS_MASK 0x00003fff /* Linear fractional address of the current channel */ | |
420 | ||
421 | #define PTRX 0x01 /* Pitch target and send A/B amounts register */ | |
60571ac9 OB |
422 | SUB_REG(PTRX, PITCHTARGET, 0xffff0000) /* Pitch target of specified channel */ |
423 | SUB_REG(PTRX, FXSENDAMOUNT_A, 0x0000ff00) /* Linear level of channel output sent to FX send bus A */ | |
424 | SUB_REG(PTRX, FXSENDAMOUNT_B, 0x000000ff) /* Linear level of channel output sent to FX send bus B */ | |
1da177e4 | 425 | |
bcdbd3b7 | 426 | // Note: the volumes are raw multpliers, so real 100% is impossible. |
1da177e4 | 427 | #define CVCF 0x02 /* Current volume and filter cutoff register */ |
60571ac9 OB |
428 | SUB_REG(CVCF, CURRENTVOL, 0xffff0000) /* Current linear volume of specified channel */ |
429 | SUB_REG(CVCF, CURRENTFILTER, 0x0000ffff) /* Current filter cutoff frequency of specified channel */ | |
1da177e4 LT |
430 | |
431 | #define VTFT 0x03 /* Volume target and filter cutoff target register */ | |
60571ac9 OB |
432 | SUB_REG(VTFT, VOLUMETARGET, 0xffff0000) /* Volume target of specified channel */ |
433 | SUB_REG(VTFT, FILTERTARGET, 0x0000ffff) /* Filter cutoff target of specified channel */ | |
1da177e4 LT |
434 | |
435 | #define Z1 0x05 /* Filter delay memory 1 register */ | |
436 | ||
437 | #define Z2 0x04 /* Filter delay memory 2 register */ | |
438 | ||
439 | #define PSST 0x06 /* Send C amount and loop start address register */ | |
60571ac9 OB |
440 | SUB_REG(PSST, FXSENDAMOUNT_C, 0xff000000) /* Linear level of channel output sent to FX send bus C */ |
441 | SUB_REG(PSST, LOOPSTARTADDR, 0x00ffffff) /* Loop start address of the specified channel */ | |
1da177e4 | 442 | |
a869057c | 443 | #define DSL 0x07 /* Send D amount and loop end address register */ |
60571ac9 OB |
444 | SUB_REG(DSL, FXSENDAMOUNT_D, 0xff000000) /* Linear level of channel output sent to FX send bus D */ |
445 | SUB_REG(DSL, LOOPENDADDR, 0x00ffffff) /* Loop end address of the specified channel */ | |
1da177e4 LT |
446 | |
447 | #define CCCA 0x08 /* Filter Q, interp. ROM, byte size, cur. addr register */ | |
60571ac9 | 448 | SUB_REG(CCCA, RESONANCE, 0xf0000000) /* Lowpass filter resonance (Q) height */ |
145ec1fd | 449 | #define CCCA_INTERPROM_MASK 0x0e000000 /* Selects passband of interpolation ROM */ |
1da177e4 LT |
450 | /* 1 == full band, 7 == lowpass */ |
451 | /* ROM 0 is used when pitch shifting downward or less */ | |
452 | /* then 3 semitones upward. Increasingly higher ROM */ | |
453 | /* numbers are used, typically in steps of 3 semitones, */ | |
454 | /* as upward pitch shifting is performed. */ | |
455 | #define CCCA_INTERPROM_0 0x00000000 /* Select interpolation ROM 0 */ | |
456 | #define CCCA_INTERPROM_1 0x02000000 /* Select interpolation ROM 1 */ | |
457 | #define CCCA_INTERPROM_2 0x04000000 /* Select interpolation ROM 2 */ | |
458 | #define CCCA_INTERPROM_3 0x06000000 /* Select interpolation ROM 3 */ | |
459 | #define CCCA_INTERPROM_4 0x08000000 /* Select interpolation ROM 4 */ | |
460 | #define CCCA_INTERPROM_5 0x0a000000 /* Select interpolation ROM 5 */ | |
461 | #define CCCA_INTERPROM_6 0x0c000000 /* Select interpolation ROM 6 */ | |
462 | #define CCCA_INTERPROM_7 0x0e000000 /* Select interpolation ROM 7 */ | |
463 | #define CCCA_8BITSELECT 0x01000000 /* 1 = Sound memory for this channel uses 8-bit samples */ | |
a869057c | 464 | /* 8-bit samples are unsigned, 16-bit ones signed */ |
60571ac9 | 465 | SUB_REG(CCCA, CURRADDR, 0x00ffffff) /* Current address of the selected channel */ |
1da177e4 LT |
466 | |
467 | #define CCR 0x09 /* Cache control register */ | |
60571ac9 | 468 | SUB_REG(CCR, CACHEINVALIDSIZE, 0xfe000000) /* Number of invalid samples before the read address */ |
1da177e4 LT |
469 | #define CCR_CACHELOOPFLAG 0x01000000 /* 1 = Cache has a loop service pending */ |
470 | #define CCR_INTERLEAVEDSAMPLES 0x00800000 /* 1 = A cache service will fetch interleaved samples */ | |
a869057c | 471 | /* Auto-set from CPF_STEREO_MASK */ |
1da177e4 | 472 | #define CCR_WORDSIZEDSAMPLES 0x00400000 /* 1 = A cache service will fetch word sized samples */ |
a869057c | 473 | /* Auto-set from CCCA_8BITSELECT */ |
60571ac9 OB |
474 | SUB_REG(CCR, READADDRESS, 0x003f0000) /* Next cached sample to play */ |
475 | SUB_REG(CCR, LOOPINVALSIZE, 0x0000fe00) /* Number of invalid samples in cache prior to loop */ | |
1da177e4 LT |
476 | /* NOTE: This is valid only if CACHELOOPFLAG is set */ |
477 | #define CCR_LOOPFLAG 0x00000100 /* Set for a single sample period when a loop occurs */ | |
60571ac9 | 478 | SUB_REG(CCR, CACHELOOPADDRHI, 0x000000ff) /* CLP_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set */ |
1da177e4 LT |
479 | |
480 | #define CLP 0x0a /* Cache loop register (valid if CCR_CACHELOOPFLAG = 1) */ | |
481 | /* NOTE: This register is normally not used */ | |
60571ac9 | 482 | SUB_REG(CLP, CACHELOOPADDR, 0x0000ffff) /* Cache loop address low word */ |
1da177e4 LT |
483 | |
484 | #define FXRT 0x0b /* Effects send routing register */ | |
485 | /* NOTE: It is illegal to assign the same routing to */ | |
486 | /* two effects sends. */ | |
487 | #define FXRT_CHANNELA 0x000f0000 /* Effects send bus number for channel's effects send A */ | |
488 | #define FXRT_CHANNELB 0x00f00000 /* Effects send bus number for channel's effects send B */ | |
489 | #define FXRT_CHANNELC 0x0f000000 /* Effects send bus number for channel's effects send C */ | |
490 | #define FXRT_CHANNELD 0xf0000000 /* Effects send bus number for channel's effects send D */ | |
491 | ||
492 | #define MAPA 0x0c /* Cache map A */ | |
1da177e4 LT |
493 | #define MAPB 0x0d /* Cache map B */ |
494 | ||
7241ea55 PZ |
495 | #define MAP_PTE_MASK0 0xfffff000 /* The 20 MSBs of the PTE indexed by the PTI */ |
496 | #define MAP_PTI_MASK0 0x00000fff /* The 12 bit index to one of the 4096 PTE dwords */ | |
497 | ||
498 | #define MAP_PTE_MASK1 0xffffe000 /* The 19 MSBs of the PTE indexed by the PTI */ | |
499 | #define MAP_PTI_MASK1 0x00001fff /* The 13 bit index to one of the 8192 PTE dwords */ | |
1da177e4 | 500 | |
a869057c | 501 | /* 0x0e, 0x0f: Internal state, at least on Audigy */ |
cbb7d8f9 | 502 | |
1da177e4 LT |
503 | #define ENVVOL 0x10 /* Volume envelope register */ |
504 | #define ENVVOL_MASK 0x0000ffff /* Current value of volume envelope state variable */ | |
505 | /* 0x8000-n == 666*n usec delay */ | |
506 | ||
507 | #define ATKHLDV 0x11 /* Volume envelope hold and attack register */ | |
145ec1fd | 508 | #define ATKHLDV_PHASE0_MASK 0x00008000 /* 0 = Begin attack phase */ |
1da177e4 LT |
509 | #define ATKHLDV_HOLDTIME_MASK 0x00007f00 /* Envelope hold time (127-n == n*88.2msec) */ |
510 | #define ATKHLDV_ATTACKTIME_MASK 0x0000007f /* Envelope attack time, log encoded */ | |
511 | /* 0 = infinite, 1 = 10.9msec, ... 0x7f = 5.5msec */ | |
512 | ||
513 | #define DCYSUSV 0x12 /* Volume envelope sustain and decay register */ | |
a869057c | 514 | #define DCYSUSV_PHASE1_MASK 0x00008000 /* 0 = Begin decay phase, 1 = begin release phase */ |
1da177e4 | 515 | #define DCYSUSV_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */ |
a869057c | 516 | #define DCYSUSV_CHANNELENABLE_MASK 0x00000080 /* 0 = Inhibit envelope engine from writing values in */ |
1da177e4 LT |
517 | /* this channel and from writing to pitch, filter and */ |
518 | /* volume targets. */ | |
519 | #define DCYSUSV_DECAYTIME_MASK 0x0000007f /* Volume envelope decay time, log encoded */ | |
520 | /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */ | |
521 | ||
522 | #define LFOVAL1 0x13 /* Modulation LFO value */ | |
523 | #define LFOVAL_MASK 0x0000ffff /* Current value of modulation LFO state variable */ | |
524 | /* 0x8000-n == 666*n usec delay */ | |
525 | ||
526 | #define ENVVAL 0x14 /* Modulation envelope register */ | |
527 | #define ENVVAL_MASK 0x0000ffff /* Current value of modulation envelope state variable */ | |
528 | /* 0x8000-n == 666*n usec delay */ | |
529 | ||
530 | #define ATKHLDM 0x15 /* Modulation envelope hold and attack register */ | |
145ec1fd | 531 | #define ATKHLDM_PHASE0_MASK 0x00008000 /* 0 = Begin attack phase */ |
1da177e4 LT |
532 | #define ATKHLDM_HOLDTIME 0x00007f00 /* Envelope hold time (127-n == n*42msec) */ |
533 | #define ATKHLDM_ATTACKTIME 0x0000007f /* Envelope attack time, log encoded */ | |
534 | /* 0 = infinite, 1 = 11msec, ... 0x7f = 5.5msec */ | |
535 | ||
536 | #define DCYSUSM 0x16 /* Modulation envelope decay and sustain register */ | |
a869057c | 537 | #define DCYSUSM_PHASE1_MASK 0x00008000 /* 0 = Begin decay phase, 1 = begin release phase */ |
1da177e4 LT |
538 | #define DCYSUSM_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */ |
539 | #define DCYSUSM_DECAYTIME_MASK 0x0000007f /* Envelope decay time, log encoded */ | |
540 | /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */ | |
541 | ||
542 | #define LFOVAL2 0x17 /* Vibrato LFO register */ | |
543 | #define LFOVAL2_MASK 0x0000ffff /* Current value of vibrato LFO state variable */ | |
544 | /* 0x8000-n == 666*n usec delay */ | |
545 | ||
546 | #define IP 0x18 /* Initial pitch register */ | |
547 | #define IP_MASK 0x0000ffff /* Exponential initial pitch shift */ | |
548 | /* 4 bits of octave, 12 bits of fractional octave */ | |
549 | #define IP_UNITY 0x0000e000 /* Unity pitch shift */ | |
550 | ||
551 | #define IFATN 0x19 /* Initial filter cutoff and attenuation register */ | |
60571ac9 | 552 | SUB_REG(IFATN, FILTERCUTOFF, 0x0000ff00) /* Initial filter cutoff frequency in exponential units */ |
1da177e4 LT |
553 | /* 6 most significant bits are semitones */ |
554 | /* 2 least significant bits are fractions */ | |
60571ac9 | 555 | SUB_REG(IFATN, ATTENUATION, 0x000000ff) /* Initial attenuation in 0.375dB steps */ |
1da177e4 | 556 | |
1da177e4 | 557 | #define PEFE 0x1a /* Pitch envelope and filter envelope amount register */ |
60571ac9 | 558 | SUB_REG(PEFE, PITCHAMOUNT, 0x0000ff00) /* Pitch envlope amount */ |
1da177e4 | 559 | /* Signed 2's complement, +/- one octave peak extremes */ |
60571ac9 | 560 | SUB_REG(PEFE, FILTERAMOUNT, 0x000000ff) /* Filter envlope amount */ |
1da177e4 | 561 | /* Signed 2's complement, +/- six octaves peak extremes */ |
60571ac9 | 562 | |
a869057c | 563 | |
1da177e4 LT |
564 | #define FMMOD 0x1b /* Vibrato/filter modulation from LFO register */ |
565 | #define FMMOD_MODVIBRATO 0x0000ff00 /* Vibrato LFO modulation depth */ | |
566 | /* Signed 2's complement, +/- one octave extremes */ | |
567 | #define FMMOD_MOFILTER 0x000000ff /* Filter LFO modulation depth */ | |
568 | /* Signed 2's complement, +/- three octave extremes */ | |
569 | ||
1da177e4 LT |
570 | #define TREMFRQ 0x1c /* Tremolo amount and modulation LFO frequency register */ |
571 | #define TREMFRQ_DEPTH 0x0000ff00 /* Tremolo depth */ | |
572 | /* Signed 2's complement, with +/- 12dB extremes */ | |
1da177e4 LT |
573 | #define TREMFRQ_FREQUENCY 0x000000ff /* Tremolo LFO frequency */ |
574 | /* ??Hz steps, maximum of ?? Hz. */ | |
a869057c | 575 | |
1da177e4 LT |
576 | #define FM2FRQ2 0x1d /* Vibrato amount and vibrato LFO frequency register */ |
577 | #define FM2FRQ2_DEPTH 0x0000ff00 /* Vibrato LFO vibrato depth */ | |
578 | /* Signed 2's complement, +/- one octave extremes */ | |
579 | #define FM2FRQ2_FREQUENCY 0x000000ff /* Vibrato LFO frequency */ | |
580 | /* 0.039Hz steps, maximum of 9.85 Hz. */ | |
581 | ||
582 | #define TEMPENV 0x1e /* Tempory envelope register */ | |
583 | #define TEMPENV_MASK 0x0000ffff /* 16-bit value */ | |
584 | /* NOTE: All channels contain internal variables; do */ | |
585 | /* not write to these locations. */ | |
586 | ||
cbb7d8f9 | 587 | /* 0x1f: not used */ |
1da177e4 LT |
588 | |
589 | #define CD0 0x20 /* Cache data 0 register */ | |
590 | #define CD1 0x21 /* Cache data 1 register */ | |
591 | #define CD2 0x22 /* Cache data 2 register */ | |
592 | #define CD3 0x23 /* Cache data 3 register */ | |
593 | #define CD4 0x24 /* Cache data 4 register */ | |
594 | #define CD5 0x25 /* Cache data 5 register */ | |
595 | #define CD6 0x26 /* Cache data 6 register */ | |
596 | #define CD7 0x27 /* Cache data 7 register */ | |
597 | #define CD8 0x28 /* Cache data 8 register */ | |
598 | #define CD9 0x29 /* Cache data 9 register */ | |
599 | #define CDA 0x2a /* Cache data A register */ | |
600 | #define CDB 0x2b /* Cache data B register */ | |
601 | #define CDC 0x2c /* Cache data C register */ | |
602 | #define CDD 0x2d /* Cache data D register */ | |
603 | #define CDE 0x2e /* Cache data E register */ | |
604 | #define CDF 0x2f /* Cache data F register */ | |
605 | ||
606 | /* 0x30-3f seem to be the same as 0x20-2f */ | |
607 | ||
608 | #define PTB 0x40 /* Page table base register */ | |
609 | #define PTB_MASK 0xfffff000 /* Physical address of the page table in host memory */ | |
610 | ||
611 | #define TCB 0x41 /* Tank cache base register */ | |
612 | #define TCB_MASK 0xfffff000 /* Physical address of the bottom of host based TRAM */ | |
613 | ||
614 | #define ADCCR 0x42 /* ADC sample rate/stereo control register */ | |
615 | #define ADCCR_RCHANENABLE 0x00000010 /* Enables right channel for writing to the host */ | |
616 | #define ADCCR_LCHANENABLE 0x00000008 /* Enables left channel for writing to the host */ | |
617 | /* NOTE: To guarantee phase coherency, both channels */ | |
618 | /* must be disabled prior to enabling both channels. */ | |
619 | #define A_ADCCR_RCHANENABLE 0x00000020 | |
620 | #define A_ADCCR_LCHANENABLE 0x00000010 | |
621 | ||
622 | #define A_ADCCR_SAMPLERATE_MASK 0x0000000F /* Audigy sample rate convertor output rate */ | |
623 | #define ADCCR_SAMPLERATE_MASK 0x00000007 /* Sample rate convertor output rate */ | |
624 | #define ADCCR_SAMPLERATE_48 0x00000000 /* 48kHz sample rate */ | |
625 | #define ADCCR_SAMPLERATE_44 0x00000001 /* 44.1kHz sample rate */ | |
626 | #define ADCCR_SAMPLERATE_32 0x00000002 /* 32kHz sample rate */ | |
627 | #define ADCCR_SAMPLERATE_24 0x00000003 /* 24kHz sample rate */ | |
628 | #define ADCCR_SAMPLERATE_22 0x00000004 /* 22.05kHz sample rate */ | |
629 | #define ADCCR_SAMPLERATE_16 0x00000005 /* 16kHz sample rate */ | |
630 | #define ADCCR_SAMPLERATE_11 0x00000006 /* 11.025kHz sample rate */ | |
631 | #define ADCCR_SAMPLERATE_8 0x00000007 /* 8kHz sample rate */ | |
632 | #define A_ADCCR_SAMPLERATE_12 0x00000006 /* 12kHz sample rate */ | |
633 | #define A_ADCCR_SAMPLERATE_11 0x00000007 /* 11.025kHz sample rate */ | |
634 | #define A_ADCCR_SAMPLERATE_8 0x00000008 /* 8kHz sample rate */ | |
635 | ||
636 | #define FXWC 0x43 /* FX output write channels register */ | |
637 | /* When set, each bit enables the writing of the */ | |
638 | /* corresponding FX output channel (internal registers */ | |
639 | /* 0x20-0x3f) to host memory. This mode of recording */ | |
640 | /* is 16bit, 48KHz only. All 32 channels can be enabled */ | |
641 | /* simultaneously. */ | |
642 | ||
5dc5ebb7 | 643 | #define A_TBLSZ 0x43 /* Effects Tank Internal Table Size. Only low byte or register used */ |
cbb7d8f9 | 644 | |
1da177e4 LT |
645 | #define TCBS 0x44 /* Tank cache buffer size register */ |
646 | #define TCBS_MASK 0x00000007 /* Tank cache buffer size field */ | |
647 | #define TCBS_BUFFSIZE_16K 0x00000000 | |
648 | #define TCBS_BUFFSIZE_32K 0x00000001 | |
649 | #define TCBS_BUFFSIZE_64K 0x00000002 | |
650 | #define TCBS_BUFFSIZE_128K 0x00000003 | |
651 | #define TCBS_BUFFSIZE_256K 0x00000004 | |
652 | #define TCBS_BUFFSIZE_512K 0x00000005 | |
653 | #define TCBS_BUFFSIZE_1024K 0x00000006 | |
654 | #define TCBS_BUFFSIZE_2048K 0x00000007 | |
655 | ||
656 | #define MICBA 0x45 /* AC97 microphone buffer address register */ | |
657 | #define MICBA_MASK 0xfffff000 /* 20 bit base address */ | |
658 | ||
659 | #define ADCBA 0x46 /* ADC buffer address register */ | |
660 | #define ADCBA_MASK 0xfffff000 /* 20 bit base address */ | |
661 | ||
662 | #define FXBA 0x47 /* FX Buffer Address */ | |
663 | #define FXBA_MASK 0xfffff000 /* 20 bit base address */ | |
664 | ||
a869057c | 665 | #define A_HWM 0x48 /* High PCI Water Mark - word access, defaults to 3f */ |
1da177e4 LT |
666 | |
667 | #define MICBS 0x49 /* Microphone buffer size register */ | |
668 | ||
669 | #define ADCBS 0x4a /* ADC buffer size register */ | |
670 | ||
671 | #define FXBS 0x4b /* FX buffer size register */ | |
672 | ||
a869057c | 673 | /* The following mask values define the size of the ADC, MIC and FX buffers in bytes */ |
1da177e4 LT |
674 | #define ADCBS_BUFSIZE_NONE 0x00000000 |
675 | #define ADCBS_BUFSIZE_384 0x00000001 | |
676 | #define ADCBS_BUFSIZE_448 0x00000002 | |
677 | #define ADCBS_BUFSIZE_512 0x00000003 | |
678 | #define ADCBS_BUFSIZE_640 0x00000004 | |
679 | #define ADCBS_BUFSIZE_768 0x00000005 | |
680 | #define ADCBS_BUFSIZE_896 0x00000006 | |
681 | #define ADCBS_BUFSIZE_1024 0x00000007 | |
682 | #define ADCBS_BUFSIZE_1280 0x00000008 | |
683 | #define ADCBS_BUFSIZE_1536 0x00000009 | |
684 | #define ADCBS_BUFSIZE_1792 0x0000000a | |
685 | #define ADCBS_BUFSIZE_2048 0x0000000b | |
686 | #define ADCBS_BUFSIZE_2560 0x0000000c | |
687 | #define ADCBS_BUFSIZE_3072 0x0000000d | |
688 | #define ADCBS_BUFSIZE_3584 0x0000000e | |
689 | #define ADCBS_BUFSIZE_4096 0x0000000f | |
690 | #define ADCBS_BUFSIZE_5120 0x00000010 | |
691 | #define ADCBS_BUFSIZE_6144 0x00000011 | |
692 | #define ADCBS_BUFSIZE_7168 0x00000012 | |
693 | #define ADCBS_BUFSIZE_8192 0x00000013 | |
694 | #define ADCBS_BUFSIZE_10240 0x00000014 | |
695 | #define ADCBS_BUFSIZE_12288 0x00000015 | |
696 | #define ADCBS_BUFSIZE_14366 0x00000016 | |
697 | #define ADCBS_BUFSIZE_16384 0x00000017 | |
698 | #define ADCBS_BUFSIZE_20480 0x00000018 | |
699 | #define ADCBS_BUFSIZE_24576 0x00000019 | |
700 | #define ADCBS_BUFSIZE_28672 0x0000001a | |
701 | #define ADCBS_BUFSIZE_32768 0x0000001b | |
702 | #define ADCBS_BUFSIZE_40960 0x0000001c | |
703 | #define ADCBS_BUFSIZE_49152 0x0000001d | |
704 | #define ADCBS_BUFSIZE_57344 0x0000001e | |
705 | #define ADCBS_BUFSIZE_65536 0x0000001f | |
706 | ||
a869057c OB |
707 | #define A_CSBA 0x4c /* FX send B & A current amounts */ |
708 | #define A_CSDC 0x4d /* FX send D & C current amounts */ | |
709 | #define A_CSFE 0x4e /* FX send F & E current amounts */ | |
710 | #define A_CSHG 0x4f /* FX send H & G current amounts */ | |
cbb7d8f9 | 711 | |
a869057c OB |
712 | // NOTE: 0x50,51,52: 64-bit (split over voices 0 & 1) |
713 | #define CDCS 0x50 /* CD-ROM digital channel status register */ | |
1da177e4 | 714 | |
a869057c | 715 | #define GPSCS 0x51 /* General Purpose SPDIF channel status register */ |
1da177e4 | 716 | |
2696d5a3 | 717 | // Corresponding EMU10K1_DBG_* constants are in the public header |
a869057c | 718 | #define DBG 0x52 |
1da177e4 | 719 | |
a869057c | 720 | #define A_SPSC 0x52 /* S/PDIF Input C Channel Status */ |
1da177e4 | 721 | |
a869057c | 722 | #define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */ |
1da177e4 | 723 | |
2696d5a3 OB |
724 | // Corresponding A_DBG_* constants are in the public header |
725 | #define A_DBG 0x53 | |
1da177e4 | 726 | |
a869057c | 727 | // NOTE: 0x54,55,56: 64-bit (split over voices 0 & 1) |
1da177e4 LT |
728 | #define SPCS0 0x54 /* SPDIF output Channel Status 0 register */ |
729 | ||
730 | #define SPCS1 0x55 /* SPDIF output Channel Status 1 register */ | |
731 | ||
732 | #define SPCS2 0x56 /* SPDIF output Channel Status 2 register */ | |
733 | ||
734 | #define SPCS_CLKACCYMASK 0x30000000 /* Clock accuracy */ | |
735 | #define SPCS_CLKACCY_1000PPM 0x00000000 /* 1000 parts per million */ | |
736 | #define SPCS_CLKACCY_50PPM 0x10000000 /* 50 parts per million */ | |
737 | #define SPCS_CLKACCY_VARIABLE 0x20000000 /* Variable accuracy */ | |
738 | #define SPCS_SAMPLERATEMASK 0x0f000000 /* Sample rate */ | |
739 | #define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */ | |
740 | #define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */ | |
741 | #define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */ | |
742 | #define SPCS_CHANNELNUMMASK 0x00f00000 /* Channel number */ | |
743 | #define SPCS_CHANNELNUM_UNSPEC 0x00000000 /* Unspecified channel number */ | |
744 | #define SPCS_CHANNELNUM_LEFT 0x00100000 /* Left channel */ | |
745 | #define SPCS_CHANNELNUM_RIGHT 0x00200000 /* Right channel */ | |
746 | #define SPCS_SOURCENUMMASK 0x000f0000 /* Source number */ | |
747 | #define SPCS_SOURCENUM_UNSPEC 0x00000000 /* Unspecified source number */ | |
748 | #define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */ | |
749 | #define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */ | |
750 | #define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */ | |
751 | #define SPCS_EMPHASISMASK 0x00000038 /* Emphasis */ | |
752 | #define SPCS_EMPHASIS_NONE 0x00000000 /* No emphasis */ | |
753 | #define SPCS_EMPHASIS_50_15 0x00000008 /* 50/15 usec 2 channel */ | |
754 | #define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */ | |
755 | #define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */ | |
756 | #define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */ | |
757 | ||
cbb7d8f9 JCD |
758 | /* 0x57: Not used */ |
759 | ||
a869057c | 760 | /* The 32-bit CLIx and SOLEx registers all have one bit per channel control/status */ |
1da177e4 | 761 | #define CLIEL 0x58 /* Channel loop interrupt enable low register */ |
1da177e4 LT |
762 | #define CLIEH 0x59 /* Channel loop interrupt enable high register */ |
763 | ||
764 | #define CLIPL 0x5a /* Channel loop interrupt pending low register */ | |
1da177e4 LT |
765 | #define CLIPH 0x5b /* Channel loop interrupt pending high register */ |
766 | ||
767 | #define SOLEL 0x5c /* Stop on loop enable low register */ | |
1da177e4 LT |
768 | #define SOLEH 0x5d /* Stop on loop enable high register */ |
769 | ||
770 | #define SPBYPASS 0x5e /* SPDIF BYPASS mode register */ | |
771 | #define SPBYPASS_SPDIF0_MASK 0x00000003 /* SPDIF 0 bypass mode */ | |
772 | #define SPBYPASS_SPDIF1_MASK 0x0000000c /* SPDIF 1 bypass mode */ | |
773 | /* bypass mode: 0 - DSP; 1 - SPDIF A, 2 - SPDIF B, 3 - SPDIF C */ | |
774 | #define SPBYPASS_FORMAT 0x00000f00 /* If 1, SPDIF XX uses 24 bit, if 0 - 20 bit */ | |
775 | ||
776 | #define AC97SLOT 0x5f /* additional AC97 slots enable bits */ | |
a869057c OB |
777 | #define AC97SLOT_REAR_RIGHT 0x01 /* Rear left */ |
778 | #define AC97SLOT_REAR_LEFT 0x02 /* Rear right */ | |
779 | #define AC97SLOT_CNTR 0x10 /* Center enable */ | |
780 | #define AC97SLOT_LFE 0x20 /* LFE enable */ | |
1da177e4 | 781 | |
a869057c | 782 | #define A_PCB 0x5f /* PCB Revision */ |
cbb7d8f9 | 783 | |
1da177e4 LT |
784 | // NOTE: 0x60,61,62: 64-bit |
785 | #define CDSRCS 0x60 /* CD-ROM Sample Rate Converter status register */ | |
786 | ||
787 | #define GPSRCS 0x61 /* General Purpose SPDIF sample rate cvt status */ | |
788 | ||
789 | #define ZVSRCS 0x62 /* ZVideo sample rate converter status */ | |
790 | /* NOTE: This one has no SPDIFLOCKED field */ | |
791 | /* Assumes sample lock */ | |
792 | ||
793 | /* These three bitfields apply to CDSRCS, GPSRCS, and (except as noted) ZVSRCS. */ | |
001f7589 | 794 | #define SRCS_SPDIFVALID 0x04000000 /* SPDIF stream valid */ |
1da177e4 LT |
795 | #define SRCS_SPDIFLOCKED 0x02000000 /* SPDIF stream locked */ |
796 | #define SRCS_RATELOCKED 0x01000000 /* Sample rate locked */ | |
797 | #define SRCS_ESTSAMPLERATE 0x0007ffff /* Do not modify this field. */ | |
798 | ||
799 | /* Note that these values can vary +/- by a small amount */ | |
800 | #define SRCS_SPDIFRATE_44 0x0003acd9 | |
801 | #define SRCS_SPDIFRATE_48 0x00040000 | |
802 | #define SRCS_SPDIFRATE_96 0x00080000 | |
803 | ||
804 | #define MICIDX 0x63 /* Microphone recording buffer index register */ | |
60571ac9 | 805 | SUB_REG(MICIDX, IDX, 0x0000ffff) |
1da177e4 LT |
806 | |
807 | #define ADCIDX 0x64 /* ADC recording buffer index register */ | |
60571ac9 | 808 | SUB_REG(ADCIDX, IDX, 0x0000ffff) |
1da177e4 LT |
809 | |
810 | #define A_ADCIDX 0x63 | |
60571ac9 | 811 | SUB_REG(A_ADCIDX, IDX, 0x0000ffff) |
1da177e4 LT |
812 | |
813 | #define A_MICIDX 0x64 | |
60571ac9 | 814 | SUB_REG(A_MICIDX, IDX, 0x0000ffff) |
1da177e4 LT |
815 | |
816 | #define FXIDX 0x65 /* FX recording buffer index register */ | |
60571ac9 | 817 | SUB_REG(FXIDX, IDX, 0x0000ffff) |
1da177e4 | 818 | |
a869057c | 819 | /* The 32-bit HLIEx and HLIPx registers all have one bit per channel control/status */ |
1da177e4 | 820 | #define HLIEL 0x66 /* Channel half loop interrupt enable low register */ |
1da177e4 LT |
821 | #define HLIEH 0x67 /* Channel half loop interrupt enable high register */ |
822 | ||
823 | #define HLIPL 0x68 /* Channel half loop interrupt pending low register */ | |
1da177e4 LT |
824 | #define HLIPH 0x69 /* Channel half loop interrupt pending high register */ |
825 | ||
a869057c OB |
826 | #define A_SPRI 0x6a /* S/PDIF Host Record Index (bypasses SRC) */ |
827 | #define A_SPRA 0x6b /* S/PDIF Host Record Address */ | |
828 | #define A_SPRC 0x6c /* S/PDIF Host Record Control */ | |
829 | ||
830 | #define A_DICE 0x6d /* Delayed Interrupt Counter & Enable */ | |
831 | ||
832 | #define A_TTB 0x6e /* Tank Table Base */ | |
833 | #define A_TDOF 0x6f /* Tank Delay Offset */ | |
1da177e4 LT |
834 | |
835 | /* This is the MPU port on the card (via the game port) */ | |
836 | #define A_MUDATA1 0x70 | |
837 | #define A_MUCMD1 0x71 | |
838 | #define A_MUSTAT1 A_MUCMD1 | |
839 | ||
840 | /* This is the MPU port on the Audigy Drive */ | |
841 | #define A_MUDATA2 0x72 | |
842 | #define A_MUCMD2 0x73 | |
843 | #define A_MUSTAT2 A_MUCMD2 | |
844 | ||
845 | /* The next two are the Audigy equivalent of FXWC */ | |
a869057c | 846 | /* the Audigy can record any output (16bit, 48kHz, up to 64 channels simultaneously) */ |
1da177e4 LT |
847 | /* Each bit selects a channel for recording */ |
848 | #define A_FXWC1 0x74 /* Selects 0x7f-0x60 for FX recording */ | |
849 | #define A_FXWC2 0x75 /* Selects 0x9f-0x80 for FX recording */ | |
850 | ||
145ec1fd OB |
851 | #define A_EHC 0x76 /* Extended Hardware Control */ |
852 | ||
853 | #define A_SPDIF_SAMPLERATE A_EHC /* Set the sample rate of SPDIF output */ | |
14c7e472 | 854 | #define A_SPDIF_RATE_MASK 0x000000e0 /* Any other values for rates, just use 48000 */ |
145ec1fd | 855 | #define A_SPDIF_48000 0x00000000 /* kX calls this BYPASS */ |
14c7e472 | 856 | #define A_SPDIF_192000 0x00000020 |
1da177e4 | 857 | #define A_SPDIF_96000 0x00000040 |
14c7e472 | 858 | #define A_SPDIF_44100 0x00000080 |
145ec1fd | 859 | #define A_SPDIF_MUTED 0x000000c0 |
14c7e472 | 860 | |
60571ac9 OB |
861 | SUB_REG_NC(A_EHC, A_I2S_CAPTURE_RATE, 0x00000e00) /* This sets the capture PCM rate, but it is */ |
862 | /* unclear if this sets the ADC rate as well. */ | |
8d60d5ca OB |
863 | #define A_I2S_CAPTURE_48000 0x0 |
864 | #define A_I2S_CAPTURE_192000 0x1 | |
865 | #define A_I2S_CAPTURE_96000 0x2 | |
866 | #define A_I2S_CAPTURE_44100 0x4 | |
14c7e472 | 867 | |
145ec1fd OB |
868 | #define A_EHC_SRC48_MASK 0x0000e000 /* This sets the playback PCM rate on the P16V */ |
869 | #define A_EHC_SRC48_BYPASS 0x00000000 | |
870 | #define A_EHC_SRC48_192 0x00002000 | |
871 | #define A_EHC_SRC48_96 0x00004000 | |
872 | #define A_EHC_SRC48_44 0x00008000 | |
873 | #define A_EHC_SRC48_MUTED 0x0000c000 | |
874 | ||
875 | #define A_EHC_P17V_TVM 0x00000001 /* Tank virtual memory mode */ | |
876 | #define A_EHC_P17V_SEL0_MASK 0x00030000 /* Aka A_EHC_P16V_PB_RATE; 00: 48, 01: 44.1, 10: 96, 11: 192 */ | |
877 | #define A_EHC_P17V_SEL1_MASK 0x000c0000 | |
878 | #define A_EHC_P17V_SEL2_MASK 0x00300000 | |
879 | #define A_EHC_P17V_SEL3_MASK 0x00c00000 | |
880 | ||
881 | #define A_EHC_ASYNC_BYPASS 0x80000000 | |
1da177e4 | 882 | |
a869057c OB |
883 | #define A_SRT3 0x77 /* I2S0 Sample Rate Tracker Status */ |
884 | #define A_SRT4 0x78 /* I2S1 Sample Rate Tracker Status */ | |
885 | #define A_SRT5 0x79 /* I2S2 Sample Rate Tracker Status */ | |
cbb7d8f9 JCD |
886 | /* - default to 0x01080000 on my audigy 2 ZS --rlrevell */ |
887 | ||
145ec1fd OB |
888 | #define A_SRT_ESTSAMPLERATE 0x001fffff |
889 | #define A_SRT_RATELOCKED 0x01000000 | |
890 | ||
a869057c OB |
891 | #define A_TTDA 0x7a /* Tank Table DMA Address */ |
892 | #define A_TTDD 0x7b /* Tank Table DMA Data */ | |
1da177e4 LT |
893 | |
894 | #define A_FXRT2 0x7c | |
895 | #define A_FXRT_CHANNELE 0x0000003f /* Effects send bus number for channel's effects send E */ | |
896 | #define A_FXRT_CHANNELF 0x00003f00 /* Effects send bus number for channel's effects send F */ | |
897 | #define A_FXRT_CHANNELG 0x003f0000 /* Effects send bus number for channel's effects send G */ | |
898 | #define A_FXRT_CHANNELH 0x3f000000 /* Effects send bus number for channel's effects send H */ | |
899 | ||
900 | #define A_SENDAMOUNTS 0x7d | |
901 | #define A_FXSENDAMOUNT_E_MASK 0xFF000000 | |
902 | #define A_FXSENDAMOUNT_F_MASK 0x00FF0000 | |
903 | #define A_FXSENDAMOUNT_G_MASK 0x0000FF00 | |
904 | #define A_FXSENDAMOUNT_H_MASK 0x000000FF | |
a869057c | 905 | |
1da177e4 LT |
906 | /* 0x7c, 0x7e "high bit is used for filtering" */ |
907 | ||
908 | /* The send amounts for this one are the same as used with the emu10k1 */ | |
909 | #define A_FXRT1 0x7e | |
910 | #define A_FXRT_CHANNELA 0x0000003f | |
911 | #define A_FXRT_CHANNELB 0x00003f00 | |
912 | #define A_FXRT_CHANNELC 0x003f0000 | |
913 | #define A_FXRT_CHANNELD 0x3f000000 | |
914 | ||
cbb7d8f9 | 915 | /* 0x7f: Not used */ |
1da177e4 | 916 | |
2696d5a3 OB |
917 | /* The public header defines the GPR and TRAM base addresses that |
918 | * are valid for _both_ CPU and DSP addressing. */ | |
1da177e4 LT |
919 | |
920 | /* Each DSP microcode instruction is mapped into 2 doublewords */ | |
921 | /* NOTE: When writing, always write the LO doubleword first. Reads can be in either order. */ | |
2696d5a3 | 922 | #define MICROCODEBASE 0x400 /* Microcode data base address */ |
1da177e4 | 923 | #define A_MICROCODEBASE 0x600 |
1da177e4 | 924 | |
a869057c OB |
925 | |
926 | /************************************************************************************************/ | |
927 | /* E-MU Digital Audio System overview */ | |
9f4bd5dd | 928 | /************************************************************************************************/ |
a869057c OB |
929 | |
930 | // - These cards use a regular PCI-attached Audigy chip (Alice2/Tina/Tina2); | |
931 | // the PCIe variants simply put the Audigy chip behind a PCI bridge. | |
932 | // - All physical PCM I/O is routed through an additional FPGA; the regular | |
933 | // EXTIN/EXTOUT ports are unconnected. | |
934 | // - The FPGA has a signal routing matrix, to connect each destination (output | |
935 | // socket or capture channel) to a source (input socket or playback channel). | |
936 | // - The FPGA is controlled via Audigy's GPIO port, while sample data is | |
937 | // transmitted via proprietary EMU32 serial links. On first-generation | |
938 | // E-MU 1010 cards, Audigy's I2S inputs are also used for sample data. | |
939 | // - The Audio/Micro Dock is attached to Hana via EDI, a "network" link. | |
940 | // - The Audigy chip operates in slave mode; the clock is supplied by the FPGA. | |
941 | // Gen1 E-MU 1010 cards have two crystals (for 44.1 kHz and 48 kHz multiples), | |
942 | // while the later cards use a single crystal and a PLL chip. | |
943 | // - The whole card is switched to 2x/4x mode to achieve 88.2/96/176.4/192 kHz | |
944 | // sample rates. Alice2/Tina keeps running at 44.1/48 kHz, but multiple channels | |
945 | // are bundled. | |
946 | // - The number of available EMU32/EDI channels is hit in 2x/4x mode, so the total | |
947 | // number of usable inputs/outputs is limited, esp. with ADAT in use. | |
948 | // - S/PDIF is unavailable in 4x mode (only over TOSLINK on newer 1010 cards) due | |
949 | // to being unspecified at 176.4/192 kHz. Therefore, the Dock's S/PDIF channels | |
950 | // can overlap with the Dock's ADC/DAC's high channels. | |
951 | // - The code names are mentioned below and in the emu_chip_details table. | |
952 | ||
9f4bd5dd | 953 | /************************************************************************************************/ |
a869057c OB |
954 | /* EMU1010 FPGA registers */ |
955 | /************************************************************************************************/ | |
956 | ||
9f4bd5dd JCD |
957 | #define EMU_HANA_DESTHI 0x00 /* 0000xxx 3 bits Link Destination */ |
958 | #define EMU_HANA_DESTLO 0x01 /* 00xxxxx 5 bits */ | |
a869057c | 959 | |
9f4bd5dd JCD |
960 | #define EMU_HANA_SRCHI 0x02 /* 0000xxx 3 bits Link Source */ |
961 | #define EMU_HANA_SRCLO 0x03 /* 00xxxxx 5 bits */ | |
a869057c | 962 | |
9f4bd5dd JCD |
963 | #define EMU_HANA_DOCK_PWR 0x04 /* 000000x 1 bits Audio Dock power */ |
964 | #define EMU_HANA_DOCK_PWR_ON 0x01 /* Audio Dock power on */ | |
a869057c | 965 | |
9f4bd5dd JCD |
966 | #define EMU_HANA_WCLOCK 0x05 /* 0000xxx 3 bits Word Clock source select */ |
967 | /* Must be written after power on to reset DLL */ | |
968 | /* One is unable to detect the Audio dock without this */ | |
969 | #define EMU_HANA_WCLOCK_SRC_MASK 0x07 | |
970 | #define EMU_HANA_WCLOCK_INT_48K 0x00 | |
971 | #define EMU_HANA_WCLOCK_INT_44_1K 0x01 | |
972 | #define EMU_HANA_WCLOCK_HANA_SPDIF_IN 0x02 | |
973 | #define EMU_HANA_WCLOCK_HANA_ADAT_IN 0x03 | |
145ec1fd | 974 | #define EMU_HANA_WCLOCK_SYNC_BNC 0x04 |
9f4bd5dd JCD |
975 | #define EMU_HANA_WCLOCK_2ND_HANA 0x05 |
976 | #define EMU_HANA_WCLOCK_SRC_RESERVED 0x06 | |
977 | #define EMU_HANA_WCLOCK_OFF 0x07 /* For testing, forces fallback to DEFCLOCK */ | |
978 | #define EMU_HANA_WCLOCK_MULT_MASK 0x18 | |
979 | #define EMU_HANA_WCLOCK_1X 0x00 | |
980 | #define EMU_HANA_WCLOCK_2X 0x08 | |
981 | #define EMU_HANA_WCLOCK_4X 0x10 | |
982 | #define EMU_HANA_WCLOCK_MULT_RESERVED 0x18 | |
983 | ||
984 | #define EMU_HANA_DEFCLOCK 0x06 /* 000000x 1 bits Default Word Clock */ | |
985 | #define EMU_HANA_DEFCLOCK_48K 0x00 | |
986 | #define EMU_HANA_DEFCLOCK_44_1K 0x01 | |
987 | ||
988 | #define EMU_HANA_UNMUTE 0x07 /* 000000x 1 bits Mute all audio outputs */ | |
989 | #define EMU_MUTE 0x00 | |
990 | #define EMU_UNMUTE 0x01 | |
991 | ||
992 | #define EMU_HANA_FPGA_CONFIG 0x08 /* 00000xx 2 bits Config control of FPGAs */ | |
993 | #define EMU_HANA_FPGA_CONFIG_AUDIODOCK 0x01 /* Set in order to program FPGA on Audio Dock */ | |
994 | #define EMU_HANA_FPGA_CONFIG_HANA 0x02 /* Set in order to program FPGA on Hana */ | |
995 | ||
996 | #define EMU_HANA_IRQ_ENABLE 0x09 /* 000xxxx 4 bits IRQ Enable */ | |
997 | #define EMU_HANA_IRQ_WCLK_CHANGED 0x01 | |
998 | #define EMU_HANA_IRQ_ADAT 0x02 | |
999 | #define EMU_HANA_IRQ_DOCK 0x04 | |
1000 | #define EMU_HANA_IRQ_DOCK_LOST 0x08 | |
1001 | ||
1002 | #define EMU_HANA_SPDIF_MODE 0x0a /* 00xxxxx 5 bits SPDIF MODE */ | |
145ec1fd | 1003 | #define EMU_HANA_SPDIF_MODE_TX_CONSUMER 0x00 |
9f4bd5dd JCD |
1004 | #define EMU_HANA_SPDIF_MODE_TX_PRO 0x01 |
1005 | #define EMU_HANA_SPDIF_MODE_TX_NOCOPY 0x02 | |
145ec1fd | 1006 | #define EMU_HANA_SPDIF_MODE_RX_CONSUMER 0x00 |
9f4bd5dd JCD |
1007 | #define EMU_HANA_SPDIF_MODE_RX_PRO 0x04 |
1008 | #define EMU_HANA_SPDIF_MODE_RX_NOCOPY 0x08 | |
1009 | #define EMU_HANA_SPDIF_MODE_RX_INVALID 0x10 | |
1010 | ||
1011 | #define EMU_HANA_OPTICAL_TYPE 0x0b /* 00000xx 2 bits ADAT or SPDIF in/out */ | |
1012 | #define EMU_HANA_OPTICAL_IN_SPDIF 0x00 | |
1013 | #define EMU_HANA_OPTICAL_IN_ADAT 0x01 | |
1014 | #define EMU_HANA_OPTICAL_OUT_SPDIF 0x00 | |
1015 | #define EMU_HANA_OPTICAL_OUT_ADAT 0x02 | |
1016 | ||
9148cc50 | 1017 | #define EMU_HANA_MIDI_IN 0x0c /* 000000x 1 bit Control MIDI */ |
145ec1fd OB |
1018 | #define EMU_HANA_MIDI_INA_FROM_HAMOA 0x01 /* HAMOA MIDI in to Alice 2 MIDI A */ |
1019 | #define EMU_HANA_MIDI_INA_FROM_DOCK1 0x02 /* Audio Dock-1 MIDI in to Alice 2 MIDI A */ | |
1020 | #define EMU_HANA_MIDI_INA_FROM_DOCK2 0x03 /* Audio Dock-2 MIDI in to Alice 2 MIDI A */ | |
1021 | #define EMU_HANA_MIDI_INB_FROM_HAMOA 0x08 /* HAMOA MIDI in to Alice 2 MIDI B */ | |
1022 | #define EMU_HANA_MIDI_INB_FROM_DOCK1 0x10 /* Audio Dock-1 MIDI in to Alice 2 MIDI B */ | |
1023 | #define EMU_HANA_MIDI_INB_FROM_DOCK2 0x18 /* Audio Dock-2 MIDI in to Alice 2 MIDI B */ | |
9f4bd5dd JCD |
1024 | |
1025 | #define EMU_HANA_DOCK_LEDS_1 0x0d /* 000xxxx 4 bit Audio Dock LEDs */ | |
1026 | #define EMU_HANA_DOCK_LEDS_1_MIDI1 0x01 /* MIDI 1 LED on */ | |
1027 | #define EMU_HANA_DOCK_LEDS_1_MIDI2 0x02 /* MIDI 2 LED on */ | |
1028 | #define EMU_HANA_DOCK_LEDS_1_SMPTE_IN 0x04 /* SMPTE IN LED on */ | |
1029 | #define EMU_HANA_DOCK_LEDS_1_SMPTE_OUT 0x08 /* SMPTE OUT LED on */ | |
1030 | ||
1031 | #define EMU_HANA_DOCK_LEDS_2 0x0e /* 0xxxxxx 6 bit Audio Dock LEDs */ | |
1032 | #define EMU_HANA_DOCK_LEDS_2_44K 0x01 /* 44.1 kHz LED on */ | |
1033 | #define EMU_HANA_DOCK_LEDS_2_48K 0x02 /* 48 kHz LED on */ | |
1034 | #define EMU_HANA_DOCK_LEDS_2_96K 0x04 /* 96 kHz LED on */ | |
1035 | #define EMU_HANA_DOCK_LEDS_2_192K 0x08 /* 192 kHz LED on */ | |
1036 | #define EMU_HANA_DOCK_LEDS_2_LOCK 0x10 /* LOCK LED on */ | |
1037 | #define EMU_HANA_DOCK_LEDS_2_EXT 0x20 /* EXT LED on */ | |
1038 | ||
1039 | #define EMU_HANA_DOCK_LEDS_3 0x0f /* 0xxxxxx 6 bit Audio Dock LEDs */ | |
1040 | #define EMU_HANA_DOCK_LEDS_3_CLIP_A 0x01 /* Mic A Clip LED on */ | |
1041 | #define EMU_HANA_DOCK_LEDS_3_CLIP_B 0x02 /* Mic B Clip LED on */ | |
1042 | #define EMU_HANA_DOCK_LEDS_3_SIGNAL_A 0x04 /* Signal A Clip LED on */ | |
1043 | #define EMU_HANA_DOCK_LEDS_3_SIGNAL_B 0x08 /* Signal B Clip LED on */ | |
1044 | #define EMU_HANA_DOCK_LEDS_3_MANUAL_CLIP 0x10 /* Manual Clip detection */ | |
1045 | #define EMU_HANA_DOCK_LEDS_3_MANUAL_SIGNAL 0x20 /* Manual Signal detection */ | |
1046 | ||
9148cc50 | 1047 | #define EMU_HANA_ADC_PADS 0x10 /* 0000xxx 3 bit Audio Dock ADC 14dB pads */ |
6815f535 OB |
1048 | #define EMU_HANA_DOCK_ADC_PAD1 0x01 /* 14dB Attenuation on Audio Dock ADC 1 */ |
1049 | #define EMU_HANA_DOCK_ADC_PAD2 0x02 /* 14dB Attenuation on Audio Dock ADC 2 */ | |
1050 | #define EMU_HANA_DOCK_ADC_PAD3 0x04 /* 14dB Attenuation on Audio Dock ADC 3 */ | |
1051 | #define EMU_HANA_0202_ADC_PAD1 0x08 /* 14dB Attenuation on 0202 ADC 1 */ | |
9f4bd5dd JCD |
1052 | |
1053 | #define EMU_HANA_DOCK_MISC 0x11 /* 0xxxxxx 6 bit Audio Dock misc bits */ | |
6815f535 OB |
1054 | #define EMU_HANA_DOCK_DAC1_MUTE 0x01 /* DAC 1 Mute */ |
1055 | #define EMU_HANA_DOCK_DAC2_MUTE 0x02 /* DAC 2 Mute */ | |
1056 | #define EMU_HANA_DOCK_DAC3_MUTE 0x04 /* DAC 3 Mute */ | |
1057 | #define EMU_HANA_DOCK_DAC4_MUTE 0x08 /* DAC 4 Mute */ | |
9f4bd5dd JCD |
1058 | #define EMU_HANA_DOCK_PHONES_192_DAC1 0x00 /* DAC 1 Headphones source at 192kHz */ |
1059 | #define EMU_HANA_DOCK_PHONES_192_DAC2 0x10 /* DAC 2 Headphones source at 192kHz */ | |
1060 | #define EMU_HANA_DOCK_PHONES_192_DAC3 0x20 /* DAC 3 Headphones source at 192kHz */ | |
1061 | #define EMU_HANA_DOCK_PHONES_192_DAC4 0x30 /* DAC 4 Headphones source at 192kHz */ | |
1062 | ||
9148cc50 | 1063 | #define EMU_HANA_MIDI_OUT 0x12 /* 00xxxxx 5 bit Source for each MIDI out port */ |
6815f535 OB |
1064 | #define EMU_HANA_MIDI_OUT_0202 0x01 /* 0202 MIDI from Alice 2. 0 = A, 1 = B */ |
1065 | #define EMU_HANA_MIDI_OUT_DOCK1 0x02 /* Audio Dock MIDI1 front, from Alice 2. 0 = A, 1 = B */ | |
1066 | #define EMU_HANA_MIDI_OUT_DOCK2 0x04 /* Audio Dock MIDI2 rear, from Alice 2. 0 = A, 1 = B */ | |
1067 | #define EMU_HANA_MIDI_OUT_SYNC2 0x08 /* Sync card. Not the actual MIDI out jack. 0 = A, 1 = B */ | |
1068 | #define EMU_HANA_MIDI_OUT_LOOP 0x10 /* 0 = bits (3:0) normal. 1 = MIDI loopback enabled. */ | |
9148cc50 JCD |
1069 | |
1070 | #define EMU_HANA_DAC_PADS 0x13 /* 00xxxxx 5 bit DAC 14dB attenuation pads */ | |
6815f535 OB |
1071 | #define EMU_HANA_DOCK_DAC_PAD1 0x01 /* 14dB Attenuation on AudioDock DAC 1. Left and Right */ |
1072 | #define EMU_HANA_DOCK_DAC_PAD2 0x02 /* 14dB Attenuation on AudioDock DAC 2. Left and Right */ | |
1073 | #define EMU_HANA_DOCK_DAC_PAD3 0x04 /* 14dB Attenuation on AudioDock DAC 3. Left and Right */ | |
1074 | #define EMU_HANA_DOCK_DAC_PAD4 0x08 /* 14dB Attenuation on AudioDock DAC 4. Left and Right */ | |
1075 | #define EMU_HANA_0202_DAC_PAD1 0x10 /* 14dB Attenuation on 0202 DAC 1. Left and Right */ | |
9148cc50 | 1076 | |
9f4bd5dd | 1077 | /* 0x14 - 0x1f Unused R/W registers */ |
a869057c OB |
1078 | |
1079 | #define EMU_HANA_IRQ_STATUS 0x20 /* 00xxxxx 5 bits IRQ Status */ | |
1080 | /* Same bits as for EMU_HANA_IRQ_ENABLE */ | |
1081 | /* Reading the register resets it. */ | |
9f4bd5dd JCD |
1082 | |
1083 | #define EMU_HANA_OPTION_CARDS 0x21 /* 000xxxx 4 bits Presence of option cards */ | |
6815f535 OB |
1084 | #define EMU_HANA_OPTION_HAMOA 0x01 /* Hamoa (analog I/O) card present */ |
1085 | #define EMU_HANA_OPTION_SYNC 0x02 /* Sync card present */ | |
a869057c OB |
1086 | #define EMU_HANA_OPTION_DOCK_ONLINE 0x04 /* Audio/Micro dock present and FPGA configured */ |
1087 | #define EMU_HANA_OPTION_DOCK_OFFLINE 0x08 /* Audio/Micro dock present and FPGA not configured */ | |
9f4bd5dd | 1088 | |
a869057c OB |
1089 | #define EMU_HANA_ID 0x22 /* 1010101 7 bits ID byte & 0x7f = 0x55 with Alice2 */ |
1090 | /* 0010101 5 bits ID byte & 0x1f = 0x15 with Tina/2 */ | |
9f4bd5dd JCD |
1091 | |
1092 | #define EMU_HANA_MAJOR_REV 0x23 /* 0000xxx 3 bit Hana FPGA Major rev */ | |
1093 | #define EMU_HANA_MINOR_REV 0x24 /* 0000xxx 3 bit Hana FPGA Minor rev */ | |
1094 | ||
1095 | #define EMU_DOCK_MAJOR_REV 0x25 /* 0000xxx 3 bit Audio Dock FPGA Major rev */ | |
1096 | #define EMU_DOCK_MINOR_REV 0x26 /* 0000xxx 3 bit Audio Dock FPGA Minor rev */ | |
1097 | ||
1098 | #define EMU_DOCK_BOARD_ID 0x27 /* 00000xx 2 bits Audio Dock ID pins */ | |
6815f535 OB |
1099 | #define EMU_DOCK_BOARD_ID0 0x00 /* ID bit 0 */ |
1100 | #define EMU_DOCK_BOARD_ID1 0x03 /* ID bit 1 */ | |
9f4bd5dd JCD |
1101 | |
1102 | #define EMU_HANA_WC_SPDIF_HI 0x28 /* 0xxxxxx 6 bit SPDIF IN Word clock, upper 6 bits */ | |
1103 | #define EMU_HANA_WC_SPDIF_LO 0x29 /* 0xxxxxx 6 bit SPDIF IN Word clock, lower 6 bits */ | |
1104 | ||
1105 | #define EMU_HANA_WC_ADAT_HI 0x2a /* 0xxxxxx 6 bit ADAT IN Word clock, upper 6 bits */ | |
1106 | #define EMU_HANA_WC_ADAT_LO 0x2b /* 0xxxxxx 6 bit ADAT IN Word clock, lower 6 bits */ | |
1107 | ||
1108 | #define EMU_HANA_WC_BNC_LO 0x2c /* 0xxxxxx 6 bit BNC IN Word clock, lower 6 bits */ | |
1109 | #define EMU_HANA_WC_BNC_HI 0x2d /* 0xxxxxx 6 bit BNC IN Word clock, upper 6 bits */ | |
1110 | ||
1111 | #define EMU_HANA2_WC_SPDIF_HI 0x2e /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, upper 6 bits */ | |
1112 | #define EMU_HANA2_WC_SPDIF_LO 0x2f /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, lower 6 bits */ | |
a869057c | 1113 | |
9f4bd5dd JCD |
1114 | /* 0x30 - 0x3f Unused Read only registers */ |
1115 | ||
145ec1fd OB |
1116 | // The meaning of this is not clear; kX-project just calls it "lock" in some info-only code. |
1117 | #define EMU_HANA_LOCK_STS_LO 0x38 /* 0xxxxxx lower 6 bits */ | |
1118 | #define EMU_HANA_LOCK_STS_HI 0x39 /* 0xxxxxx upper 6 bits */ | |
1119 | ||
9f4bd5dd | 1120 | /************************************************************************************************/ |
a869057c | 1121 | /* EMU1010 Audio Destinations */ |
9f4bd5dd | 1122 | /************************************************************************************************/ |
a869057c | 1123 | /* Hana, original 1010,1212m,1820[m] using Alice2 |
44893a36 | 1124 | * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2 |
a869057c OB |
1125 | * 0x01, 0x00-0x1f: 32 EDI channels to Audio Dock |
1126 | * 0x00: Dock DAC 1 Left | |
1127 | * 0x04: Dock DAC 1 Right | |
1128 | * 0x08: Dock DAC 2 Left | |
1129 | * 0x0c: Dock DAC 2 Right | |
1130 | * 0x10: Dock DAC 3 Left | |
1131 | * 0x12: PHONES Left (n/a in 2x/4x mode; output mirrors DAC4 Left) | |
1132 | * 0x14: Dock DAC 3 Right | |
1133 | * 0x16: PHONES Right (n/a in 2x/4x mode; output mirrors DAC4 Right) | |
1134 | * 0x18: Dock DAC 4 Left | |
1135 | * 0x1a: S/PDIF Left | |
1136 | * 0x1c: Dock DAC 4 Right | |
1137 | * 0x1e: S/PDIF Right | |
44893a36 JCD |
1138 | * 0x02, 0x00: Hana S/PDIF Left |
1139 | * 0x02, 0x01: Hana S/PDIF Right | |
a869057c OB |
1140 | * 0x03, 0x00: Hamoa DAC Left |
1141 | * 0x03, 0x01: Hamoa DAC Right | |
44893a36 JCD |
1142 | * 0x04, 0x00-0x07: Hana ADAT |
1143 | * 0x05, 0x00: I2S0 Left to Alice2 | |
1144 | * 0x05, 0x01: I2S0 Right to Alice2 | |
1145 | * 0x06, 0x00: I2S0 Left to Alice2 | |
1146 | * 0x06, 0x01: I2S0 Right to Alice2 | |
1147 | * 0x07, 0x00: I2S0 Left to Alice2 | |
1148 | * 0x07, 0x01: I2S0 Right to Alice2 | |
1149 | * | |
1150 | * Hana2 never released, but used Tina | |
1151 | * Not needed. | |
1152 | * | |
a869057c | 1153 | * Hana3, rev2 1010,1212m,1616[m] using Tina |
44893a36 | 1154 | * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina |
a869057c OB |
1155 | * 0x01, 0x00-0x1f: 32 EDI channels to Micro Dock |
1156 | * 0x00: Dock DAC 1 Left | |
1157 | * 0x04: Dock DAC 1 Right | |
1158 | * 0x08: Dock DAC 2 Left | |
1159 | * 0x0c: Dock DAC 2 Right | |
1160 | * 0x10: Dock DAC 3 Left | |
1161 | * 0x12: Dock S/PDIF Left | |
1162 | * 0x14: Dock DAC 3 Right | |
1163 | * 0x16: Dock S/PDIF Right | |
1164 | * 0x18-0x1f: Dock ADAT 0-7 | |
44893a36 JCD |
1165 | * 0x02, 0x00: Hana3 S/PDIF Left |
1166 | * 0x02, 0x01: Hana3 S/PDIF Right | |
a869057c OB |
1167 | * 0x03, 0x00: Hamoa DAC Left |
1168 | * 0x03, 0x01: Hamoa DAC Right | |
44893a36 JCD |
1169 | * 0x04, 0x00-0x07: Hana3 ADAT 0-7 |
1170 | * 0x05, 0x00-0x0f: 16 EMU32B channels to Tina | |
1171 | * 0x06-0x07: Not used | |
1172 | * | |
1173 | * HanaLite, rev1 0404 using Alice2 | |
a869057c OB |
1174 | * HanaLiteLite, rev2 0404 using Tina |
1175 | * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2/Tina | |
44893a36 JCD |
1176 | * 0x01: Not used |
1177 | * 0x02, 0x00: S/PDIF Left | |
1178 | * 0x02, 0x01: S/PDIF Right | |
1179 | * 0x03, 0x00: DAC Left | |
1180 | * 0x03, 0x01: DAC Right | |
1181 | * 0x04-0x07: Not used | |
1182 | * | |
1183 | * Mana, Cardbus 1616 using Tina2 | |
44893a36 | 1184 | * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina2 |
a869057c OB |
1185 | * 0x01, 0x00-0x1f: 32 EDI channels to Micro Dock |
1186 | * (same as rev2 1010) | |
44893a36 JCD |
1187 | * 0x02: Not used |
1188 | * 0x03, 0x00: Mana DAC Left | |
1189 | * 0x03, 0x01: Mana DAC Right | |
1190 | * 0x04, 0x00-0x0f: 16 EMU32B channels to Tina2 | |
1191 | * 0x05-0x07: Not used | |
44893a36 | 1192 | */ |
a869057c | 1193 | |
13d45709 | 1194 | /* 32-bit destinations of signal in the Hana FPGA. Destinations are either |
a869057c OB |
1195 | * physical outputs of Hana, or outputs going to Alice2/Tina for capture - |
1196 | * 16 x EMU_DST_ALICE2_EMU32_X (2x on rev2 boards). Which data is fed into | |
1197 | * a channel depends on the mixer control setting for each destination - see | |
536438f1 | 1198 | * the register arrays in emumixer.c. |
13d45709 | 1199 | */ |
9f4bd5dd | 1200 | #define EMU_DST_ALICE2_EMU32_0 0x000f /* 16 EMU32 channels to Alice2 +0 to +0xf */ |
f549466b | 1201 | /* This channel is delayed by one sample. */ |
9f4bd5dd JCD |
1202 | #define EMU_DST_ALICE2_EMU32_1 0x0000 /* 16 EMU32 channels to Alice2 +0 to +0xf */ |
1203 | #define EMU_DST_ALICE2_EMU32_2 0x0001 /* 16 EMU32 channels to Alice2 +0 to +0xf */ | |
1204 | #define EMU_DST_ALICE2_EMU32_3 0x0002 /* 16 EMU32 channels to Alice2 +0 to +0xf */ | |
1205 | #define EMU_DST_ALICE2_EMU32_4 0x0003 /* 16 EMU32 channels to Alice2 +0 to +0xf */ | |
1206 | #define EMU_DST_ALICE2_EMU32_5 0x0004 /* 16 EMU32 channels to Alice2 +0 to +0xf */ | |
1207 | #define EMU_DST_ALICE2_EMU32_6 0x0005 /* 16 EMU32 channels to Alice2 +0 to +0xf */ | |
1208 | #define EMU_DST_ALICE2_EMU32_7 0x0006 /* 16 EMU32 channels to Alice2 +0 to +0xf */ | |
1209 | #define EMU_DST_ALICE2_EMU32_8 0x0007 /* 16 EMU32 channels to Alice2 +0 to +0xf */ | |
1210 | #define EMU_DST_ALICE2_EMU32_9 0x0008 /* 16 EMU32 channels to Alice2 +0 to +0xf */ | |
1211 | #define EMU_DST_ALICE2_EMU32_A 0x0009 /* 16 EMU32 channels to Alice2 +0 to +0xf */ | |
1212 | #define EMU_DST_ALICE2_EMU32_B 0x000a /* 16 EMU32 channels to Alice2 +0 to +0xf */ | |
1213 | #define EMU_DST_ALICE2_EMU32_C 0x000b /* 16 EMU32 channels to Alice2 +0 to +0xf */ | |
1214 | #define EMU_DST_ALICE2_EMU32_D 0x000c /* 16 EMU32 channels to Alice2 +0 to +0xf */ | |
1215 | #define EMU_DST_ALICE2_EMU32_E 0x000d /* 16 EMU32 channels to Alice2 +0 to +0xf */ | |
1216 | #define EMU_DST_ALICE2_EMU32_F 0x000e /* 16 EMU32 channels to Alice2 +0 to +0xf */ | |
1217 | #define EMU_DST_DOCK_DAC1_LEFT1 0x0100 /* Audio Dock DAC1 Left, 1st or 48kHz only */ | |
1218 | #define EMU_DST_DOCK_DAC1_LEFT2 0x0101 /* Audio Dock DAC1 Left, 2nd or 96kHz */ | |
1219 | #define EMU_DST_DOCK_DAC1_LEFT3 0x0102 /* Audio Dock DAC1 Left, 3rd or 192kHz */ | |
1220 | #define EMU_DST_DOCK_DAC1_LEFT4 0x0103 /* Audio Dock DAC1 Left, 4th or 192kHz */ | |
1221 | #define EMU_DST_DOCK_DAC1_RIGHT1 0x0104 /* Audio Dock DAC1 Right, 1st or 48kHz only */ | |
1222 | #define EMU_DST_DOCK_DAC1_RIGHT2 0x0105 /* Audio Dock DAC1 Right, 2nd or 96kHz */ | |
1223 | #define EMU_DST_DOCK_DAC1_RIGHT3 0x0106 /* Audio Dock DAC1 Right, 3rd or 192kHz */ | |
1224 | #define EMU_DST_DOCK_DAC1_RIGHT4 0x0107 /* Audio Dock DAC1 Right, 4th or 192kHz */ | |
1225 | #define EMU_DST_DOCK_DAC2_LEFT1 0x0108 /* Audio Dock DAC2 Left, 1st or 48kHz only */ | |
1226 | #define EMU_DST_DOCK_DAC2_LEFT2 0x0109 /* Audio Dock DAC2 Left, 2nd or 96kHz */ | |
1227 | #define EMU_DST_DOCK_DAC2_LEFT3 0x010a /* Audio Dock DAC2 Left, 3rd or 192kHz */ | |
1228 | #define EMU_DST_DOCK_DAC2_LEFT4 0x010b /* Audio Dock DAC2 Left, 4th or 192kHz */ | |
1229 | #define EMU_DST_DOCK_DAC2_RIGHT1 0x010c /* Audio Dock DAC2 Right, 1st or 48kHz only */ | |
1230 | #define EMU_DST_DOCK_DAC2_RIGHT2 0x010d /* Audio Dock DAC2 Right, 2nd or 96kHz */ | |
1231 | #define EMU_DST_DOCK_DAC2_RIGHT3 0x010e /* Audio Dock DAC2 Right, 3rd or 192kHz */ | |
1232 | #define EMU_DST_DOCK_DAC2_RIGHT4 0x010f /* Audio Dock DAC2 Right, 4th or 192kHz */ | |
1233 | #define EMU_DST_DOCK_DAC3_LEFT1 0x0110 /* Audio Dock DAC1 Left, 1st or 48kHz only */ | |
1234 | #define EMU_DST_DOCK_DAC3_LEFT2 0x0111 /* Audio Dock DAC1 Left, 2nd or 96kHz */ | |
1235 | #define EMU_DST_DOCK_DAC3_LEFT3 0x0112 /* Audio Dock DAC1 Left, 3rd or 192kHz */ | |
1236 | #define EMU_DST_DOCK_DAC3_LEFT4 0x0113 /* Audio Dock DAC1 Left, 4th or 192kHz */ | |
1237 | #define EMU_DST_DOCK_PHONES_LEFT1 0x0112 /* Audio Dock PHONES Left, 1st or 48kHz only */ | |
1238 | #define EMU_DST_DOCK_PHONES_LEFT2 0x0113 /* Audio Dock PHONES Left, 2nd or 96kHz */ | |
1239 | #define EMU_DST_DOCK_DAC3_RIGHT1 0x0114 /* Audio Dock DAC1 Right, 1st or 48kHz only */ | |
1240 | #define EMU_DST_DOCK_DAC3_RIGHT2 0x0115 /* Audio Dock DAC1 Right, 2nd or 96kHz */ | |
1241 | #define EMU_DST_DOCK_DAC3_RIGHT3 0x0116 /* Audio Dock DAC1 Right, 3rd or 192kHz */ | |
1242 | #define EMU_DST_DOCK_DAC3_RIGHT4 0x0117 /* Audio Dock DAC1 Right, 4th or 192kHz */ | |
1243 | #define EMU_DST_DOCK_PHONES_RIGHT1 0x0116 /* Audio Dock PHONES Right, 1st or 48kHz only */ | |
1244 | #define EMU_DST_DOCK_PHONES_RIGHT2 0x0117 /* Audio Dock PHONES Right, 2nd or 96kHz */ | |
1245 | #define EMU_DST_DOCK_DAC4_LEFT1 0x0118 /* Audio Dock DAC2 Left, 1st or 48kHz only */ | |
1246 | #define EMU_DST_DOCK_DAC4_LEFT2 0x0119 /* Audio Dock DAC2 Left, 2nd or 96kHz */ | |
1247 | #define EMU_DST_DOCK_DAC4_LEFT3 0x011a /* Audio Dock DAC2 Left, 3rd or 192kHz */ | |
1248 | #define EMU_DST_DOCK_DAC4_LEFT4 0x011b /* Audio Dock DAC2 Left, 4th or 192kHz */ | |
1249 | #define EMU_DST_DOCK_SPDIF_LEFT1 0x011a /* Audio Dock SPDIF Left, 1st or 48kHz only */ | |
1250 | #define EMU_DST_DOCK_SPDIF_LEFT2 0x011b /* Audio Dock SPDIF Left, 2nd or 96kHz */ | |
1251 | #define EMU_DST_DOCK_DAC4_RIGHT1 0x011c /* Audio Dock DAC2 Right, 1st or 48kHz only */ | |
1252 | #define EMU_DST_DOCK_DAC4_RIGHT2 0x011d /* Audio Dock DAC2 Right, 2nd or 96kHz */ | |
1253 | #define EMU_DST_DOCK_DAC4_RIGHT3 0x011e /* Audio Dock DAC2 Right, 3rd or 192kHz */ | |
1254 | #define EMU_DST_DOCK_DAC4_RIGHT4 0x011f /* Audio Dock DAC2 Right, 4th or 192kHz */ | |
1255 | #define EMU_DST_DOCK_SPDIF_RIGHT1 0x011e /* Audio Dock SPDIF Right, 1st or 48kHz only */ | |
1256 | #define EMU_DST_DOCK_SPDIF_RIGHT2 0x011f /* Audio Dock SPDIF Right, 2nd or 96kHz */ | |
1257 | #define EMU_DST_HANA_SPDIF_LEFT1 0x0200 /* Hana SPDIF Left, 1st or 48kHz only */ | |
1258 | #define EMU_DST_HANA_SPDIF_LEFT2 0x0202 /* Hana SPDIF Left, 2nd or 96kHz */ | |
145ec1fd OB |
1259 | #define EMU_DST_HANA_SPDIF_LEFT3 0x0204 /* Hana SPDIF Left, 3rd or 192kHz */ |
1260 | #define EMU_DST_HANA_SPDIF_LEFT4 0x0206 /* Hana SPDIF Left, 4th or 192kHz */ | |
9f4bd5dd JCD |
1261 | #define EMU_DST_HANA_SPDIF_RIGHT1 0x0201 /* Hana SPDIF Right, 1st or 48kHz only */ |
1262 | #define EMU_DST_HANA_SPDIF_RIGHT2 0x0203 /* Hana SPDIF Right, 2nd or 96kHz */ | |
145ec1fd OB |
1263 | #define EMU_DST_HANA_SPDIF_RIGHT3 0x0205 /* Hana SPDIF Right, 3rd or 192kHz */ |
1264 | #define EMU_DST_HANA_SPDIF_RIGHT4 0x0207 /* Hana SPDIF Right, 4th or 192kHz */ | |
9f4bd5dd JCD |
1265 | #define EMU_DST_HAMOA_DAC_LEFT1 0x0300 /* Hamoa DAC Left, 1st or 48kHz only */ |
1266 | #define EMU_DST_HAMOA_DAC_LEFT2 0x0302 /* Hamoa DAC Left, 2nd or 96kHz */ | |
1267 | #define EMU_DST_HAMOA_DAC_LEFT3 0x0304 /* Hamoa DAC Left, 3rd or 192kHz */ | |
1268 | #define EMU_DST_HAMOA_DAC_LEFT4 0x0306 /* Hamoa DAC Left, 4th or 192kHz */ | |
1269 | #define EMU_DST_HAMOA_DAC_RIGHT1 0x0301 /* Hamoa DAC Right, 1st or 48kHz only */ | |
1270 | #define EMU_DST_HAMOA_DAC_RIGHT2 0x0303 /* Hamoa DAC Right, 2nd or 96kHz */ | |
1271 | #define EMU_DST_HAMOA_DAC_RIGHT3 0x0305 /* Hamoa DAC Right, 3rd or 192kHz */ | |
1272 | #define EMU_DST_HAMOA_DAC_RIGHT4 0x0307 /* Hamoa DAC Right, 4th or 192kHz */ | |
a869057c | 1273 | // In S/MUX mode, the samples of one channel are adjacent. |
9f4bd5dd JCD |
1274 | #define EMU_DST_HANA_ADAT 0x0400 /* Hana ADAT 8 channel out +0 to +7 */ |
1275 | #define EMU_DST_ALICE_I2S0_LEFT 0x0500 /* Alice2 I2S0 Left */ | |
1276 | #define EMU_DST_ALICE_I2S0_RIGHT 0x0501 /* Alice2 I2S0 Right */ | |
1277 | #define EMU_DST_ALICE_I2S1_LEFT 0x0600 /* Alice2 I2S1 Left */ | |
1278 | #define EMU_DST_ALICE_I2S1_RIGHT 0x0601 /* Alice2 I2S1 Right */ | |
1279 | #define EMU_DST_ALICE_I2S2_LEFT 0x0700 /* Alice2 I2S2 Left */ | |
1280 | #define EMU_DST_ALICE_I2S2_RIGHT 0x0701 /* Alice2 I2S2 Right */ | |
1281 | ||
1c02e366 | 1282 | /* Additional destinations for 1616(M)/Microdock */ |
a869057c OB |
1283 | |
1284 | #define EMU_DST_MDOCK_SPDIF_LEFT1 0x0112 /* Microdock S/PDIF OUT Left, 1st or 48kHz only */ | |
1285 | #define EMU_DST_MDOCK_SPDIF_LEFT2 0x0113 /* Microdock S/PDIF OUT Left, 2nd or 96kHz */ | |
1286 | #define EMU_DST_MDOCK_SPDIF_RIGHT1 0x0116 /* Microdock S/PDIF OUT Right, 1st or 48kHz only */ | |
1287 | #define EMU_DST_MDOCK_SPDIF_RIGHT2 0x0117 /* Microdock S/PDIF OUT Right, 2nd or 96kHz */ | |
1288 | #define EMU_DST_MDOCK_ADAT 0x0118 /* Microdock S/PDIF ADAT 8 channel out +8 to +f */ | |
1289 | ||
1290 | #define EMU_DST_MANA_DAC_LEFT 0x0300 /* Headphone jack on 1010 cardbus? 44.1/48kHz only? */ | |
1291 | #define EMU_DST_MANA_DAC_RIGHT 0x0301 /* Headphone jack on 1010 cardbus? 44.1/48kHz only? */ | |
1c02e366 | 1292 | |
9f4bd5dd | 1293 | /************************************************************************************************/ |
a869057c | 1294 | /* EMU1010 Audio Sources */ |
9f4bd5dd | 1295 | /************************************************************************************************/ |
a869057c OB |
1296 | /* Hana, original 1010,1212m,1820[m] using Alice2 |
1297 | * 0x00, 0x00-0x1f: Silence | |
1298 | * 0x01, 0x00-0x1f: 32 EDI channels from Audio Dock | |
1299 | * 0x00: Dock Mic A | |
1300 | * 0x04: Dock Mic B | |
1301 | * 0x08: Dock ADC 1 Left | |
1302 | * 0x0c: Dock ADC 1 Right | |
1303 | * 0x10: Dock ADC 2 Left | |
1304 | * 0x14: Dock ADC 2 Right | |
1305 | * 0x18: Dock ADC 3 Left | |
1306 | * 0x1c: Dock ADC 3 Right | |
1307 | * 0x02, 0x00: Hamoa ADC Left | |
1308 | * 0x02, 0x01: Hamoa ADC Right | |
44893a36 JCD |
1309 | * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output |
1310 | * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output | |
1311 | * 0x04, 0x00-0x07: Hana ADAT | |
1312 | * 0x05, 0x00: Hana S/PDIF Left | |
1313 | * 0x05, 0x01: Hana S/PDIF Right | |
1314 | * 0x06-0x07: Not used | |
1315 | * | |
1316 | * Hana2 never released, but used Tina | |
1317 | * Not needed. | |
1318 | * | |
a869057c OB |
1319 | * Hana3, rev2 1010,1212m,1616[m] using Tina |
1320 | * 0x00, 0x00-0x1f: Silence | |
1321 | * 0x01, 0x00-0x1f: 32 EDI channels from Micro Dock | |
1322 | * 0x00: Dock Mic A | |
1323 | * 0x04: Dock Mic B | |
1324 | * 0x08: Dock ADC 1 Left | |
1325 | * 0x0c: Dock ADC 1 Right | |
1326 | * 0x10: Dock ADC 2 Left | |
1327 | * 0x12: Dock S/PDIF Left | |
1328 | * 0x14: Dock ADC 2 Right | |
1329 | * 0x16: Dock S/PDIF Right | |
1330 | * 0x18-0x1f: Dock ADAT 0-7 | |
1331 | * 0x02, 0x00: Hamoa ADC Left | |
1332 | * 0x02, 0x01: Hamoa ADC Right | |
44893a36 JCD |
1333 | * 0x03, 0x00-0x0f: 16 inputs from Tina Emu32A output |
1334 | * 0x03, 0x10-0x1f: 16 inputs from Tina Emu32B output | |
1335 | * 0x04, 0x00-0x07: Hana3 ADAT | |
1336 | * 0x05, 0x00: Hana3 S/PDIF Left | |
1337 | * 0x05, 0x01: Hana3 S/PDIF Right | |
1338 | * 0x06-0x07: Not used | |
1339 | * | |
1340 | * HanaLite, rev1 0404 using Alice2 | |
a869057c OB |
1341 | * HanaLiteLite, rev2 0404 using Tina |
1342 | * 0x00, 0x00-0x1f: Silence | |
44893a36 JCD |
1343 | * 0x01: Not used |
1344 | * 0x02, 0x00: ADC Left | |
1345 | * 0x02, 0x01: ADC Right | |
a869057c OB |
1346 | * 0x03, 0x00-0x0f: 16 inputs from Alice2/Tina Emu32A output |
1347 | * 0x03, 0x10-0x1f: 16 inputs from Alice2/Tina Emu32B output | |
44893a36 JCD |
1348 | * 0x04: Not used |
1349 | * 0x05, 0x00: S/PDIF Left | |
1350 | * 0x05, 0x01: S/PDIF Right | |
1351 | * 0x06-0x07: Not used | |
1352 | * | |
1353 | * Mana, Cardbus 1616 using Tina2 | |
a869057c OB |
1354 | * 0x00, 0x00-0x1f: Silence |
1355 | * 0x01, 0x00-0x1f: 32 EDI channels from Micro Dock | |
1356 | * (same as rev2 1010) | |
44893a36 | 1357 | * 0x02: Not used |
a869057c OB |
1358 | * 0x03, 0x00-0x0f: 16 inputs from Tina2 Emu32A output |
1359 | * 0x03, 0x10-0x1f: 16 inputs from Tina2 Emu32B output | |
44893a36 | 1360 | * 0x04-0x07: Not used |
44893a36 JCD |
1361 | */ |
1362 | ||
13d45709 | 1363 | /* 32-bit sources of signal in the Hana FPGA. The sources are routed to |
a869057c OB |
1364 | * destinations using a mixer control for each destination - see emumixer.c. |
1365 | * Sources are either physical inputs of Hana, or inputs from Alice2/Tina - | |
1366 | * 16 x EMU_SRC_ALICE_EMU32A + 16 x EMU_SRC_ALICE_EMU32B. | |
13d45709 | 1367 | */ |
9f4bd5dd JCD |
1368 | #define EMU_SRC_SILENCE 0x0000 /* Silence */ |
1369 | #define EMU_SRC_DOCK_MIC_A1 0x0100 /* Audio Dock Mic A, 1st or 48kHz only */ | |
1370 | #define EMU_SRC_DOCK_MIC_A2 0x0101 /* Audio Dock Mic A, 2nd or 96kHz */ | |
1371 | #define EMU_SRC_DOCK_MIC_A3 0x0102 /* Audio Dock Mic A, 3rd or 192kHz */ | |
1372 | #define EMU_SRC_DOCK_MIC_A4 0x0103 /* Audio Dock Mic A, 4th or 192kHz */ | |
1373 | #define EMU_SRC_DOCK_MIC_B1 0x0104 /* Audio Dock Mic B, 1st or 48kHz only */ | |
1374 | #define EMU_SRC_DOCK_MIC_B2 0x0105 /* Audio Dock Mic B, 2nd or 96kHz */ | |
1375 | #define EMU_SRC_DOCK_MIC_B3 0x0106 /* Audio Dock Mic B, 3rd or 192kHz */ | |
1376 | #define EMU_SRC_DOCK_MIC_B4 0x0107 /* Audio Dock Mic B, 4th or 192kHz */ | |
1377 | #define EMU_SRC_DOCK_ADC1_LEFT1 0x0108 /* Audio Dock ADC1 Left, 1st or 48kHz only */ | |
1378 | #define EMU_SRC_DOCK_ADC1_LEFT2 0x0109 /* Audio Dock ADC1 Left, 2nd or 96kHz */ | |
1379 | #define EMU_SRC_DOCK_ADC1_LEFT3 0x010a /* Audio Dock ADC1 Left, 3rd or 192kHz */ | |
1380 | #define EMU_SRC_DOCK_ADC1_LEFT4 0x010b /* Audio Dock ADC1 Left, 4th or 192kHz */ | |
1381 | #define EMU_SRC_DOCK_ADC1_RIGHT1 0x010c /* Audio Dock ADC1 Right, 1st or 48kHz only */ | |
1382 | #define EMU_SRC_DOCK_ADC1_RIGHT2 0x010d /* Audio Dock ADC1 Right, 2nd or 96kHz */ | |
1383 | #define EMU_SRC_DOCK_ADC1_RIGHT3 0x010e /* Audio Dock ADC1 Right, 3rd or 192kHz */ | |
1384 | #define EMU_SRC_DOCK_ADC1_RIGHT4 0x010f /* Audio Dock ADC1 Right, 4th or 192kHz */ | |
1385 | #define EMU_SRC_DOCK_ADC2_LEFT1 0x0110 /* Audio Dock ADC2 Left, 1st or 48kHz only */ | |
1386 | #define EMU_SRC_DOCK_ADC2_LEFT2 0x0111 /* Audio Dock ADC2 Left, 2nd or 96kHz */ | |
1387 | #define EMU_SRC_DOCK_ADC2_LEFT3 0x0112 /* Audio Dock ADC2 Left, 3rd or 192kHz */ | |
1388 | #define EMU_SRC_DOCK_ADC2_LEFT4 0x0113 /* Audio Dock ADC2 Left, 4th or 192kHz */ | |
1389 | #define EMU_SRC_DOCK_ADC2_RIGHT1 0x0114 /* Audio Dock ADC2 Right, 1st or 48kHz only */ | |
1390 | #define EMU_SRC_DOCK_ADC2_RIGHT2 0x0115 /* Audio Dock ADC2 Right, 2nd or 96kHz */ | |
1391 | #define EMU_SRC_DOCK_ADC2_RIGHT3 0x0116 /* Audio Dock ADC2 Right, 3rd or 192kHz */ | |
1392 | #define EMU_SRC_DOCK_ADC2_RIGHT4 0x0117 /* Audio Dock ADC2 Right, 4th or 192kHz */ | |
1393 | #define EMU_SRC_DOCK_ADC3_LEFT1 0x0118 /* Audio Dock ADC3 Left, 1st or 48kHz only */ | |
1394 | #define EMU_SRC_DOCK_ADC3_LEFT2 0x0119 /* Audio Dock ADC3 Left, 2nd or 96kHz */ | |
1395 | #define EMU_SRC_DOCK_ADC3_LEFT3 0x011a /* Audio Dock ADC3 Left, 3rd or 192kHz */ | |
1396 | #define EMU_SRC_DOCK_ADC3_LEFT4 0x011b /* Audio Dock ADC3 Left, 4th or 192kHz */ | |
1397 | #define EMU_SRC_DOCK_ADC3_RIGHT1 0x011c /* Audio Dock ADC3 Right, 1st or 48kHz only */ | |
1398 | #define EMU_SRC_DOCK_ADC3_RIGHT2 0x011d /* Audio Dock ADC3 Right, 2nd or 96kHz */ | |
1399 | #define EMU_SRC_DOCK_ADC3_RIGHT3 0x011e /* Audio Dock ADC3 Right, 3rd or 192kHz */ | |
1400 | #define EMU_SRC_DOCK_ADC3_RIGHT4 0x011f /* Audio Dock ADC3 Right, 4th or 192kHz */ | |
1401 | #define EMU_SRC_HAMOA_ADC_LEFT1 0x0200 /* Hamoa ADC Left, 1st or 48kHz only */ | |
1402 | #define EMU_SRC_HAMOA_ADC_LEFT2 0x0202 /* Hamoa ADC Left, 2nd or 96kHz */ | |
1403 | #define EMU_SRC_HAMOA_ADC_LEFT3 0x0204 /* Hamoa ADC Left, 3rd or 192kHz */ | |
1404 | #define EMU_SRC_HAMOA_ADC_LEFT4 0x0206 /* Hamoa ADC Left, 4th or 192kHz */ | |
1405 | #define EMU_SRC_HAMOA_ADC_RIGHT1 0x0201 /* Hamoa ADC Right, 1st or 48kHz only */ | |
1406 | #define EMU_SRC_HAMOA_ADC_RIGHT2 0x0203 /* Hamoa ADC Right, 2nd or 96kHz */ | |
1407 | #define EMU_SRC_HAMOA_ADC_RIGHT3 0x0205 /* Hamoa ADC Right, 3rd or 192kHz */ | |
1408 | #define EMU_SRC_HAMOA_ADC_RIGHT4 0x0207 /* Hamoa ADC Right, 4th or 192kHz */ | |
1409 | #define EMU_SRC_ALICE_EMU32A 0x0300 /* Alice2 EMU32a 16 outputs. +0 to +0xf */ | |
1410 | #define EMU_SRC_ALICE_EMU32B 0x0310 /* Alice2 EMU32b 16 outputs. +0 to +0xf */ | |
a869057c | 1411 | // In S/MUX mode, the samples of one channel are adjacent. |
9f4bd5dd JCD |
1412 | #define EMU_SRC_HANA_ADAT 0x0400 /* Hana ADAT 8 channel in +0 to +7 */ |
1413 | #define EMU_SRC_HANA_SPDIF_LEFT1 0x0500 /* Hana SPDIF Left, 1st or 48kHz only */ | |
1414 | #define EMU_SRC_HANA_SPDIF_LEFT2 0x0502 /* Hana SPDIF Left, 2nd or 96kHz */ | |
145ec1fd OB |
1415 | #define EMU_SRC_HANA_SPDIF_LEFT3 0x0504 /* Hana SPDIF Left, 3rd or 192kHz */ |
1416 | #define EMU_SRC_HANA_SPDIF_LEFT4 0x0506 /* Hana SPDIF Left, 4th or 192kHz */ | |
9f4bd5dd JCD |
1417 | #define EMU_SRC_HANA_SPDIF_RIGHT1 0x0501 /* Hana SPDIF Right, 1st or 48kHz only */ |
1418 | #define EMU_SRC_HANA_SPDIF_RIGHT2 0x0503 /* Hana SPDIF Right, 2nd or 96kHz */ | |
145ec1fd OB |
1419 | #define EMU_SRC_HANA_SPDIF_RIGHT3 0x0505 /* Hana SPDIF Right, 3rd or 192kHz */ |
1420 | #define EMU_SRC_HANA_SPDIF_RIGHT4 0x0507 /* Hana SPDIF Right, 4th or 192kHz */ | |
1c02e366 CF |
1421 | |
1422 | /* Additional inputs for 1616(M)/Microdock */ | |
a869057c OB |
1423 | |
1424 | #define EMU_SRC_MDOCK_SPDIF_LEFT1 0x0112 /* Microdock S/PDIF Left, 1st or 48kHz only */ | |
1425 | #define EMU_SRC_MDOCK_SPDIF_LEFT2 0x0113 /* Microdock S/PDIF Left, 2nd or 96kHz */ | |
1426 | #define EMU_SRC_MDOCK_SPDIF_RIGHT1 0x0116 /* Microdock S/PDIF Right, 1st or 48kHz only */ | |
1427 | #define EMU_SRC_MDOCK_SPDIF_RIGHT2 0x0117 /* Microdock S/PDIF Right, 2nd or 96kHz */ | |
1428 | #define EMU_SRC_MDOCK_ADAT 0x0118 /* Microdock ADAT 8 channel in +8 to +f */ | |
1c02e366 | 1429 | |
9f4bd5dd | 1430 | /* 0x600 and 0x700 no used */ |
1da177e4 LT |
1431 | |
1432 | /* ------------------- STRUCTURES -------------------- */ | |
1433 | ||
eb4698f3 | 1434 | enum { |
1da177e4 LT |
1435 | EMU10K1_EFX, |
1436 | EMU10K1_PCM, | |
1437 | EMU10K1_SYNTH, | |
1438 | EMU10K1_MIDI | |
eb4698f3 TI |
1439 | }; |
1440 | ||
1441 | struct snd_emu10k1; | |
1da177e4 | 1442 | |
eb4698f3 | 1443 | struct snd_emu10k1_voice { |
1da177e4 LT |
1444 | int number; |
1445 | unsigned int use: 1, | |
1446 | pcm: 1, | |
1447 | efx: 1, | |
1448 | synth: 1, | |
1449 | midi: 1; | |
eb4698f3 | 1450 | void (*interrupt)(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice); |
1da177e4 | 1451 | |
eb4698f3 | 1452 | struct snd_emu10k1_pcm *epcm; |
1da177e4 LT |
1453 | }; |
1454 | ||
eb4698f3 | 1455 | enum { |
1da177e4 LT |
1456 | PLAYBACK_EMUVOICE, |
1457 | PLAYBACK_EFX, | |
1458 | CAPTURE_AC97ADC, | |
1459 | CAPTURE_AC97MIC, | |
1460 | CAPTURE_EFX | |
eb4698f3 TI |
1461 | }; |
1462 | ||
1463 | struct snd_emu10k1_pcm { | |
1464 | struct snd_emu10k1 *emu; | |
1465 | int type; | |
1466 | struct snd_pcm_substream *substream; | |
1467 | struct snd_emu10k1_voice *voices[NUM_EFX_PLAYBACK]; | |
1468 | struct snd_emu10k1_voice *extra; | |
1da177e4 LT |
1469 | unsigned short running; |
1470 | unsigned short first_ptr; | |
eb4698f3 | 1471 | struct snd_util_memblk *memblk; |
1da177e4 LT |
1472 | unsigned int start_addr; |
1473 | unsigned int ccca_start_addr; | |
1474 | unsigned int capture_ipr; /* interrupt acknowledge mask */ | |
1475 | unsigned int capture_inte; /* interrupt enable mask */ | |
1476 | unsigned int capture_ba_reg; /* buffer address register */ | |
1477 | unsigned int capture_bs_reg; /* buffer size register */ | |
1478 | unsigned int capture_idx_reg; /* buffer index register */ | |
1479 | unsigned int capture_cr_val; /* control value */ | |
1480 | unsigned int capture_cr_val2; /* control value2 (for audigy) */ | |
1481 | unsigned int capture_bs_val; /* buffer size value */ | |
1482 | unsigned int capture_bufsize; /* buffer size in bytes */ | |
1483 | }; | |
1484 | ||
eb4698f3 | 1485 | struct snd_emu10k1_pcm_mixer { |
1da177e4 LT |
1486 | /* mono, left, right x 8 sends (4 on emu10k1) */ |
1487 | unsigned char send_routing[3][8]; | |
1488 | unsigned char send_volume[3][8]; | |
bcdbd3b7 OB |
1489 | // 0x8000 is neutral. The mixer code rescales it to 0xffff to maintain |
1490 | // backwards compatibility with user space. | |
1da177e4 | 1491 | unsigned short attn[3]; |
eb4698f3 TI |
1492 | struct snd_emu10k1_pcm *epcm; |
1493 | }; | |
1da177e4 LT |
1494 | |
1495 | #define snd_emu10k1_compose_send_routing(route) \ | |
1496 | ((route[0] | (route[1] << 4) | (route[2] << 8) | (route[3] << 12)) << 16) | |
1497 | ||
1498 | #define snd_emu10k1_compose_audigy_fxrt1(route) \ | |
1499 | ((unsigned int)route[0] | ((unsigned int)route[1] << 8) | ((unsigned int)route[2] << 16) | ((unsigned int)route[3] << 24)) | |
1500 | ||
1501 | #define snd_emu10k1_compose_audigy_fxrt2(route) \ | |
1502 | ((unsigned int)route[4] | ((unsigned int)route[5] << 8) | ((unsigned int)route[6] << 16) | ((unsigned int)route[7] << 24)) | |
1503 | ||
51d652f4 OB |
1504 | #define snd_emu10k1_compose_audigy_sendamounts(vol) \ |
1505 | (((unsigned int)vol[4] << 24) | ((unsigned int)vol[5] << 16) | ((unsigned int)vol[6] << 8) | (unsigned int)vol[7]) | |
1506 | ||
eb4698f3 TI |
1507 | struct snd_emu10k1_memblk { |
1508 | struct snd_util_memblk mem; | |
1da177e4 LT |
1509 | /* private part */ |
1510 | int first_page, last_page, pages, mapped_page; | |
1511 | unsigned int map_locked; | |
1512 | struct list_head mapped_link; | |
1513 | struct list_head mapped_order_link; | |
eb4698f3 | 1514 | }; |
1da177e4 LT |
1515 | |
1516 | #define snd_emu10k1_memblk_offset(blk) (((blk)->mapped_page << PAGE_SHIFT) | ((blk)->mem.offset & (PAGE_SIZE - 1))) | |
1517 | ||
1518 | #define EMU10K1_MAX_TRAM_BLOCKS_PER_CODE 16 | |
1519 | ||
eb4698f3 | 1520 | struct snd_emu10k1_fx8010_ctl { |
1da177e4 LT |
1521 | struct list_head list; /* list link container */ |
1522 | unsigned int vcount; | |
1523 | unsigned int count; /* count of GPR (1..16) */ | |
1524 | unsigned short gpr[32]; /* GPR number(s) */ | |
1298bc97 OB |
1525 | int value[32]; |
1526 | int min; /* minimum range */ | |
1527 | int max; /* maximum range */ | |
1da177e4 | 1528 | unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */ |
eb4698f3 TI |
1529 | struct snd_kcontrol *kcontrol; |
1530 | }; | |
1da177e4 | 1531 | |
eb4698f3 | 1532 | typedef void (snd_fx8010_irq_handler_t)(struct snd_emu10k1 *emu, void *private_data); |
1da177e4 | 1533 | |
eb4698f3 TI |
1534 | struct snd_emu10k1_fx8010_irq { |
1535 | struct snd_emu10k1_fx8010_irq *next; | |
1da177e4 LT |
1536 | snd_fx8010_irq_handler_t *handler; |
1537 | unsigned short gpr_running; | |
1538 | void *private_data; | |
eb4698f3 | 1539 | }; |
1da177e4 | 1540 | |
eb4698f3 | 1541 | struct snd_emu10k1_fx8010_pcm { |
1da177e4 LT |
1542 | unsigned int valid: 1, |
1543 | opened: 1, | |
1544 | active: 1; | |
1545 | unsigned int channels; /* 16-bit channels count */ | |
1546 | unsigned int tram_start; /* initial ring buffer position in TRAM (in samples) */ | |
1547 | unsigned int buffer_size; /* count of buffered samples */ | |
1548 | unsigned short gpr_size; /* GPR containing size of ring buffer in samples (host) */ | |
1549 | unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */ | |
1550 | unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */ | |
1551 | unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */ | |
1552 | unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */ | |
1553 | unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */ | |
1554 | unsigned char etram[32]; /* external TRAM address & data */ | |
eb4698f3 | 1555 | struct snd_pcm_indirect pcm_rec; |
1da177e4 LT |
1556 | unsigned int tram_pos; |
1557 | unsigned int tram_shift; | |
057666b6 | 1558 | struct snd_emu10k1_fx8010_irq irq; |
eb4698f3 | 1559 | }; |
1da177e4 | 1560 | |
eb4698f3 | 1561 | struct snd_emu10k1_fx8010 { |
e81995a8 OB |
1562 | unsigned short extin_mask; /* used external inputs (bitmask); not used for Audigy */ |
1563 | unsigned short extout_mask; /* used external outputs (bitmask); not used for Audigy */ | |
1da177e4 LT |
1564 | unsigned int itram_size; /* internal TRAM size in samples */ |
1565 | struct snd_dma_buffer etram_pages; /* external TRAM pages and size */ | |
1566 | unsigned int dbg; /* FX debugger register */ | |
1567 | unsigned char name[128]; | |
1568 | int gpr_size; /* size of allocated GPR controls */ | |
1569 | int gpr_count; /* count of used kcontrols */ | |
1570 | struct list_head gpr_ctl; /* GPR controls */ | |
62932df8 | 1571 | struct mutex lock; |
eb4698f3 | 1572 | struct snd_emu10k1_fx8010_pcm pcm[8]; |
1da177e4 | 1573 | spinlock_t irq_lock; |
eb4698f3 TI |
1574 | struct snd_emu10k1_fx8010_irq *irq_handlers; |
1575 | }; | |
1da177e4 | 1576 | |
eb4698f3 TI |
1577 | struct snd_emu10k1_midi { |
1578 | struct snd_emu10k1 *emu; | |
1579 | struct snd_rawmidi *rmidi; | |
1580 | struct snd_rawmidi_substream *substream_input; | |
1581 | struct snd_rawmidi_substream *substream_output; | |
1da177e4 LT |
1582 | unsigned int midi_mode; |
1583 | spinlock_t input_lock; | |
1584 | spinlock_t output_lock; | |
1585 | spinlock_t open_lock; | |
1586 | int tx_enable, rx_enable; | |
1587 | int port; | |
1588 | int ipr_tx, ipr_rx; | |
eb4698f3 TI |
1589 | void (*interrupt)(struct snd_emu10k1 *emu, unsigned int status); |
1590 | }; | |
1da177e4 | 1591 | |
3839e4f1 TI |
1592 | enum { |
1593 | EMU_MODEL_SB, | |
1594 | EMU_MODEL_EMU1010, | |
1595 | EMU_MODEL_EMU1010B, | |
1596 | EMU_MODEL_EMU1616, | |
1597 | EMU_MODEL_EMU0404, | |
1598 | }; | |
1599 | ||
a869057c OB |
1600 | // Chip-o-logy: |
1601 | // - All SB Live! cards use EMU10K1 chips | |
1602 | // - All SB Audigy cards use CA* chips, termed "emu10k2" by the driver | |
1603 | // - Original Audigy uses CA0100 "Alice" | |
1604 | // - Audigy 2 uses CA0102/CA10200 "Alice2" | |
1605 | // - Has an interface for CA0151 (P16V) "Alice3" | |
1606 | // - Audigy 2 Value uses CA0108/CA10300 "Tina" | |
1607 | // - Approximately a CA0102 with an on-chip CA0151 (P17V) | |
1608 | // - Audigy 2 ZS NB uses CA0109 "Tina2" | |
1609 | // - Cardbus version of CA0108 | |
eb4698f3 | 1610 | struct snd_emu_chip_details { |
1da177e4 LT |
1611 | u32 vendor; |
1612 | u32 device; | |
1613 | u32 subsystem; | |
bdaed502 | 1614 | unsigned char revision; |
9b00a1e9 OB |
1615 | unsigned char emu_model; /* EMU model type */ |
1616 | unsigned int emu10k1_chip:1; /* Original SB Live. Not SB Live 24bit. */ | |
1617 | /* Redundant with emu10k2_chip being unset. */ | |
1618 | unsigned int emu10k2_chip:1; /* Audigy 1 or Audigy 2. */ | |
1619 | unsigned int ca0102_chip:1; /* Audigy 1 or Audigy 2. Not SB Audigy 2 Value. */ | |
1620 | /* Redundant with ca0108_chip being unset. */ | |
1621 | unsigned int ca0108_chip:1; /* Audigy 2 Value */ | |
1622 | unsigned int ca_cardbus_chip:1; /* Audigy 2 ZS Notebook */ | |
1623 | unsigned int ca0151_chip:1; /* P16V */ | |
6f3609f8 | 1624 | unsigned int spk20:1; /* Stereo only */ |
9b00a1e9 | 1625 | unsigned int spk71:1; /* Has 7.1 speakers */ |
6f3609f8 | 1626 | unsigned int no_adat:1; /* Has no ADAT, only SPDIF */ |
9b00a1e9 OB |
1627 | unsigned int sblive51:1; /* SBLive! 5.1 - extout 0x11 -> center, 0x12 -> lfe */ |
1628 | unsigned int spdif_bug:1; /* Has Spdif phasing bug */ | |
1629 | unsigned int ac97_chip:2; /* Has an AC97 chip: 1 = mandatory, 2 = optional */ | |
1630 | unsigned int ecard:1; /* APS EEPROM */ | |
1631 | unsigned int spi_dac:1; /* SPI interface for DAC; requires ca0108_chip */ | |
1632 | unsigned int i2c_adc:1; /* I2C interface for ADC; requires ca0108_chip */ | |
1633 | unsigned int adc_1361t:1; /* Use Philips 1361T ADC */ | |
1634 | unsigned int invert_shared_spdif:1; /* analog/digital switch inverted */ | |
aec72e0a TI |
1635 | const char *driver; |
1636 | const char *name; | |
1637 | const char *id; /* for backward compatibility - can be NULL if not needed */ | |
eb4698f3 | 1638 | }; |
1da177e4 | 1639 | |
9f4bd5dd JCD |
1640 | struct snd_emu1010 { |
1641 | unsigned int output_source[64]; | |
1642 | unsigned int input_source[64]; | |
9148cc50 JCD |
1643 | unsigned int adc_pads; /* bit mask */ |
1644 | unsigned int dac_pads; /* bit mask */ | |
b0dbdaea | 1645 | unsigned int internal_clock; /* 44100 or 48000 */ |
f93abe51 JCD |
1646 | unsigned int optical_in; /* 0:SPDIF, 1:ADAT */ |
1647 | unsigned int optical_out; /* 0:SPDIF, 1:ADAT */ | |
aeaa6203 TI |
1648 | struct delayed_work firmware_work; |
1649 | u32 last_reg; | |
9f4bd5dd JCD |
1650 | }; |
1651 | ||
eb4698f3 | 1652 | struct snd_emu10k1 { |
1da177e4 LT |
1653 | int irq; |
1654 | ||
1655 | unsigned long port; /* I/O port number */ | |
2b637da5 | 1656 | unsigned int tos_link: 1, /* tos link detected */ |
09668b44 TI |
1657 | rear_ac97: 1, /* rear channels are on AC'97 */ |
1658 | enable_ir: 1; | |
f7ba7fc6 | 1659 | unsigned int support_tlv :1; |
eb4698f3 TI |
1660 | /* Contains profile of card capabilities */ |
1661 | const struct snd_emu_chip_details *card_capabilities; | |
1da177e4 LT |
1662 | unsigned int audigy; /* is Audigy? */ |
1663 | unsigned int revision; /* chip revision */ | |
1664 | unsigned int serial; /* serial number */ | |
1665 | unsigned short model; /* subsystem id */ | |
1da177e4 | 1666 | unsigned int ecard_ctrl; /* ecard control bits */ |
7241ea55 | 1667 | unsigned int address_mode; /* address mode */ |
1da177e4 | 1668 | unsigned long dma_mask; /* PCI DMA mask */ |
04f8773a | 1669 | bool iommu_workaround; /* IOMMU workaround needed */ |
56385a12 | 1670 | unsigned int delay_pcm_irq; /* in samples */ |
1da177e4 LT |
1671 | int max_cache_pages; /* max memory size / PAGE_SIZE */ |
1672 | struct snd_dma_buffer silent_page; /* silent page */ | |
1673 | struct snd_dma_buffer ptb_pages; /* page table pages */ | |
1674 | struct snd_dma_device p16v_dma_dev; | |
79e8b218 | 1675 | struct snd_dma_buffer *p16v_buffer; |
1da177e4 | 1676 | |
eb4698f3 | 1677 | struct snd_util_memhdr *memhdr; /* page allocation list */ |
1da177e4 LT |
1678 | |
1679 | struct list_head mapped_link_head; | |
1680 | struct list_head mapped_order_link_head; | |
1681 | void **page_ptr_table; | |
1682 | unsigned long *page_addr_table; | |
1683 | spinlock_t memblk_lock; | |
1684 | ||
1685 | unsigned int spdif_bits[3]; /* s/pdif out setup */ | |
184c1e2c JCD |
1686 | unsigned int i2c_capture_source; |
1687 | u8 i2c_capture_volume[4][2]; | |
1da177e4 | 1688 | |
eb4698f3 | 1689 | struct snd_emu10k1_fx8010 fx8010; /* FX8010 info */ |
1da177e4 LT |
1690 | int gpr_base; |
1691 | ||
eb4698f3 | 1692 | struct snd_ac97 *ac97; |
1da177e4 LT |
1693 | |
1694 | struct pci_dev *pci; | |
eb4698f3 TI |
1695 | struct snd_card *card; |
1696 | struct snd_pcm *pcm; | |
1697 | struct snd_pcm *pcm_mic; | |
1698 | struct snd_pcm *pcm_efx; | |
09668b44 | 1699 | struct snd_pcm *pcm_multi; |
eb4698f3 | 1700 | struct snd_pcm *pcm_p16v; |
1da177e4 LT |
1701 | |
1702 | spinlock_t synth_lock; | |
1703 | void *synth; | |
eb4698f3 | 1704 | int (*get_synth_voice)(struct snd_emu10k1 *emu); |
1da177e4 | 1705 | |
a869057c OB |
1706 | spinlock_t reg_lock; // high-level driver lock |
1707 | spinlock_t emu_lock; // low-level i/o lock | |
1708 | spinlock_t voice_lock; // voice allocator lock | |
c94fa4c9 JCD |
1709 | spinlock_t spi_lock; /* serialises access to spi port */ |
1710 | spinlock_t i2c_lock; /* serialises access to i2c port */ | |
1da177e4 | 1711 | |
eb4698f3 | 1712 | struct snd_emu10k1_voice voices[NUM_G]; |
1da177e4 | 1713 | int p16v_device_offset; |
6e4abc40 | 1714 | u32 p16v_capture_source; |
f927c8fc | 1715 | u32 p16v_capture_channel; |
9f4bd5dd | 1716 | struct snd_emu1010 emu1010; |
eb4698f3 TI |
1717 | struct snd_emu10k1_pcm_mixer pcm_mixer[32]; |
1718 | struct snd_emu10k1_pcm_mixer efx_pcm_mixer[NUM_EFX_PLAYBACK]; | |
1719 | struct snd_kcontrol *ctl_send_routing; | |
1720 | struct snd_kcontrol *ctl_send_volume; | |
1721 | struct snd_kcontrol *ctl_attn; | |
1722 | struct snd_kcontrol *ctl_efx_send_routing; | |
1723 | struct snd_kcontrol *ctl_efx_send_volume; | |
1724 | struct snd_kcontrol *ctl_efx_attn; | |
1725 | ||
1726 | void (*hwvol_interrupt)(struct snd_emu10k1 *emu, unsigned int status); | |
1727 | void (*capture_interrupt)(struct snd_emu10k1 *emu, unsigned int status); | |
1728 | void (*capture_mic_interrupt)(struct snd_emu10k1 *emu, unsigned int status); | |
1729 | void (*capture_efx_interrupt)(struct snd_emu10k1 *emu, unsigned int status); | |
1730 | void (*spdif_interrupt)(struct snd_emu10k1 *emu, unsigned int status); | |
1731 | void (*dsp_interrupt)(struct snd_emu10k1 *emu); | |
02a0d9c2 | 1732 | void (*p16v_interrupt)(struct snd_emu10k1 *emu); |
eb4698f3 TI |
1733 | |
1734 | struct snd_pcm_substream *pcm_capture_substream; | |
1735 | struct snd_pcm_substream *pcm_capture_mic_substream; | |
1736 | struct snd_pcm_substream *pcm_capture_efx_substream; | |
eb4698f3 TI |
1737 | |
1738 | struct snd_timer *timer; | |
1739 | ||
1740 | struct snd_emu10k1_midi midi; | |
1741 | struct snd_emu10k1_midi midi2; /* for audigy */ | |
1da177e4 LT |
1742 | |
1743 | unsigned int efx_voices_mask[2]; | |
1744 | unsigned int next_free_voice; | |
09668b44 | 1745 | |
b209c4df | 1746 | const struct firmware *firmware; |
e08b34e8 | 1747 | const struct firmware *dock_fw; |
b209c4df | 1748 | |
c7561cd8 | 1749 | #ifdef CONFIG_PM_SLEEP |
09668b44 TI |
1750 | unsigned int *saved_ptr; |
1751 | unsigned int *saved_gpr; | |
1752 | unsigned int *tram_val_saved; | |
1753 | unsigned int *tram_addr_saved; | |
1754 | unsigned int *saved_icode; | |
1755 | unsigned int *p16v_saved; | |
1756 | unsigned int saved_a_iocfg, saved_hcfg; | |
4f86f120 | 1757 | bool suspend; |
09668b44 TI |
1758 | #endif |
1759 | ||
1da177e4 LT |
1760 | }; |
1761 | ||
eb4698f3 | 1762 | int snd_emu10k1_create(struct snd_card *card, |
1da177e4 LT |
1763 | struct pci_dev *pci, |
1764 | unsigned short extin_mask, | |
1765 | unsigned short extout_mask, | |
1766 | long max_cache_bytes, | |
1767 | int enable_ir, | |
79e8b218 | 1768 | uint subsystem); |
eb4698f3 | 1769 | |
bb814c39 LPC |
1770 | int snd_emu10k1_pcm(struct snd_emu10k1 *emu, int device); |
1771 | int snd_emu10k1_pcm_mic(struct snd_emu10k1 *emu, int device); | |
1772 | int snd_emu10k1_pcm_efx(struct snd_emu10k1 *emu, int device); | |
1773 | int snd_p16v_pcm(struct snd_emu10k1 *emu, int device); | |
eb4698f3 | 1774 | int snd_p16v_mixer(struct snd_emu10k1 * emu); |
bb814c39 LPC |
1775 | int snd_emu10k1_pcm_multi(struct snd_emu10k1 *emu, int device); |
1776 | int snd_emu10k1_fx8010_pcm(struct snd_emu10k1 *emu, int device); | |
eb4698f3 TI |
1777 | int snd_emu10k1_mixer(struct snd_emu10k1 * emu, int pcm_device, int multi_device); |
1778 | int snd_emu10k1_timer(struct snd_emu10k1 * emu, int device); | |
bb814c39 | 1779 | int snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device); |
1da177e4 | 1780 | |
7d12e780 | 1781 | irqreturn_t snd_emu10k1_interrupt(int irq, void *dev_id); |
1da177e4 | 1782 | |
eb4698f3 TI |
1783 | void snd_emu10k1_voice_init(struct snd_emu10k1 * emu, int voice); |
1784 | int snd_emu10k1_init_efx(struct snd_emu10k1 *emu); | |
1785 | void snd_emu10k1_free_efx(struct snd_emu10k1 *emu); | |
1786 | int snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 *emu, u32 size); | |
09668b44 | 1787 | int snd_emu10k1_done(struct snd_emu10k1 * emu); |
1da177e4 LT |
1788 | |
1789 | /* I/O functions */ | |
eb4698f3 TI |
1790 | unsigned int snd_emu10k1_ptr_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn); |
1791 | void snd_emu10k1_ptr_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data); | |
1792 | unsigned int snd_emu10k1_ptr20_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn); | |
1793 | void snd_emu10k1_ptr20_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data); | |
27fe864e | 1794 | int snd_emu10k1_spi_write(struct snd_emu10k1 * emu, unsigned int data); |
184c1e2c | 1795 | int snd_emu10k1_i2c_write(struct snd_emu10k1 *emu, u32 reg, u32 value); |
10f212bd OB |
1796 | void snd_emu1010_fpga_write(struct snd_emu10k1 *emu, u32 reg, u32 value); |
1797 | void snd_emu1010_fpga_read(struct snd_emu10k1 *emu, u32 reg, u32 *value); | |
1798 | void snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 *emu, u32 dst, u32 src); | |
eb4698f3 TI |
1799 | unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc); |
1800 | void snd_emu10k1_intr_enable(struct snd_emu10k1 *emu, unsigned int intrenb); | |
1801 | void snd_emu10k1_intr_disable(struct snd_emu10k1 *emu, unsigned int intrenb); | |
1802 | void snd_emu10k1_voice_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum); | |
1803 | void snd_emu10k1_voice_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum); | |
1804 | void snd_emu10k1_voice_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum); | |
1805 | void snd_emu10k1_voice_half_loop_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum); | |
1806 | void snd_emu10k1_voice_half_loop_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum); | |
1807 | void snd_emu10k1_voice_half_loop_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum); | |
a61c695a | 1808 | #if 0 |
eb4698f3 TI |
1809 | void snd_emu10k1_voice_set_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum); |
1810 | void snd_emu10k1_voice_clear_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum); | |
a61c695a | 1811 | #endif |
eb4698f3 TI |
1812 | void snd_emu10k1_wait(struct snd_emu10k1 *emu, unsigned int wait); |
1813 | static inline unsigned int snd_emu10k1_wc(struct snd_emu10k1 *emu) { return (inl(emu->port + WC) >> 6) & 0xfffff; } | |
1814 | unsigned short snd_emu10k1_ac97_read(struct snd_ac97 *ac97, unsigned short reg); | |
1815 | void snd_emu10k1_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short data); | |
1da177e4 | 1816 | |
c7561cd8 | 1817 | #ifdef CONFIG_PM_SLEEP |
09668b44 TI |
1818 | void snd_emu10k1_suspend_regs(struct snd_emu10k1 *emu); |
1819 | void snd_emu10k1_resume_init(struct snd_emu10k1 *emu); | |
1820 | void snd_emu10k1_resume_regs(struct snd_emu10k1 *emu); | |
1821 | int snd_emu10k1_efx_alloc_pm_buffer(struct snd_emu10k1 *emu); | |
1822 | void snd_emu10k1_efx_free_pm_buffer(struct snd_emu10k1 *emu); | |
1823 | void snd_emu10k1_efx_suspend(struct snd_emu10k1 *emu); | |
1824 | void snd_emu10k1_efx_resume(struct snd_emu10k1 *emu); | |
1825 | int snd_p16v_alloc_pm_buffer(struct snd_emu10k1 *emu); | |
1826 | void snd_p16v_free_pm_buffer(struct snd_emu10k1 *emu); | |
1827 | void snd_p16v_suspend(struct snd_emu10k1 *emu); | |
1828 | void snd_p16v_resume(struct snd_emu10k1 *emu); | |
1829 | #endif | |
1830 | ||
1da177e4 | 1831 | /* memory allocation */ |
eb4698f3 TI |
1832 | struct snd_util_memblk *snd_emu10k1_alloc_pages(struct snd_emu10k1 *emu, struct snd_pcm_substream *substream); |
1833 | int snd_emu10k1_free_pages(struct snd_emu10k1 *emu, struct snd_util_memblk *blk); | |
04f8773a MS |
1834 | int snd_emu10k1_alloc_pages_maybe_wider(struct snd_emu10k1 *emu, size_t size, |
1835 | struct snd_dma_buffer *dmab); | |
eb4698f3 TI |
1836 | struct snd_util_memblk *snd_emu10k1_synth_alloc(struct snd_emu10k1 *emu, unsigned int size); |
1837 | int snd_emu10k1_synth_free(struct snd_emu10k1 *emu, struct snd_util_memblk *blk); | |
1838 | int snd_emu10k1_synth_bzero(struct snd_emu10k1 *emu, struct snd_util_memblk *blk, int offset, int size); | |
1839 | int snd_emu10k1_synth_copy_from_user(struct snd_emu10k1 *emu, struct snd_util_memblk *blk, int offset, const char __user *data, int size); | |
1840 | int snd_emu10k1_memblk_map(struct snd_emu10k1 *emu, struct snd_emu10k1_memblk *blk); | |
1da177e4 LT |
1841 | |
1842 | /* voice allocation */ | |
eb4698f3 TI |
1843 | int snd_emu10k1_voice_alloc(struct snd_emu10k1 *emu, int type, int pair, struct snd_emu10k1_voice **rvoice); |
1844 | int snd_emu10k1_voice_free(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice); | |
1da177e4 LT |
1845 | |
1846 | /* MIDI uart */ | |
eb4698f3 TI |
1847 | int snd_emu10k1_midi(struct snd_emu10k1 * emu); |
1848 | int snd_emu10k1_audigy_midi(struct snd_emu10k1 * emu); | |
1da177e4 LT |
1849 | |
1850 | /* proc interface */ | |
eb4698f3 | 1851 | int snd_emu10k1_proc_init(struct snd_emu10k1 * emu); |
1da177e4 LT |
1852 | |
1853 | /* fx8010 irq handler */ | |
eb4698f3 | 1854 | int snd_emu10k1_fx8010_register_irq_handler(struct snd_emu10k1 *emu, |
1da177e4 LT |
1855 | snd_fx8010_irq_handler_t *handler, |
1856 | unsigned char gpr_running, | |
1857 | void *private_data, | |
057666b6 | 1858 | struct snd_emu10k1_fx8010_irq *irq); |
eb4698f3 TI |
1859 | int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu, |
1860 | struct snd_emu10k1_fx8010_irq *irq); | |
1da177e4 | 1861 | |
1da177e4 | 1862 | #endif /* __SOUND_EMU10K1_H */ |