[linux-2.6-block.git] / include / sound / designware_i2s.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * Copyright (ST) 2012 Rajeev Kumar (rajeevkumar.linux@gmail.com)
 */

#ifndef __SOUND_DESIGNWARE_I2S_H
#define __SOUND_DESIGNWARE_I2S_H

#include <linux/dmaengine.h>
#include <linux/types.h>

/*
 * struct i2s_clk_config_data - represent i2s clk configuration data
 * @chan_nr: number of channel
 * @data_width: number of bits per sample (8/16/24/32 bit)
 * @sample_rate: sampling frequency (8Khz, 16Khz, 32Khz, 44Khz, 48Khz)
 */
struct i2s_clk_config_data {
	int chan_nr;
	u32 data_width;
	u32 sample_rate;
};

struct i2s_platform_data {
	#define DWC_I2S_PLAY	(1 << 0)
	#define DWC_I2S_RECORD	(1 << 1)
	#define DW_I2S_SLAVE	(1 << 2)
	#define DW_I2S_MASTER	(1 << 3)
	unsigned int cap;
	int channel;
	u32 snd_fmts;
	u32 snd_rates;

	#define DW_I2S_QUIRK_COMP_REG_OFFSET	(1 << 0)
	#define DW_I2S_QUIRK_COMP_PARAM1	(1 << 1)
	#define DW_I2S_QUIRK_16BIT_IDX_OVERRIDE (1 << 2)
	unsigned int quirks;
	unsigned int i2s_reg_comp1;
	unsigned int i2s_reg_comp2;

	void *play_dma_data;
	void *capture_dma_data;
	bool (*filter)(struct dma_chan *chan, void *slave);
	int (*i2s_clk_cfg)(struct i2s_clk_config_data *config);
};

struct i2s_dma_data {
	void *data;
	dma_addr_t addr;
	u32 max_burst;
	enum dma_slave_buswidth addr_width;
	bool (*filter)(struct dma_chan *chan, void *slave);
};

/* I2S DMA registers */
#define I2S_RXDMA		0x01C0
#define I2S_TXDMA		0x01C8

#define TWO_CHANNEL_SUPPORT	2	/* up to 2.0 */
#define FOUR_CHANNEL_SUPPORT	4	/* up to 3.1 */
#define SIX_CHANNEL_SUPPORT	6	/* up to 5.1 */
#define EIGHT_CHANNEL_SUPPORT	8	/* up to 7.1 */

#endif /*  __SOUND_DESIGNWARE_I2S_H */
Commit	Line	Data
1a59d1b8	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
3a9cf8ef	2	/*
9d7dd6cd	3	* Copyright (ST) 2012 Rajeev Kumar (rajeevkumar.linux@gmail.com)
3a9cf8ef RK	4	*/
	5
	6	#ifndef __SOUND_DESIGNWARE_I2S_H
	7	#define __SOUND_DESIGNWARE_I2S_H
	8
	9	#include <linux/dmaengine.h>
	10	#include <linux/types.h>
	11
	12	/*
	13	* struct i2s_clk_config_data - represent i2s clk configuration data
	14	* @chan_nr: number of channel
	15	* @data_width: number of bits per sample (8/16/24/32 bit)
	16	* @sample_rate: sampling frequency (8Khz, 16Khz, 32Khz, 44Khz, 48Khz)
	17	*/
	18	struct i2s_clk_config_data {
	19	int chan_nr;
	20	u32 data_width;
	21	u32 sample_rate;
	22	};
	23
	24	struct i2s_platform_data {
	25	#define DWC_I2S_PLAY (1 << 0)
	26	#define DWC_I2S_RECORD (1 << 1)
1d957d86 MSB	27	#define DW_I2S_SLAVE (1 << 2)
1d957d86 MSB	28	#define DW_I2S_MASTER (1 << 3)
3a9cf8ef RK	29	unsigned int cap;
	30	int channel;
	31	u32 snd_fmts;
	32	u32 snd_rates;
	33
e164835a	34	#define DW_I2S_QUIRK_COMP_REG_OFFSET (1 << 0)
a242cac1	35	#define DW_I2S_QUIRK_COMP_PARAM1 (1 << 1)
286345ee	36	#define DW_I2S_QUIRK_16BIT_IDX_OVERRIDE (1 << 2)
e164835a MSB	37	unsigned int quirks;
	38	unsigned int i2s_reg_comp1;
	39	unsigned int i2s_reg_comp2;
	40
3a9cf8ef RK	41	void *play_dma_data;
	42	void *capture_dma_data;
	43	bool (filter)(struct dma_chan chan, void *slave);
	44	int (i2s_clk_cfg)(struct i2s_clk_config_data config);
	45	};
	46
	47	struct i2s_dma_data {
	48	void *data;
	49	dma_addr_t addr;
	50	u32 max_burst;
	51	enum dma_slave_buswidth addr_width;
	52	bool (filter)(struct dma_chan chan, void *slave);
	53	};
	54
	55	/* I2S DMA registers */
	56	#define I2S_RXDMA 0x01C0
	57	#define I2S_TXDMA 0x01C8
	58
	59	#define TWO_CHANNEL_SUPPORT 2 /* up to 2.0 */
	60	#define FOUR_CHANNEL_SUPPORT 4 /* up to 3.1 */
	61	#define SIX_CHANNEL_SUPPORT 6 /* up to 5.1 */
	62	#define EIGHT_CHANNEL_SUPPORT 8 /* up to 7.1 */
	63
	64	#endif /* __SOUND_DESIGNWARE_I2S_H */