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6450ef55 DR |
1 | /* SPDX-License-Identifier: GPL-2.0 |
2 | * | |
3 | * linux/sound/cs35l41.h -- Platform data for CS35L41 | |
4 | * | |
5 | * Copyright (c) 2017-2021 Cirrus Logic Inc. | |
6 | * | |
7 | * Author: David Rhodes <david.rhodes@cirrus.com> | |
8 | */ | |
9 | ||
10 | #ifndef __CS35L41_H | |
11 | #define __CS35L41_H | |
12 | ||
a87d4222 | 13 | #include <linux/regmap.h> |
0db99577 | 14 | #include <linux/firmware/cirrus/cs_dsp.h> |
a87d4222 LT |
15 | |
16 | #define CS35L41_FIRSTREG 0x00000000 | |
17 | #define CS35L41_LASTREG 0x03804FE8 | |
18 | #define CS35L41_DEVID 0x00000000 | |
19 | #define CS35L41_REVID 0x00000004 | |
20 | #define CS35L41_FABID 0x00000008 | |
21 | #define CS35L41_RELID 0x0000000C | |
22 | #define CS35L41_OTPID 0x00000010 | |
23 | #define CS35L41_SFT_RESET 0x00000020 | |
24 | #define CS35L41_TEST_KEY_CTL 0x00000040 | |
25 | #define CS35L41_USER_KEY_CTL 0x00000044 | |
26 | #define CS35L41_OTP_MEM0 0x00000400 | |
27 | #define CS35L41_OTP_MEM31 0x0000047C | |
28 | #define CS35L41_OTP_CTRL0 0x00000500 | |
29 | #define CS35L41_OTP_CTRL1 0x00000504 | |
30 | #define CS35L41_OTP_CTRL3 0x00000508 | |
31 | #define CS35L41_OTP_CTRL4 0x0000050C | |
32 | #define CS35L41_OTP_CTRL5 0x00000510 | |
33 | #define CS35L41_OTP_CTRL6 0x00000514 | |
34 | #define CS35L41_OTP_CTRL7 0x00000518 | |
35 | #define CS35L41_OTP_CTRL8 0x0000051C | |
36 | #define CS35L41_PWR_CTRL1 0x00002014 | |
37 | #define CS35L41_PWR_CTRL2 0x00002018 | |
38 | #define CS35L41_PWR_CTRL3 0x0000201C | |
39 | #define CS35L41_CTRL_OVRRIDE 0x00002020 | |
40 | #define CS35L41_AMP_OUT_MUTE 0x00002024 | |
41 | #define CS35L41_PROTECT_REL_ERR_IGN 0x00002034 | |
42 | #define CS35L41_GPIO_PAD_CONTROL 0x0000242C | |
43 | #define CS35L41_JTAG_CONTROL 0x00002438 | |
f517ba49 CK |
44 | #define CS35L41_PWRMGT_CTL 0x00002900 |
45 | #define CS35L41_WAKESRC_CTL 0x00002904 | |
46 | #define CS35L41_PWRMGT_STS 0x00002908 | |
a87d4222 LT |
47 | #define CS35L41_PLL_CLK_CTRL 0x00002C04 |
48 | #define CS35L41_DSP_CLK_CTRL 0x00002C08 | |
49 | #define CS35L41_GLOBAL_CLK_CTRL 0x00002C0C | |
50 | #define CS35L41_DATA_FS_SEL 0x00002C10 | |
51 | #define CS35L41_TST_FS_MON0 0x00002D10 | |
52 | #define CS35L41_MDSYNC_EN 0x00003400 | |
53 | #define CS35L41_MDSYNC_TX_ID 0x00003408 | |
54 | #define CS35L41_MDSYNC_PWR_CTRL 0x0000340C | |
55 | #define CS35L41_MDSYNC_DATA_TX 0x00003410 | |
56 | #define CS35L41_MDSYNC_TX_STATUS 0x00003414 | |
57 | #define CS35L41_MDSYNC_DATA_RX 0x0000341C | |
58 | #define CS35L41_MDSYNC_RX_STATUS 0x00003420 | |
59 | #define CS35L41_MDSYNC_ERR_STATUS 0x00003424 | |
60 | #define CS35L41_MDSYNC_SYNC_PTE2 0x00003528 | |
61 | #define CS35L41_MDSYNC_SYNC_PTE3 0x0000352C | |
62 | #define CS35L41_MDSYNC_SYNC_MSM_STATUS 0x0000353C | |
63 | #define CS35L41_BSTCVRT_VCTRL1 0x00003800 | |
64 | #define CS35L41_BSTCVRT_VCTRL2 0x00003804 | |
65 | #define CS35L41_BSTCVRT_PEAK_CUR 0x00003808 | |
66 | #define CS35L41_BSTCVRT_SFT_RAMP 0x0000380C | |
67 | #define CS35L41_BSTCVRT_COEFF 0x00003810 | |
68 | #define CS35L41_BSTCVRT_SLOPE_LBST 0x00003814 | |
69 | #define CS35L41_BSTCVRT_SW_FREQ 0x00003818 | |
70 | #define CS35L41_BSTCVRT_DCM_CTRL 0x0000381C | |
71 | #define CS35L41_BSTCVRT_DCM_MODE_FORCE 0x00003820 | |
72 | #define CS35L41_BSTCVRT_OVERVOLT_CTRL 0x00003830 | |
73 | #define CS35L41_VI_VOL_POL 0x00004000 | |
74 | #define CS35L41_VIMON_SPKMON_RESYNC 0x00004100 | |
75 | #define CS35L41_DTEMP_WARN_THLD 0x00004220 | |
76 | #define CS35L41_DTEMP_CFG 0x00004224 | |
77 | #define CS35L41_DTEMP_EN 0x00004308 | |
78 | #define CS35L41_VPVBST_FS_SEL 0x00004400 | |
79 | #define CS35L41_SP_ENABLES 0x00004800 | |
80 | #define CS35L41_SP_RATE_CTRL 0x00004804 | |
81 | #define CS35L41_SP_FORMAT 0x00004808 | |
82 | #define CS35L41_SP_HIZ_CTRL 0x0000480C | |
83 | #define CS35L41_SP_FRAME_TX_SLOT 0x00004810 | |
84 | #define CS35L41_SP_FRAME_RX_SLOT 0x00004820 | |
85 | #define CS35L41_SP_TX_WL 0x00004830 | |
86 | #define CS35L41_SP_RX_WL 0x00004840 | |
87 | #define CS35L41_ASP_CONTROL4 0x00004854 | |
88 | #define CS35L41_DAC_PCM1_SRC 0x00004C00 | |
89 | #define CS35L41_ASP_TX1_SRC 0x00004C20 | |
90 | #define CS35L41_ASP_TX2_SRC 0x00004C24 | |
91 | #define CS35L41_ASP_TX3_SRC 0x00004C28 | |
92 | #define CS35L41_ASP_TX4_SRC 0x00004C2C | |
93 | #define CS35L41_DSP1_RX1_SRC 0x00004C40 | |
94 | #define CS35L41_DSP1_RX2_SRC 0x00004C44 | |
95 | #define CS35L41_DSP1_RX3_SRC 0x00004C48 | |
96 | #define CS35L41_DSP1_RX4_SRC 0x00004C4C | |
97 | #define CS35L41_DSP1_RX5_SRC 0x00004C50 | |
98 | #define CS35L41_DSP1_RX6_SRC 0x00004C54 | |
99 | #define CS35L41_DSP1_RX7_SRC 0x00004C58 | |
100 | #define CS35L41_DSP1_RX8_SRC 0x00004C5C | |
101 | #define CS35L41_NGATE1_SRC 0x00004C60 | |
102 | #define CS35L41_NGATE2_SRC 0x00004C64 | |
103 | #define CS35L41_AMP_DIG_VOL_CTRL 0x00006000 | |
104 | #define CS35L41_VPBR_CFG 0x00006404 | |
105 | #define CS35L41_VBBR_CFG 0x00006408 | |
106 | #define CS35L41_VPBR_STATUS 0x0000640C | |
107 | #define CS35L41_VBBR_STATUS 0x00006410 | |
108 | #define CS35L41_OVERTEMP_CFG 0x00006414 | |
109 | #define CS35L41_AMP_ERR_VOL 0x00006418 | |
110 | #define CS35L41_VOL_STATUS_TO_DSP 0x00006450 | |
111 | #define CS35L41_CLASSH_CFG 0x00006800 | |
112 | #define CS35L41_WKFET_CFG 0x00006804 | |
113 | #define CS35L41_NG_CFG 0x00006808 | |
114 | #define CS35L41_AMP_GAIN_CTRL 0x00006C04 | |
115 | #define CS35L41_DAC_MSM_CFG 0x00007400 | |
116 | #define CS35L41_IRQ1_CFG 0x00010000 | |
117 | #define CS35L41_IRQ1_STATUS 0x00010004 | |
118 | #define CS35L41_IRQ1_STATUS1 0x00010010 | |
119 | #define CS35L41_IRQ1_STATUS2 0x00010014 | |
120 | #define CS35L41_IRQ1_STATUS3 0x00010018 | |
121 | #define CS35L41_IRQ1_STATUS4 0x0001001C | |
122 | #define CS35L41_IRQ1_RAW_STATUS1 0x00010090 | |
123 | #define CS35L41_IRQ1_RAW_STATUS2 0x00010094 | |
124 | #define CS35L41_IRQ1_RAW_STATUS3 0x00010098 | |
125 | #define CS35L41_IRQ1_RAW_STATUS4 0x0001009C | |
126 | #define CS35L41_IRQ1_MASK1 0x00010110 | |
127 | #define CS35L41_IRQ1_MASK2 0x00010114 | |
128 | #define CS35L41_IRQ1_MASK3 0x00010118 | |
129 | #define CS35L41_IRQ1_MASK4 0x0001011C | |
130 | #define CS35L41_IRQ1_FRC1 0x00010190 | |
131 | #define CS35L41_IRQ1_FRC2 0x00010194 | |
132 | #define CS35L41_IRQ1_FRC3 0x00010198 | |
133 | #define CS35L41_IRQ1_FRC4 0x0001019C | |
134 | #define CS35L41_IRQ1_EDGE1 0x00010210 | |
135 | #define CS35L41_IRQ1_EDGE4 0x0001021C | |
136 | #define CS35L41_IRQ1_POL1 0x00010290 | |
137 | #define CS35L41_IRQ1_POL2 0x00010294 | |
138 | #define CS35L41_IRQ1_POL3 0x00010298 | |
139 | #define CS35L41_IRQ1_POL4 0x0001029C | |
140 | #define CS35L41_IRQ1_DB3 0x00010318 | |
141 | #define CS35L41_IRQ2_CFG 0x00010800 | |
142 | #define CS35L41_IRQ2_STATUS 0x00010804 | |
143 | #define CS35L41_IRQ2_STATUS1 0x00010810 | |
144 | #define CS35L41_IRQ2_STATUS2 0x00010814 | |
145 | #define CS35L41_IRQ2_STATUS3 0x00010818 | |
146 | #define CS35L41_IRQ2_STATUS4 0x0001081C | |
147 | #define CS35L41_IRQ2_RAW_STATUS1 0x00010890 | |
148 | #define CS35L41_IRQ2_RAW_STATUS2 0x00010894 | |
149 | #define CS35L41_IRQ2_RAW_STATUS3 0x00010898 | |
150 | #define CS35L41_IRQ2_RAW_STATUS4 0x0001089C | |
151 | #define CS35L41_IRQ2_MASK1 0x00010910 | |
152 | #define CS35L41_IRQ2_MASK2 0x00010914 | |
153 | #define CS35L41_IRQ2_MASK3 0x00010918 | |
154 | #define CS35L41_IRQ2_MASK4 0x0001091C | |
155 | #define CS35L41_IRQ2_FRC1 0x00010990 | |
156 | #define CS35L41_IRQ2_FRC2 0x00010994 | |
157 | #define CS35L41_IRQ2_FRC3 0x00010998 | |
158 | #define CS35L41_IRQ2_FRC4 0x0001099C | |
159 | #define CS35L41_IRQ2_EDGE1 0x00010A10 | |
160 | #define CS35L41_IRQ2_EDGE4 0x00010A1C | |
161 | #define CS35L41_IRQ2_POL1 0x00010A90 | |
162 | #define CS35L41_IRQ2_POL2 0x00010A94 | |
163 | #define CS35L41_IRQ2_POL3 0x00010A98 | |
164 | #define CS35L41_IRQ2_POL4 0x00010A9C | |
165 | #define CS35L41_IRQ2_DB3 0x00010B18 | |
166 | #define CS35L41_GPIO_STATUS1 0x00011000 | |
167 | #define CS35L41_GPIO1_CTRL1 0x00011008 | |
168 | #define CS35L41_GPIO2_CTRL1 0x0001100C | |
169 | #define CS35L41_MIXER_NGATE_CFG 0x00012000 | |
170 | #define CS35L41_MIXER_NGATE_CH1_CFG 0x00012004 | |
171 | #define CS35L41_MIXER_NGATE_CH2_CFG 0x00012008 | |
172 | #define CS35L41_DSP_MBOX_1 0x00013000 | |
173 | #define CS35L41_DSP_MBOX_2 0x00013004 | |
174 | #define CS35L41_DSP_MBOX_3 0x00013008 | |
175 | #define CS35L41_DSP_MBOX_4 0x0001300C | |
176 | #define CS35L41_DSP_MBOX_5 0x00013010 | |
177 | #define CS35L41_DSP_MBOX_6 0x00013014 | |
178 | #define CS35L41_DSP_MBOX_7 0x00013018 | |
179 | #define CS35L41_DSP_MBOX_8 0x0001301C | |
180 | #define CS35L41_DSP_VIRT1_MBOX_1 0x00013020 | |
181 | #define CS35L41_DSP_VIRT1_MBOX_2 0x00013024 | |
182 | #define CS35L41_DSP_VIRT1_MBOX_3 0x00013028 | |
183 | #define CS35L41_DSP_VIRT1_MBOX_4 0x0001302C | |
184 | #define CS35L41_DSP_VIRT1_MBOX_5 0x00013030 | |
185 | #define CS35L41_DSP_VIRT1_MBOX_6 0x00013034 | |
186 | #define CS35L41_DSP_VIRT1_MBOX_7 0x00013038 | |
187 | #define CS35L41_DSP_VIRT1_MBOX_8 0x0001303C | |
188 | #define CS35L41_DSP_VIRT2_MBOX_1 0x00013040 | |
189 | #define CS35L41_DSP_VIRT2_MBOX_2 0x00013044 | |
190 | #define CS35L41_DSP_VIRT2_MBOX_3 0x00013048 | |
191 | #define CS35L41_DSP_VIRT2_MBOX_4 0x0001304C | |
192 | #define CS35L41_DSP_VIRT2_MBOX_5 0x00013050 | |
193 | #define CS35L41_DSP_VIRT2_MBOX_6 0x00013054 | |
194 | #define CS35L41_DSP_VIRT2_MBOX_7 0x00013058 | |
195 | #define CS35L41_DSP_VIRT2_MBOX_8 0x0001305C | |
196 | #define CS35L41_CLOCK_DETECT_1 0x00014000 | |
197 | #define CS35L41_TIMER1_CONTROL 0x00015000 | |
198 | #define CS35L41_TIMER1_COUNT_PRESET 0x00015004 | |
199 | #define CS35L41_TIMER1_START_STOP 0x0001500C | |
200 | #define CS35L41_TIMER1_STATUS 0x00015010 | |
201 | #define CS35L41_TIMER1_COUNT_READBACK 0x00015014 | |
202 | #define CS35L41_TIMER1_DSP_CLK_CFG 0x00015018 | |
203 | #define CS35L41_TIMER1_DSP_CLK_STATUS 0x0001501C | |
204 | #define CS35L41_TIMER2_CONTROL 0x00015100 | |
205 | #define CS35L41_TIMER2_COUNT_PRESET 0x00015104 | |
206 | #define CS35L41_TIMER2_START_STOP 0x0001510C | |
207 | #define CS35L41_TIMER2_STATUS 0x00015110 | |
208 | #define CS35L41_TIMER2_COUNT_READBACK 0x00015114 | |
209 | #define CS35L41_TIMER2_DSP_CLK_CFG 0x00015118 | |
210 | #define CS35L41_TIMER2_DSP_CLK_STATUS 0x0001511C | |
211 | #define CS35L41_DFT_JTAG_CONTROL 0x00016000 | |
212 | #define CS35L41_DIE_STS1 0x00017040 | |
213 | #define CS35L41_DIE_STS2 0x00017044 | |
214 | #define CS35L41_TEMP_CAL1 0x00017048 | |
215 | #define CS35L41_TEMP_CAL2 0x0001704C | |
216 | #define CS35L41_DSP1_XMEM_PACK_0 0x02000000 | |
217 | #define CS35L41_DSP1_XMEM_PACK_3068 0x02002FF0 | |
218 | #define CS35L41_DSP1_XMEM_UNPACK32_0 0x02400000 | |
219 | #define CS35L41_DSP1_XMEM_UNPACK32_2046 0x02401FF8 | |
220 | #define CS35L41_DSP1_TIMESTAMP_COUNT 0x025C0800 | |
221 | #define CS35L41_DSP1_SYS_ID 0x025E0000 | |
222 | #define CS35L41_DSP1_SYS_VERSION 0x025E0004 | |
223 | #define CS35L41_DSP1_SYS_CORE_ID 0x025E0008 | |
224 | #define CS35L41_DSP1_SYS_AHB_ADDR 0x025E000C | |
225 | #define CS35L41_DSP1_SYS_XSRAM_SIZE 0x025E0010 | |
226 | #define CS35L41_DSP1_SYS_YSRAM_SIZE 0x025E0018 | |
227 | #define CS35L41_DSP1_SYS_PSRAM_SIZE 0x025E0020 | |
228 | #define CS35L41_DSP1_SYS_PM_BOOT_SIZE 0x025E0028 | |
229 | #define CS35L41_DSP1_SYS_FEATURES 0x025E002C | |
230 | #define CS35L41_DSP1_SYS_FIR_FILTERS 0x025E0030 | |
231 | #define CS35L41_DSP1_SYS_LMS_FILTERS 0x025E0034 | |
232 | #define CS35L41_DSP1_SYS_XM_BANK_SIZE 0x025E0038 | |
233 | #define CS35L41_DSP1_SYS_YM_BANK_SIZE 0x025E003C | |
234 | #define CS35L41_DSP1_SYS_PM_BANK_SIZE 0x025E0040 | |
235 | #define CS35L41_DSP1_AHBM_WIN0_CTRL0 0x025E2000 | |
236 | #define CS35L41_DSP1_AHBM_WIN0_CTRL1 0x025E2004 | |
237 | #define CS35L41_DSP1_AHBM_WIN1_CTRL0 0x025E2008 | |
238 | #define CS35L41_DSP1_AHBM_WIN1_CTRL1 0x025E200C | |
239 | #define CS35L41_DSP1_AHBM_WIN2_CTRL0 0x025E2010 | |
240 | #define CS35L41_DSP1_AHBM_WIN2_CTRL1 0x025E2014 | |
241 | #define CS35L41_DSP1_AHBM_WIN3_CTRL0 0x025E2018 | |
242 | #define CS35L41_DSP1_AHBM_WIN3_CTRL1 0x025E201C | |
243 | #define CS35L41_DSP1_AHBM_WIN4_CTRL0 0x025E2020 | |
244 | #define CS35L41_DSP1_AHBM_WIN4_CTRL1 0x025E2024 | |
245 | #define CS35L41_DSP1_AHBM_WIN5_CTRL0 0x025E2028 | |
246 | #define CS35L41_DSP1_AHBM_WIN5_CTRL1 0x025E202C | |
247 | #define CS35L41_DSP1_AHBM_WIN6_CTRL0 0x025E2030 | |
248 | #define CS35L41_DSP1_AHBM_WIN6_CTRL1 0x025E2034 | |
249 | #define CS35L41_DSP1_AHBM_WIN7_CTRL0 0x025E2038 | |
250 | #define CS35L41_DSP1_AHBM_WIN7_CTRL1 0x025E203C | |
251 | #define CS35L41_DSP1_AHBM_WIN_DBG_CTRL0 0x025E2040 | |
252 | #define CS35L41_DSP1_AHBM_WIN_DBG_CTRL1 0x025E2044 | |
253 | #define CS35L41_DSP1_XMEM_UNPACK24_0 0x02800000 | |
254 | #define CS35L41_DSP1_XMEM_UNPACK24_4093 0x02803FF4 | |
255 | #define CS35L41_DSP1_CTRL_BASE 0x02B80000 | |
256 | #define CS35L41_DSP1_CORE_SOFT_RESET 0x02B80010 | |
257 | #define CS35L41_DSP1_DEBUG 0x02B80040 | |
258 | #define CS35L41_DSP1_TIMER_CTRL 0x02B80048 | |
259 | #define CS35L41_DSP1_STREAM_ARB_CTRL 0x02B80050 | |
260 | #define CS35L41_DSP1_RX1_RATE 0x02B80080 | |
261 | #define CS35L41_DSP1_RX2_RATE 0x02B80088 | |
262 | #define CS35L41_DSP1_RX3_RATE 0x02B80090 | |
263 | #define CS35L41_DSP1_RX4_RATE 0x02B80098 | |
264 | #define CS35L41_DSP1_RX5_RATE 0x02B800A0 | |
265 | #define CS35L41_DSP1_RX6_RATE 0x02B800A8 | |
266 | #define CS35L41_DSP1_RX7_RATE 0x02B800B0 | |
267 | #define CS35L41_DSP1_RX8_RATE 0x02B800B8 | |
268 | #define CS35L41_DSP1_TX1_RATE 0x02B80280 | |
269 | #define CS35L41_DSP1_TX2_RATE 0x02B80288 | |
270 | #define CS35L41_DSP1_TX3_RATE 0x02B80290 | |
271 | #define CS35L41_DSP1_TX4_RATE 0x02B80298 | |
272 | #define CS35L41_DSP1_TX5_RATE 0x02B802A0 | |
273 | #define CS35L41_DSP1_TX6_RATE 0x02B802A8 | |
274 | #define CS35L41_DSP1_TX7_RATE 0x02B802B0 | |
275 | #define CS35L41_DSP1_TX8_RATE 0x02B802B8 | |
276 | #define CS35L41_DSP1_NMI_CTRL1 0x02B80480 | |
277 | #define CS35L41_DSP1_NMI_CTRL2 0x02B80488 | |
278 | #define CS35L41_DSP1_NMI_CTRL3 0x02B80490 | |
279 | #define CS35L41_DSP1_NMI_CTRL4 0x02B80498 | |
280 | #define CS35L41_DSP1_NMI_CTRL5 0x02B804A0 | |
281 | #define CS35L41_DSP1_NMI_CTRL6 0x02B804A8 | |
282 | #define CS35L41_DSP1_NMI_CTRL7 0x02B804B0 | |
283 | #define CS35L41_DSP1_NMI_CTRL8 0x02B804B8 | |
284 | #define CS35L41_DSP1_RESUME_CTRL 0x02B80500 | |
285 | #define CS35L41_DSP1_IRQ1_CTRL 0x02B80508 | |
286 | #define CS35L41_DSP1_IRQ2_CTRL 0x02B80510 | |
287 | #define CS35L41_DSP1_IRQ3_CTRL 0x02B80518 | |
288 | #define CS35L41_DSP1_IRQ4_CTRL 0x02B80520 | |
289 | #define CS35L41_DSP1_IRQ5_CTRL 0x02B80528 | |
290 | #define CS35L41_DSP1_IRQ6_CTRL 0x02B80530 | |
291 | #define CS35L41_DSP1_IRQ7_CTRL 0x02B80538 | |
292 | #define CS35L41_DSP1_IRQ8_CTRL 0x02B80540 | |
293 | #define CS35L41_DSP1_IRQ9_CTRL 0x02B80548 | |
294 | #define CS35L41_DSP1_IRQ10_CTRL 0x02B80550 | |
295 | #define CS35L41_DSP1_IRQ11_CTRL 0x02B80558 | |
296 | #define CS35L41_DSP1_IRQ12_CTRL 0x02B80560 | |
297 | #define CS35L41_DSP1_IRQ13_CTRL 0x02B80568 | |
298 | #define CS35L41_DSP1_IRQ14_CTRL 0x02B80570 | |
299 | #define CS35L41_DSP1_IRQ15_CTRL 0x02B80578 | |
300 | #define CS35L41_DSP1_IRQ16_CTRL 0x02B80580 | |
301 | #define CS35L41_DSP1_IRQ17_CTRL 0x02B80588 | |
302 | #define CS35L41_DSP1_IRQ18_CTRL 0x02B80590 | |
303 | #define CS35L41_DSP1_IRQ19_CTRL 0x02B80598 | |
304 | #define CS35L41_DSP1_IRQ20_CTRL 0x02B805A0 | |
305 | #define CS35L41_DSP1_IRQ21_CTRL 0x02B805A8 | |
306 | #define CS35L41_DSP1_IRQ22_CTRL 0x02B805B0 | |
307 | #define CS35L41_DSP1_IRQ23_CTRL 0x02B805B8 | |
308 | #define CS35L41_DSP1_SCRATCH1 0x02B805C0 | |
309 | #define CS35L41_DSP1_SCRATCH2 0x02B805C8 | |
310 | #define CS35L41_DSP1_SCRATCH3 0x02B805D0 | |
311 | #define CS35L41_DSP1_SCRATCH4 0x02B805D8 | |
312 | #define CS35L41_DSP1_CCM_CORE_CTRL 0x02BC1000 | |
313 | #define CS35L41_DSP1_CCM_CLK_OVERRIDE 0x02BC1008 | |
314 | #define CS35L41_DSP1_XM_MSTR_EN 0x02BC2000 | |
315 | #define CS35L41_DSP1_XM_CORE_PRI 0x02BC2008 | |
316 | #define CS35L41_DSP1_XM_AHB_PACK_PL_PRI 0x02BC2010 | |
317 | #define CS35L41_DSP1_XM_AHB_UP_PL_PRI 0x02BC2018 | |
318 | #define CS35L41_DSP1_XM_ACCEL_PL0_PRI 0x02BC2020 | |
319 | #define CS35L41_DSP1_XM_NPL0_PRI 0x02BC2078 | |
320 | #define CS35L41_DSP1_YM_MSTR_EN 0x02BC20C0 | |
321 | #define CS35L41_DSP1_YM_CORE_PRI 0x02BC20C8 | |
322 | #define CS35L41_DSP1_YM_AHB_PACK_PL_PRI 0x02BC20D0 | |
323 | #define CS35L41_DSP1_YM_AHB_UP_PL_PRI 0x02BC20D8 | |
324 | #define CS35L41_DSP1_YM_ACCEL_PL0_PRI 0x02BC20E0 | |
325 | #define CS35L41_DSP1_YM_NPL0_PRI 0x02BC2138 | |
326 | #define CS35L41_DSP1_PM_MSTR_EN 0x02BC2180 | |
327 | #define CS35L41_DSP1_PM_PATCH0_ADDR 0x02BC2188 | |
328 | #define CS35L41_DSP1_PM_PATCH0_EN 0x02BC218C | |
329 | #define CS35L41_DSP1_PM_PATCH0_DATA_LO 0x02BC2190 | |
330 | #define CS35L41_DSP1_PM_PATCH0_DATA_HI 0x02BC2194 | |
331 | #define CS35L41_DSP1_PM_PATCH1_ADDR 0x02BC2198 | |
332 | #define CS35L41_DSP1_PM_PATCH1_EN 0x02BC219C | |
333 | #define CS35L41_DSP1_PM_PATCH1_DATA_LO 0x02BC21A0 | |
334 | #define CS35L41_DSP1_PM_PATCH1_DATA_HI 0x02BC21A4 | |
335 | #define CS35L41_DSP1_PM_PATCH2_ADDR 0x02BC21A8 | |
336 | #define CS35L41_DSP1_PM_PATCH2_EN 0x02BC21AC | |
337 | #define CS35L41_DSP1_PM_PATCH2_DATA_LO 0x02BC21B0 | |
338 | #define CS35L41_DSP1_PM_PATCH2_DATA_HI 0x02BC21B4 | |
339 | #define CS35L41_DSP1_PM_PATCH3_ADDR 0x02BC21B8 | |
340 | #define CS35L41_DSP1_PM_PATCH3_EN 0x02BC21BC | |
341 | #define CS35L41_DSP1_PM_PATCH3_DATA_LO 0x02BC21C0 | |
342 | #define CS35L41_DSP1_PM_PATCH3_DATA_HI 0x02BC21C4 | |
343 | #define CS35L41_DSP1_PM_PATCH4_ADDR 0x02BC21C8 | |
344 | #define CS35L41_DSP1_PM_PATCH4_EN 0x02BC21CC | |
345 | #define CS35L41_DSP1_PM_PATCH4_DATA_LO 0x02BC21D0 | |
346 | #define CS35L41_DSP1_PM_PATCH4_DATA_HI 0x02BC21D4 | |
347 | #define CS35L41_DSP1_PM_PATCH5_ADDR 0x02BC21D8 | |
348 | #define CS35L41_DSP1_PM_PATCH5_EN 0x02BC21DC | |
349 | #define CS35L41_DSP1_PM_PATCH5_DATA_LO 0x02BC21E0 | |
350 | #define CS35L41_DSP1_PM_PATCH5_DATA_HI 0x02BC21E4 | |
351 | #define CS35L41_DSP1_PM_PATCH6_ADDR 0x02BC21E8 | |
352 | #define CS35L41_DSP1_PM_PATCH6_EN 0x02BC21EC | |
353 | #define CS35L41_DSP1_PM_PATCH6_DATA_LO 0x02BC21F0 | |
354 | #define CS35L41_DSP1_PM_PATCH6_DATA_HI 0x02BC21F4 | |
355 | #define CS35L41_DSP1_PM_PATCH7_ADDR 0x02BC21F8 | |
356 | #define CS35L41_DSP1_PM_PATCH7_EN 0x02BC21FC | |
357 | #define CS35L41_DSP1_PM_PATCH7_DATA_LO 0x02BC2200 | |
358 | #define CS35L41_DSP1_PM_PATCH7_DATA_HI 0x02BC2204 | |
359 | #define CS35L41_DSP1_MPU_XM_ACCESS0 0x02BC3000 | |
360 | #define CS35L41_DSP1_MPU_YM_ACCESS0 0x02BC3004 | |
361 | #define CS35L41_DSP1_MPU_WNDW_ACCESS0 0x02BC3008 | |
362 | #define CS35L41_DSP1_MPU_XREG_ACCESS0 0x02BC300C | |
363 | #define CS35L41_DSP1_MPU_YREG_ACCESS0 0x02BC3014 | |
364 | #define CS35L41_DSP1_MPU_XM_ACCESS1 0x02BC3018 | |
365 | #define CS35L41_DSP1_MPU_YM_ACCESS1 0x02BC301C | |
366 | #define CS35L41_DSP1_MPU_WNDW_ACCESS1 0x02BC3020 | |
367 | #define CS35L41_DSP1_MPU_XREG_ACCESS1 0x02BC3024 | |
368 | #define CS35L41_DSP1_MPU_YREG_ACCESS1 0x02BC302C | |
369 | #define CS35L41_DSP1_MPU_XM_ACCESS2 0x02BC3030 | |
370 | #define CS35L41_DSP1_MPU_YM_ACCESS2 0x02BC3034 | |
371 | #define CS35L41_DSP1_MPU_WNDW_ACCESS2 0x02BC3038 | |
372 | #define CS35L41_DSP1_MPU_XREG_ACCESS2 0x02BC303C | |
373 | #define CS35L41_DSP1_MPU_YREG_ACCESS2 0x02BC3044 | |
374 | #define CS35L41_DSP1_MPU_XM_ACCESS3 0x02BC3048 | |
375 | #define CS35L41_DSP1_MPU_YM_ACCESS3 0x02BC304C | |
376 | #define CS35L41_DSP1_MPU_WNDW_ACCESS3 0x02BC3050 | |
377 | #define CS35L41_DSP1_MPU_XREG_ACCESS3 0x02BC3054 | |
378 | #define CS35L41_DSP1_MPU_YREG_ACCESS3 0x02BC305C | |
379 | #define CS35L41_DSP1_MPU_XM_VIO_ADDR 0x02BC3100 | |
380 | #define CS35L41_DSP1_MPU_XM_VIO_STATUS 0x02BC3104 | |
381 | #define CS35L41_DSP1_MPU_YM_VIO_ADDR 0x02BC3108 | |
382 | #define CS35L41_DSP1_MPU_YM_VIO_STATUS 0x02BC310C | |
383 | #define CS35L41_DSP1_MPU_PM_VIO_ADDR 0x02BC3110 | |
384 | #define CS35L41_DSP1_MPU_PM_VIO_STATUS 0x02BC3114 | |
385 | #define CS35L41_DSP1_MPU_LOCK_CONFIG 0x02BC3140 | |
386 | #define CS35L41_DSP1_MPU_WDT_RST_CTRL 0x02BC3180 | |
387 | #define CS35L41_DSP1_STRMARB_MSTR0_CFG0 0x02BC5000 | |
388 | #define CS35L41_DSP1_STRMARB_MSTR0_CFG1 0x02BC5004 | |
389 | #define CS35L41_DSP1_STRMARB_MSTR0_CFG2 0x02BC5008 | |
390 | #define CS35L41_DSP1_STRMARB_MSTR1_CFG0 0x02BC5010 | |
391 | #define CS35L41_DSP1_STRMARB_MSTR1_CFG1 0x02BC5014 | |
392 | #define CS35L41_DSP1_STRMARB_MSTR1_CFG2 0x02BC5018 | |
393 | #define CS35L41_DSP1_STRMARB_MSTR2_CFG0 0x02BC5020 | |
394 | #define CS35L41_DSP1_STRMARB_MSTR2_CFG1 0x02BC5024 | |
395 | #define CS35L41_DSP1_STRMARB_MSTR2_CFG2 0x02BC5028 | |
396 | #define CS35L41_DSP1_STRMARB_MSTR3_CFG0 0x02BC5030 | |
397 | #define CS35L41_DSP1_STRMARB_MSTR3_CFG1 0x02BC5034 | |
398 | #define CS35L41_DSP1_STRMARB_MSTR3_CFG2 0x02BC5038 | |
399 | #define CS35L41_DSP1_STRMARB_MSTR4_CFG0 0x02BC5040 | |
400 | #define CS35L41_DSP1_STRMARB_MSTR4_CFG1 0x02BC5044 | |
401 | #define CS35L41_DSP1_STRMARB_MSTR4_CFG2 0x02BC5048 | |
402 | #define CS35L41_DSP1_STRMARB_MSTR5_CFG0 0x02BC5050 | |
403 | #define CS35L41_DSP1_STRMARB_MSTR5_CFG1 0x02BC5054 | |
404 | #define CS35L41_DSP1_STRMARB_MSTR5_CFG2 0x02BC5058 | |
405 | #define CS35L41_DSP1_STRMARB_MSTR6_CFG0 0x02BC5060 | |
406 | #define CS35L41_DSP1_STRMARB_MSTR6_CFG1 0x02BC5064 | |
407 | #define CS35L41_DSP1_STRMARB_MSTR6_CFG2 0x02BC5068 | |
408 | #define CS35L41_DSP1_STRMARB_MSTR7_CFG0 0x02BC5070 | |
409 | #define CS35L41_DSP1_STRMARB_MSTR7_CFG1 0x02BC5074 | |
410 | #define CS35L41_DSP1_STRMARB_MSTR7_CFG2 0x02BC5078 | |
411 | #define CS35L41_DSP1_STRMARB_TX0_CFG0 0x02BC5200 | |
412 | #define CS35L41_DSP1_STRMARB_TX0_CFG1 0x02BC5204 | |
413 | #define CS35L41_DSP1_STRMARB_TX1_CFG0 0x02BC5208 | |
414 | #define CS35L41_DSP1_STRMARB_TX1_CFG1 0x02BC520C | |
415 | #define CS35L41_DSP1_STRMARB_TX2_CFG0 0x02BC5210 | |
416 | #define CS35L41_DSP1_STRMARB_TX2_CFG1 0x02BC5214 | |
417 | #define CS35L41_DSP1_STRMARB_TX3_CFG0 0x02BC5218 | |
418 | #define CS35L41_DSP1_STRMARB_TX3_CFG1 0x02BC521C | |
419 | #define CS35L41_DSP1_STRMARB_TX4_CFG0 0x02BC5220 | |
420 | #define CS35L41_DSP1_STRMARB_TX4_CFG1 0x02BC5224 | |
421 | #define CS35L41_DSP1_STRMARB_TX5_CFG0 0x02BC5228 | |
422 | #define CS35L41_DSP1_STRMARB_TX5_CFG1 0x02BC522C | |
423 | #define CS35L41_DSP1_STRMARB_TX6_CFG0 0x02BC5230 | |
424 | #define CS35L41_DSP1_STRMARB_TX6_CFG1 0x02BC5234 | |
425 | #define CS35L41_DSP1_STRMARB_TX7_CFG0 0x02BC5238 | |
426 | #define CS35L41_DSP1_STRMARB_TX7_CFG1 0x02BC523C | |
427 | #define CS35L41_DSP1_STRMARB_RX0_CFG0 0x02BC5400 | |
428 | #define CS35L41_DSP1_STRMARB_RX0_CFG1 0x02BC5404 | |
429 | #define CS35L41_DSP1_STRMARB_RX1_CFG0 0x02BC5408 | |
430 | #define CS35L41_DSP1_STRMARB_RX1_CFG1 0x02BC540C | |
431 | #define CS35L41_DSP1_STRMARB_RX2_CFG0 0x02BC5410 | |
432 | #define CS35L41_DSP1_STRMARB_RX2_CFG1 0x02BC5414 | |
433 | #define CS35L41_DSP1_STRMARB_RX3_CFG0 0x02BC5418 | |
434 | #define CS35L41_DSP1_STRMARB_RX3_CFG1 0x02BC541C | |
435 | #define CS35L41_DSP1_STRMARB_RX4_CFG0 0x02BC5420 | |
436 | #define CS35L41_DSP1_STRMARB_RX4_CFG1 0x02BC5424 | |
437 | #define CS35L41_DSP1_STRMARB_RX5_CFG0 0x02BC5428 | |
438 | #define CS35L41_DSP1_STRMARB_RX5_CFG1 0x02BC542C | |
439 | #define CS35L41_DSP1_STRMARB_RX6_CFG0 0x02BC5430 | |
440 | #define CS35L41_DSP1_STRMARB_RX6_CFG1 0x02BC5434 | |
441 | #define CS35L41_DSP1_STRMARB_RX7_CFG0 0x02BC5438 | |
442 | #define CS35L41_DSP1_STRMARB_RX7_CFG1 0x02BC543C | |
443 | #define CS35L41_DSP1_STRMARB_IRQ0_CFG0 0x02BC5600 | |
444 | #define CS35L41_DSP1_STRMARB_IRQ0_CFG1 0x02BC5604 | |
445 | #define CS35L41_DSP1_STRMARB_IRQ0_CFG2 0x02BC5608 | |
446 | #define CS35L41_DSP1_STRMARB_IRQ1_CFG0 0x02BC5610 | |
447 | #define CS35L41_DSP1_STRMARB_IRQ1_CFG1 0x02BC5614 | |
448 | #define CS35L41_DSP1_STRMARB_IRQ1_CFG2 0x02BC5618 | |
449 | #define CS35L41_DSP1_STRMARB_IRQ2_CFG0 0x02BC5620 | |
450 | #define CS35L41_DSP1_STRMARB_IRQ2_CFG1 0x02BC5624 | |
451 | #define CS35L41_DSP1_STRMARB_IRQ2_CFG2 0x02BC5628 | |
452 | #define CS35L41_DSP1_STRMARB_IRQ3_CFG0 0x02BC5630 | |
453 | #define CS35L41_DSP1_STRMARB_IRQ3_CFG1 0x02BC5634 | |
454 | #define CS35L41_DSP1_STRMARB_IRQ3_CFG2 0x02BC5638 | |
455 | #define CS35L41_DSP1_STRMARB_IRQ4_CFG0 0x02BC5640 | |
456 | #define CS35L41_DSP1_STRMARB_IRQ4_CFG1 0x02BC5644 | |
457 | #define CS35L41_DSP1_STRMARB_IRQ4_CFG2 0x02BC5648 | |
458 | #define CS35L41_DSP1_STRMARB_IRQ5_CFG0 0x02BC5650 | |
459 | #define CS35L41_DSP1_STRMARB_IRQ5_CFG1 0x02BC5654 | |
460 | #define CS35L41_DSP1_STRMARB_IRQ5_CFG2 0x02BC5658 | |
461 | #define CS35L41_DSP1_STRMARB_IRQ6_CFG0 0x02BC5660 | |
462 | #define CS35L41_DSP1_STRMARB_IRQ6_CFG1 0x02BC5664 | |
463 | #define CS35L41_DSP1_STRMARB_IRQ6_CFG2 0x02BC5668 | |
464 | #define CS35L41_DSP1_STRMARB_IRQ7_CFG0 0x02BC5670 | |
465 | #define CS35L41_DSP1_STRMARB_IRQ7_CFG1 0x02BC5674 | |
466 | #define CS35L41_DSP1_STRMARB_IRQ7_CFG2 0x02BC5678 | |
467 | #define CS35L41_DSP1_STRMARB_RESYNC_MSK 0x02BC5A00 | |
468 | #define CS35L41_DSP1_STRMARB_ERR_STATUS 0x02BC5A08 | |
469 | #define CS35L41_DSP1_INTPCTL_RES_STATIC 0x02BC6000 | |
470 | #define CS35L41_DSP1_INTPCTL_RES_DYN 0x02BC6004 | |
471 | #define CS35L41_DSP1_INTPCTL_NMI_CTRL 0x02BC6008 | |
472 | #define CS35L41_DSP1_INTPCTL_IRQ_INV 0x02BC6010 | |
473 | #define CS35L41_DSP1_INTPCTL_IRQ_MODE 0x02BC6014 | |
474 | #define CS35L41_DSP1_INTPCTL_IRQ_EN 0x02BC6018 | |
475 | #define CS35L41_DSP1_INTPCTL_IRQ_MSK 0x02BC601C | |
476 | #define CS35L41_DSP1_INTPCTL_IRQ_FLUSH 0x02BC6020 | |
477 | #define CS35L41_DSP1_INTPCTL_IRQ_MSKCLR 0x02BC6024 | |
478 | #define CS35L41_DSP1_INTPCTL_IRQ_FRC 0x02BC6028 | |
479 | #define CS35L41_DSP1_INTPCTL_IRQ_MSKSET 0x02BC602C | |
480 | #define CS35L41_DSP1_INTPCTL_IRQ_ERR 0x02BC6030 | |
481 | #define CS35L41_DSP1_INTPCTL_IRQ_PEND 0x02BC6034 | |
482 | #define CS35L41_DSP1_INTPCTL_IRQ_GEN 0x02BC6038 | |
483 | #define CS35L41_DSP1_INTPCTL_TESTBITS 0x02BC6040 | |
484 | #define CS35L41_DSP1_WDT_CONTROL 0x02BC7000 | |
485 | #define CS35L41_DSP1_WDT_STATUS 0x02BC7008 | |
486 | #define CS35L41_DSP1_YMEM_PACK_0 0x02C00000 | |
487 | #define CS35L41_DSP1_YMEM_PACK_1532 0x02C017F0 | |
488 | #define CS35L41_DSP1_YMEM_UNPACK32_0 0x03000000 | |
489 | #define CS35L41_DSP1_YMEM_UNPACK32_1022 0x03000FF8 | |
490 | #define CS35L41_DSP1_YMEM_UNPACK24_0 0x03400000 | |
491 | #define CS35L41_DSP1_YMEM_UNPACK24_2045 0x03401FF4 | |
492 | #define CS35L41_DSP1_PMEM_0 0x03800000 | |
493 | #define CS35L41_DSP1_PMEM_5114 0x03804FE8 | |
494 | ||
495 | /*test regs for emulation bringup*/ | |
496 | #define CS35L41_PLL_OVR 0x00003018 | |
497 | #define CS35L41_BST_TEST_DUTY 0x00003900 | |
498 | #define CS35L41_DIGPWM_IOCTRL 0x0000706C | |
499 | ||
500 | /*registers populated by OTP*/ | |
501 | #define CS35L41_OTP_TRIM_1 0x0000208c | |
502 | #define CS35L41_OTP_TRIM_2 0x00002090 | |
503 | #define CS35L41_OTP_TRIM_3 0x00003010 | |
504 | #define CS35L41_OTP_TRIM_4 0x0000300C | |
505 | #define CS35L41_OTP_TRIM_5 0x0000394C | |
506 | #define CS35L41_OTP_TRIM_6 0x00003950 | |
507 | #define CS35L41_OTP_TRIM_7 0x00003954 | |
508 | #define CS35L41_OTP_TRIM_8 0x00003958 | |
509 | #define CS35L41_OTP_TRIM_9 0x0000395C | |
510 | #define CS35L41_OTP_TRIM_10 0x0000416C | |
511 | #define CS35L41_OTP_TRIM_11 0x00004160 | |
512 | #define CS35L41_OTP_TRIM_12 0x00004170 | |
513 | #define CS35L41_OTP_TRIM_13 0x00004360 | |
514 | #define CS35L41_OTP_TRIM_14 0x00004448 | |
515 | #define CS35L41_OTP_TRIM_15 0x0000444C | |
516 | #define CS35L41_OTP_TRIM_16 0x00006E30 | |
517 | #define CS35L41_OTP_TRIM_17 0x00006E34 | |
518 | #define CS35L41_OTP_TRIM_18 0x00006E38 | |
519 | #define CS35L41_OTP_TRIM_19 0x00006E3C | |
520 | #define CS35L41_OTP_TRIM_20 0x00006E40 | |
521 | #define CS35L41_OTP_TRIM_21 0x00006E44 | |
522 | #define CS35L41_OTP_TRIM_22 0x00006E48 | |
523 | #define CS35L41_OTP_TRIM_23 0x00006E4C | |
524 | #define CS35L41_OTP_TRIM_24 0x00006E50 | |
525 | #define CS35L41_OTP_TRIM_25 0x00006E54 | |
526 | #define CS35L41_OTP_TRIM_26 0x00006E58 | |
527 | #define CS35L41_OTP_TRIM_27 0x00006E5C | |
528 | #define CS35L41_OTP_TRIM_28 0x00006E60 | |
529 | #define CS35L41_OTP_TRIM_29 0x00006E64 | |
530 | #define CS35L41_OTP_TRIM_30 0x00007418 | |
531 | #define CS35L41_OTP_TRIM_31 0x0000741C | |
532 | #define CS35L41_OTP_TRIM_32 0x00007434 | |
533 | #define CS35L41_OTP_TRIM_33 0x00007068 | |
534 | #define CS35L41_OTP_TRIM_34 0x0000410C | |
535 | #define CS35L41_OTP_TRIM_35 0x0000400C | |
536 | #define CS35L41_OTP_TRIM_36 0x00002030 | |
537 | ||
538 | #define CS35L41_MAX_CACHE_REG 36 | |
539 | #define CS35L41_OTP_SIZE_WORDS 32 | |
a87d4222 | 540 | |
a87d4222 LT |
541 | #define CS35L41_NUM_SUPPLIES 2 |
542 | ||
543 | #define CS35L41_SCLK_MSTR_MASK 0x10 | |
544 | #define CS35L41_SCLK_MSTR_SHIFT 4 | |
545 | #define CS35L41_LRCLK_MSTR_MASK 0x01 | |
546 | #define CS35L41_LRCLK_MSTR_SHIFT 0 | |
547 | #define CS35L41_SCLK_INV_MASK 0x40 | |
548 | #define CS35L41_SCLK_INV_SHIFT 6 | |
549 | #define CS35L41_LRCLK_INV_MASK 0x04 | |
550 | #define CS35L41_LRCLK_INV_SHIFT 2 | |
551 | #define CS35L41_SCLK_FRC_MASK 0x20 | |
552 | #define CS35L41_SCLK_FRC_SHIFT 5 | |
553 | #define CS35L41_LRCLK_FRC_MASK 0x02 | |
554 | #define CS35L41_LRCLK_FRC_SHIFT 1 | |
555 | ||
556 | #define CS35L41_AMP_GAIN_PCM_MASK 0x3E0 | |
557 | #define CS35L41_AMP_GAIN_ZC_MASK 0x0400 | |
558 | #define CS35L41_AMP_GAIN_ZC_SHIFT 10 | |
559 | ||
560 | #define CS35L41_BST_CTL_MASK 0xFF | |
561 | #define CS35L41_BST_CTL_SEL_MASK 0x03 | |
562 | #define CS35L41_BST_CTL_SEL_REG 0x00 | |
563 | #define CS35L41_BST_CTL_SEL_CLASSH 0x01 | |
564 | #define CS35L41_BST_IPK_MASK 0x7F | |
565 | #define CS35L41_BST_IPK_SHIFT 0 | |
566 | #define CS35L41_BST_LIM_MASK 0x4 | |
567 | #define CS35L41_BST_LIM_SHIFT 2 | |
568 | #define CS35L41_BST_K1_MASK 0x000000FF | |
569 | #define CS35L41_BST_K1_SHIFT 0 | |
570 | #define CS35L41_BST_K2_MASK 0x0000FF00 | |
571 | #define CS35L41_BST_K2_SHIFT 8 | |
572 | #define CS35L41_BST_SLOPE_MASK 0x0000FF00 | |
573 | #define CS35L41_BST_SLOPE_SHIFT 8 | |
574 | #define CS35L41_BST_LBST_VAL_MASK 0x00000003 | |
575 | #define CS35L41_BST_LBST_VAL_SHIFT 0 | |
576 | ||
577 | #define CS35L41_TEMP_THLD_MASK 0x03 | |
578 | #define CS35L41_VMON_IMON_VOL_MASK 0x07FF07FF | |
579 | #define CS35L41_PDM_MODE_MASK 0x01 | |
580 | #define CS35L41_PDM_MODE_SHIFT 0 | |
581 | ||
582 | #define CS35L41_CH_MEM_DEPTH_MASK 0x07 | |
583 | #define CS35L41_CH_MEM_DEPTH_SHIFT 0 | |
584 | #define CS35L41_CH_HDRM_CTL_MASK 0x007F0000 | |
585 | #define CS35L41_CH_HDRM_CTL_SHIFT 16 | |
586 | #define CS35L41_CH_REL_RATE_MASK 0xFF00 | |
587 | #define CS35L41_CH_REL_RATE_SHIFT 8 | |
588 | #define CS35L41_CH_WKFET_DLY_MASK 0x001C | |
589 | #define CS35L41_CH_WKFET_DLY_SHIFT 2 | |
590 | #define CS35L41_CH_WKFET_THLD_MASK 0x0F00 | |
591 | #define CS35L41_CH_WKFET_THLD_SHIFT 8 | |
592 | ||
593 | #define CS35L41_HW_NG_SEL_MASK 0x3F00 | |
594 | #define CS35L41_HW_NG_SEL_SHIFT 8 | |
595 | #define CS35L41_HW_NG_DLY_MASK 0x0070 | |
596 | #define CS35L41_HW_NG_DLY_SHIFT 4 | |
597 | #define CS35L41_HW_NG_THLD_MASK 0x0007 | |
598 | #define CS35L41_HW_NG_THLD_SHIFT 0 | |
599 | ||
600 | #define CS35L41_DSP_NG_ENABLE_MASK 0x00010000 | |
601 | #define CS35L41_DSP_NG_ENABLE_SHIFT 16 | |
602 | #define CS35L41_DSP_NG_THLD_MASK 0x7 | |
603 | #define CS35L41_DSP_NG_THLD_SHIFT 0 | |
604 | #define CS35L41_DSP_NG_DELAY_MASK 0x0F00 | |
605 | #define CS35L41_DSP_NG_DELAY_SHIFT 8 | |
606 | ||
607 | #define CS35L41_ASP_FMT_MASK 0x0700 | |
608 | #define CS35L41_ASP_FMT_SHIFT 8 | |
609 | #define CS35L41_ASP_DOUT_HIZ_MASK 0x03 | |
610 | #define CS35L41_ASP_DOUT_HIZ_SHIFT 0 | |
611 | #define CS35L41_ASP_WIDTH_16 0x10 | |
612 | #define CS35L41_ASP_WIDTH_24 0x18 | |
613 | #define CS35L41_ASP_WIDTH_32 0x20 | |
614 | #define CS35L41_ASP_WIDTH_TX_MASK 0xFF0000 | |
615 | #define CS35L41_ASP_WIDTH_TX_SHIFT 16 | |
616 | #define CS35L41_ASP_WIDTH_RX_MASK 0xFF000000 | |
617 | #define CS35L41_ASP_WIDTH_RX_SHIFT 24 | |
618 | #define CS35L41_ASP_RX1_SLOT_MASK 0x3F | |
619 | #define CS35L41_ASP_RX1_SLOT_SHIFT 0 | |
620 | #define CS35L41_ASP_RX2_SLOT_MASK 0x3F00 | |
621 | #define CS35L41_ASP_RX2_SLOT_SHIFT 8 | |
622 | #define CS35L41_ASP_RX_WL_MASK 0x3F | |
623 | #define CS35L41_ASP_TX_WL_MASK 0x3F | |
624 | #define CS35L41_ASP_RX_WL_SHIFT 0 | |
625 | #define CS35L41_ASP_TX_WL_SHIFT 0 | |
626 | #define CS35L41_ASP_SOURCE_MASK 0x7F | |
627 | ||
628 | #define CS35L41_INPUT_SRC_ASPRX1 0x08 | |
629 | #define CS35L41_INPUT_SRC_ASPRX2 0x09 | |
630 | #define CS35L41_INPUT_SRC_VMON 0x18 | |
631 | #define CS35L41_INPUT_SRC_IMON 0x19 | |
632 | #define CS35L41_INPUT_SRC_CLASSH 0x21 | |
633 | #define CS35L41_INPUT_SRC_VPMON 0x28 | |
634 | #define CS35L41_INPUT_SRC_VBSTMON 0x29 | |
635 | #define CS35L41_INPUT_SRC_TEMPMON 0x3A | |
636 | #define CS35L41_INPUT_SRC_RSVD 0x3B | |
637 | #define CS35L41_INPUT_DSP_TX1 0x32 | |
638 | #define CS35L41_INPUT_DSP_TX2 0x33 | |
639 | ||
f517ba49 CK |
640 | #define CS35L41_WR_PEND_STS_MASK 0x2 |
641 | ||
a87d4222 LT |
642 | #define CS35L41_PLL_CLK_SEL_MASK 0x07 |
643 | #define CS35L41_PLL_CLK_SEL_SHIFT 0 | |
644 | #define CS35L41_PLL_CLK_EN_MASK 0x10 | |
645 | #define CS35L41_PLL_CLK_EN_SHIFT 4 | |
646 | #define CS35L41_PLL_OPENLOOP_MASK 0x0800 | |
647 | #define CS35L41_PLL_OPENLOOP_SHIFT 11 | |
648 | #define CS35L41_PLLSRC_SCLK 0 | |
649 | #define CS35L41_PLLSRC_LRCLK 1 | |
650 | #define CS35L41_PLLSRC_SELF 3 | |
651 | #define CS35L41_PLLSRC_PDMCLK 4 | |
652 | #define CS35L41_PLLSRC_MCLK 5 | |
653 | #define CS35L41_PLLSRC_SWIRE 7 | |
654 | #define CS35L41_REFCLK_FREQ_MASK 0x7E0 | |
655 | #define CS35L41_REFCLK_FREQ_SHIFT 5 | |
656 | ||
657 | #define CS35L41_GLOBAL_FS_MASK 0x1F | |
658 | #define CS35L41_GLOBAL_FS_SHIFT 0 | |
659 | ||
660 | #define CS35L41_GLOBAL_EN_MASK 0x01 | |
661 | #define CS35L41_GLOBAL_EN_SHIFT 0 | |
662 | #define CS35L41_BST_EN_MASK 0x0030 | |
663 | #define CS35L41_BST_EN_SHIFT 4 | |
5fdb68a7 | 664 | #define CS35L41_BST_DIS_FET_OFF 0x00 |
a87d4222 LT |
665 | #define CS35L41_BST_EN_DEFAULT 0x2 |
666 | #define CS35L41_AMP_EN_SHIFT 0 | |
667 | #define CS35L41_AMP_EN_MASK 1 | |
2e81e1ff VR |
668 | #define CS35L41_VMON_EN_MASK 0x1000 |
669 | #define CS35L41_VMON_EN_SHIFT 12 | |
670 | #define CS35L41_IMON_EN_MASK 0x2000 | |
671 | #define CS35L41_IMON_EN_SHIFT 13 | |
a87d4222 LT |
672 | |
673 | #define CS35L41_PDN_DONE_MASK 0x00800000 | |
674 | #define CS35L41_PDN_DONE_SHIFT 23 | |
675 | #define CS35L41_PUP_DONE_MASK 0x01000000 | |
676 | #define CS35L41_PUP_DONE_SHIFT 24 | |
677 | ||
678 | #define CS35L36_PUP_DONE_IRQ_UNMASK 0x5F | |
679 | #define CS35L36_PUP_DONE_IRQ_MASK 0xBF | |
680 | ||
681 | #define CS35L41_AMP_SHORT_ERR 0x80000000 | |
682 | #define CS35L41_BST_SHORT_ERR 0x0100 | |
683 | #define CS35L41_TEMP_WARN 0x8000 | |
684 | #define CS35L41_TEMP_ERR 0x00020000 | |
685 | #define CS35L41_BST_OVP_ERR 0x40 | |
686 | #define CS35L41_BST_DCM_UVP_ERR 0x80 | |
687 | #define CS35L41_OTP_BOOT_DONE 0x02 | |
688 | #define CS35L41_PLL_UNLOCK 0x10 | |
689 | #define CS35L41_OTP_BOOT_ERR 0x80000000 | |
690 | ||
691 | #define CS35L41_AMP_SHORT_ERR_RLS 0x02 | |
692 | #define CS35L41_BST_SHORT_ERR_RLS 0x04 | |
693 | #define CS35L41_BST_OVP_ERR_RLS 0x08 | |
694 | #define CS35L41_BST_UVP_ERR_RLS 0x10 | |
695 | #define CS35L41_TEMP_WARN_ERR_RLS 0x20 | |
696 | #define CS35L41_TEMP_ERR_RLS 0x40 | |
697 | ||
aa4a38af SB |
698 | #define CS35L41_AMP_SHORT_ERR_RLS_SHIFT 1 |
699 | #define CS35L41_BST_SHORT_ERR_RLS_SHIFT 2 | |
700 | #define CS35L41_BST_OVP_ERR_RLS_SHIFT 3 | |
701 | #define CS35L41_BST_UVP_ERR_RLS_SHIFT 4 | |
702 | #define CS35L41_TEMP_WARN_ERR_RLS_SHIFT 5 | |
703 | #define CS35L41_TEMP_ERR_RLS_SHIFT 6 | |
704 | ||
a87d4222 LT |
705 | #define CS35L41_INT1_MASK_DEFAULT 0x7FFCFE3F |
706 | #define CS35L41_INT1_UNMASK_PUP 0xFEFFFFFF | |
707 | #define CS35L41_INT1_UNMASK_PDN 0xFF7FFFFF | |
708 | ||
709 | #define CS35L41_GPIO_DIR_MASK 0x80000000 | |
710 | #define CS35L41_GPIO_DIR_SHIFT 31 | |
711 | #define CS35L41_GPIO1_CTRL_MASK 0x00030000 | |
712 | #define CS35L41_GPIO1_CTRL_SHIFT 16 | |
713 | #define CS35L41_GPIO2_CTRL_MASK 0x07000000 | |
714 | #define CS35L41_GPIO2_CTRL_SHIFT 24 | |
bb06c203 LT |
715 | #define CS35L41_GPIO_LVL_SHIFT 15 |
716 | #define CS35L41_GPIO_LVL_MASK BIT(CS35L41_GPIO_LVL_SHIFT) | |
a87d4222 LT |
717 | #define CS35L41_GPIO_POL_MASK 0x1000 |
718 | #define CS35L41_GPIO_POL_SHIFT 12 | |
719 | ||
720 | #define CS35L41_AMP_INV_PCM_SHIFT 14 | |
721 | #define CS35L41_AMP_INV_PCM_MASK BIT(CS35L41_AMP_INV_PCM_SHIFT) | |
722 | #define CS35L41_AMP_PCM_VOL_SHIFT 3 | |
723 | #define CS35L41_AMP_PCM_VOL_MASK (0x7FF << 3) | |
724 | #define CS35L41_AMP_PCM_VOL_MUTE 0x4CF | |
725 | ||
726 | #define CS35L41_CHIP_ID 0x35a40 | |
727 | #define CS35L41R_CHIP_ID 0x35b40 | |
728 | #define CS35L41_MTLREVID_MASK 0x0F | |
729 | #define CS35L41_REVID_A0 0xA0 | |
730 | #define CS35L41_REVID_B0 0xB0 | |
731 | #define CS35L41_REVID_B2 0xB2 | |
732 | ||
733 | #define CS35L41_HALO_CORE_RESET 0x00000200 | |
734 | ||
735 | #define CS35L41_FS1_WINDOW_MASK 0x000007FF | |
736 | #define CS35L41_FS2_WINDOW_MASK 0x00FFF800 | |
737 | #define CS35L41_FS2_WINDOW_SHIFT 12 | |
738 | ||
739 | #define CS35L41_SPI_MAX_FREQ 4000000 | |
740 | #define CS35L41_REGSTRIDE 4 | |
741 | ||
b8388a1a LT |
742 | enum cs35l41_boost_type { |
743 | CS35L41_INT_BOOST, | |
744 | CS35L41_EXT_BOOST, | |
745 | CS35L41_EXT_BOOST_NO_VSPK_SWITCH, | |
746 | }; | |
747 | ||
6450ef55 DR |
748 | enum cs35l41_clk_ids { |
749 | CS35L41_CLKID_SCLK = 0, | |
750 | CS35L41_CLKID_LRCLK = 1, | |
751 | CS35L41_CLKID_MCLK = 4, | |
752 | }; | |
753 | ||
f7f20737 LT |
754 | enum cs35l41_gpio1_func { |
755 | CS35L41_GPIO1_HIZ, | |
756 | CS35L41_GPIO1_GPIO, | |
757 | CS35L41_GPIO1_MDSYNC, | |
758 | CS35L41_GPIO1_MCLK, | |
759 | CS35L41_GPIO1_PDM_CLK, | |
760 | CS35L41_GPIO1_PDM_DATA, | |
6450ef55 DR |
761 | }; |
762 | ||
f7f20737 LT |
763 | enum cs35l41_gpio2_func { |
764 | CS35L41_GPIO2_HIZ, | |
765 | CS35L41_GPIO2_GPIO, | |
766 | CS35L41_GPIO2_INT_OPEN_DRAIN, | |
767 | CS35L41_GPIO2_MCLK, | |
768 | CS35L41_GPIO2_INT_PUSH_PULL_LOW, | |
769 | CS35L41_GPIO2_INT_PUSH_PULL_HIGH, | |
770 | CS35L41_GPIO2_PDM_CLK, | |
771 | CS35L41_GPIO2_PDM_DATA, | |
772 | }; | |
773 | ||
774 | struct cs35l41_gpio_cfg { | |
2603c974 | 775 | bool valid; |
f7f20737 LT |
776 | bool pol_inv; |
777 | bool out_en; | |
778 | unsigned int func; | |
779 | }; | |
780 | ||
781 | struct cs35l41_hw_cfg { | |
2603c974 | 782 | bool valid; |
6450ef55 DR |
783 | int bst_ind; |
784 | int bst_ipk; | |
785 | int bst_cap; | |
786 | int dout_hiz; | |
f7f20737 LT |
787 | struct cs35l41_gpio_cfg gpio1; |
788 | struct cs35l41_gpio_cfg gpio2; | |
789 | unsigned int spk_pos; | |
790 | ||
b8388a1a | 791 | enum cs35l41_boost_type bst_type; |
6450ef55 DR |
792 | }; |
793 | ||
a87d4222 LT |
794 | struct cs35l41_otp_packed_element_t { |
795 | u32 reg; | |
796 | u8 shift; | |
797 | u8 size; | |
798 | }; | |
799 | ||
800 | struct cs35l41_otp_map_element_t { | |
801 | u32 id; | |
802 | u32 num_elements; | |
803 | const struct cs35l41_otp_packed_element_t *map; | |
804 | u32 bit_offset; | |
805 | u32 word_offset; | |
806 | }; | |
807 | ||
caf7c1f1 SB |
808 | enum cs35l41_cspl_mbox_status { |
809 | CSPL_MBOX_STS_RUNNING = 0, | |
810 | CSPL_MBOX_STS_PAUSED = 1, | |
811 | CSPL_MBOX_STS_RDY_FOR_REINIT = 2, | |
812 | }; | |
813 | ||
814 | enum cs35l41_cspl_mbox_cmd { | |
815 | CSPL_MBOX_CMD_NONE = 0, | |
816 | CSPL_MBOX_CMD_PAUSE = 1, | |
817 | CSPL_MBOX_CMD_RESUME = 2, | |
818 | CSPL_MBOX_CMD_REINIT = 3, | |
819 | CSPL_MBOX_CMD_STOP_PRE_REINIT = 4, | |
820 | CSPL_MBOX_CMD_HIBERNATE = 5, | |
821 | CSPL_MBOX_CMD_OUT_OF_HIBERNATE = 6, | |
822 | CSPL_MBOX_CMD_UNKNOWN_CMD = -1, | |
823 | CSPL_MBOX_CMD_INVALID_SEQUENCE = -2, | |
824 | }; | |
825 | ||
aa4a38af SB |
826 | /* |
827 | * IRQs | |
828 | */ | |
829 | #define CS35L41_IRQ(_irq, _name, _hand) \ | |
830 | { \ | |
831 | .irq = CS35L41_ ## _irq ## _IRQ,\ | |
832 | .name = _name, \ | |
833 | .handler = _hand, \ | |
834 | } | |
835 | ||
836 | struct cs35l41_irq { | |
837 | int irq; | |
838 | const char *name; | |
839 | irqreturn_t (*handler)(int irq, void *data); | |
840 | }; | |
841 | ||
842 | #define CS35L41_REG_IRQ(_reg, _irq) \ | |
843 | [CS35L41_ ## _irq ## _IRQ] = { \ | |
844 | .reg_offset = (CS35L41_ ## _reg) - CS35L41_IRQ1_STATUS1,\ | |
845 | .mask = CS35L41_ ## _irq ## _MASK \ | |
846 | } | |
847 | ||
848 | /* (0x0000E010) CS35L41_IRQ1_STATUS1 */ | |
849 | #define CS35L41_BST_OVP_ERR_SHIFT 6 | |
850 | #define CS35L41_BST_OVP_ERR_MASK BIT(CS35L41_BST_OVP_ERR_SHIFT) | |
851 | #define CS35L41_BST_DCM_UVP_ERR_SHIFT 7 | |
852 | #define CS35L41_BST_DCM_UVP_ERR_MASK BIT(CS35L41_BST_DCM_UVP_ERR_SHIFT) | |
853 | #define CS35L41_BST_SHORT_ERR_SHIFT 8 | |
854 | #define CS35L41_BST_SHORT_ERR_MASK BIT(CS35L41_BST_SHORT_ERR_SHIFT) | |
855 | #define CS35L41_TEMP_WARN_SHIFT 15 | |
856 | #define CS35L41_TEMP_WARN_MASK BIT(CS35L41_TEMP_WARN_SHIFT) | |
857 | #define CS35L41_TEMP_ERR_SHIFT 17 | |
858 | #define CS35L41_TEMP_ERR_MASK BIT(CS35L41_TEMP_ERR_SHIFT) | |
859 | #define CS35L41_AMP_SHORT_ERR_SHIFT 31 | |
860 | #define CS35L41_AMP_SHORT_ERR_MASK BIT(CS35L41_AMP_SHORT_ERR_SHIFT) | |
861 | ||
862 | enum cs35l41_irq_list { | |
863 | CS35L41_BST_OVP_ERR_IRQ, | |
864 | CS35L41_BST_DCM_UVP_ERR_IRQ, | |
865 | CS35L41_BST_SHORT_ERR_IRQ, | |
866 | CS35L41_TEMP_WARN_IRQ, | |
867 | CS35L41_TEMP_ERR_IRQ, | |
868 | CS35L41_AMP_SHORT_ERR_IRQ, | |
869 | ||
870 | CS35L41_NUM_IRQ | |
871 | }; | |
872 | ||
a87d4222 LT |
873 | extern struct regmap_config cs35l41_regmap_i2c; |
874 | extern struct regmap_config cs35l41_regmap_spi; | |
875 | ||
d92321bb CK |
876 | int cs35l41_test_key_unlock(struct device *dev, struct regmap *regmap); |
877 | int cs35l41_test_key_lock(struct device *dev, struct regmap *regmap); | |
fe120d4c | 878 | int cs35l41_otp_unpack(struct device *dev, struct regmap *regmap); |
8b227860 | 879 | int cs35l41_register_errata_patch(struct device *dev, struct regmap *reg, unsigned int reg_revid); |
3bc3e3da LT |
880 | int cs35l41_set_channels(struct device *dev, struct regmap *reg, |
881 | unsigned int tx_num, unsigned int *tx_slot, | |
882 | unsigned int rx_num, unsigned int *rx_slot); | |
fcad8950 | 883 | int cs35l41_gpio_config(struct regmap *regmap, struct cs35l41_hw_cfg *hw_cfg); |
0db99577 | 884 | void cs35l41_configure_cs_dsp(struct device *dev, struct regmap *reg, struct cs_dsp *dsp); |
caf7c1f1 SB |
885 | int cs35l41_set_cspl_mbox_cmd(struct device *dev, struct regmap *regmap, |
886 | enum cs35l41_cspl_mbox_cmd cmd); | |
ff8aad07 | 887 | int cs35l41_write_fs_errata(struct device *dev, struct regmap *regmap); |
e341efc3 SB |
888 | int cs35l41_enter_hibernate(struct device *dev, struct regmap *regmap, |
889 | enum cs35l41_boost_type b_type); | |
94e0bc31 | 890 | int cs35l41_exit_hibernate(struct device *dev, struct regmap *regmap); |
5577dd23 LT |
891 | int cs35l41_init_boost(struct device *dev, struct regmap *regmap, |
892 | struct cs35l41_hw_cfg *hw_cfg); | |
893 | bool cs35l41_safe_reset(struct regmap *regmap, enum cs35l41_boost_type b_type); | |
894 | int cs35l41_global_enable(struct regmap *regmap, enum cs35l41_boost_type b_type, int enable); | |
fe120d4c | 895 | |
6450ef55 | 896 | #endif /* __CS35L41_H */ |