Commit | Line | Data |
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5f3cc447 | 1 | /* |
56bc911a | 2 | * Samsung S5P/Exynos4 SoC series camera interface driver header |
5f3cc447 | 3 | * |
56bc911a SN |
4 | * Copyright (C) 2010 - 2013 Samsung Electronics Co., Ltd. |
5 | * Sylwester Nawrocki <s.nawrocki@samsung.com> | |
5f3cc447 SN |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
df7e09a3 SN |
12 | #ifndef S5P_FIMC_H_ |
13 | #define S5P_FIMC_H_ | |
5f3cc447 | 14 | |
b9ee31e6 | 15 | #include <media/media-entity.h> |
bc7584b0 | 16 | #include <media/v4l2-dev.h> |
80f958f4 | 17 | #include <media/v4l2-mediabus.h> |
b9ee31e6 | 18 | |
02399e35 SN |
19 | /* |
20 | * Enumeration of data inputs to the camera subsystem. | |
21 | */ | |
22 | enum fimc_input { | |
23 | FIMC_INPUT_PARALLEL_0 = 1, | |
24 | FIMC_INPUT_PARALLEL_1, | |
25 | FIMC_INPUT_MIPI_CSI2_0 = 3, | |
26 | FIMC_INPUT_MIPI_CSI2_1, | |
27 | FIMC_INPUT_WRITEBACK_A = 5, | |
28 | FIMC_INPUT_WRITEBACK_B, | |
29 | FIMC_INPUT_WRITEBACK_ISP = 5, | |
30 | }; | |
31 | ||
56bc911a SN |
32 | /* |
33 | * Enumeration of the FIMC data bus types. | |
34 | */ | |
35 | enum fimc_bus_type { | |
36 | /* Camera parallel bus */ | |
37 | FIMC_BUS_TYPE_ITU_601 = 1, | |
38 | /* Camera parallel bus with embedded synchronization */ | |
39 | FIMC_BUS_TYPE_ITU_656, | |
40 | /* Camera MIPI-CSI2 serial bus */ | |
41 | FIMC_BUS_TYPE_MIPI_CSI2, | |
42 | /* FIFO link from LCD controller (WriteBack A) */ | |
43 | FIMC_BUS_TYPE_LCD_WRITEBACK_A, | |
44 | /* FIFO link from LCD controller (WriteBack B) */ | |
45 | FIMC_BUS_TYPE_LCD_WRITEBACK_B, | |
46 | /* FIFO link from FIMC-IS */ | |
47 | FIMC_BUS_TYPE_ISP_WRITEBACK = FIMC_BUS_TYPE_LCD_WRITEBACK_B, | |
5f3cc447 SN |
48 | }; |
49 | ||
2b13f7d4 SN |
50 | #define fimc_input_is_parallel(x) ((x) == 1 || (x) == 2) |
51 | #define fimc_input_is_mipi_csi(x) ((x) == 3 || (x) == 4) | |
52 | ||
488f29d0 SN |
53 | /* |
54 | * The subdevices' group IDs. | |
55 | */ | |
56 | #define GRP_ID_SENSOR (1 << 8) | |
57 | #define GRP_ID_FIMC_IS_SENSOR (1 << 9) | |
58 | #define GRP_ID_WRITEBACK (1 << 10) | |
59 | #define GRP_ID_CSIS (1 << 11) | |
60 | #define GRP_ID_FIMC (1 << 12) | |
61 | #define GRP_ID_FLITE (1 << 13) | |
62 | #define GRP_ID_FIMC_IS (1 << 14) | |
63 | ||
5f3cc447 SN |
64 | struct i2c_board_info; |
65 | ||
66 | /** | |
56bc911a SN |
67 | * struct fimc_source_info - video source description required for the host |
68 | * interface configuration | |
5f3cc447 SN |
69 | * |
70 | * @board_info: pointer to I2C subdevice's board info | |
a25be18d | 71 | * @clk_frequency: frequency of the clock the host interface provides to sensor |
56bc911a SN |
72 | * @fimc_bus_type: FIMC camera input type |
73 | * @sensor_bus_type: image sensor bus type, MIPI, ITU-R BT.601 etc. | |
74 | * @flags: the parallel sensor bus flags defining signals polarity (V4L2_MBUS_*) | |
5f3cc447 SN |
75 | * @i2c_bus_num: i2c control bus id the sensor is attached to |
76 | * @mux_id: FIMC camera interface multiplexer index (separate for MIPI and ITU) | |
d3953223 | 77 | * @clk_id: index of the SoC peripheral clock for sensors |
5f3cc447 | 78 | */ |
56bc911a | 79 | struct fimc_source_info { |
5f3cc447 | 80 | struct i2c_board_info *board_info; |
a25be18d | 81 | unsigned long clk_frequency; |
56bc911a SN |
82 | enum fimc_bus_type fimc_bus_type; |
83 | enum fimc_bus_type sensor_bus_type; | |
84 | u16 flags; | |
5f3cc447 SN |
85 | u16 i2c_bus_num; |
86 | u16 mux_id; | |
d3953223 | 87 | u8 clk_id; |
5f3cc447 SN |
88 | }; |
89 | ||
5f3cc447 | 90 | /** |
df7e09a3 | 91 | * struct s5p_platform_fimc - camera host interface platform data |
5f3cc447 | 92 | * |
56bc911a SN |
93 | * @source_info: properties of an image source for the host interface setup |
94 | * @num_clients: the number of attached image sources | |
5f3cc447 | 95 | */ |
df7e09a3 | 96 | struct s5p_platform_fimc { |
56bc911a | 97 | struct fimc_source_info *source_info; |
117182d1 | 98 | int num_clients; |
5f3cc447 | 99 | }; |
e1d72f4d SN |
100 | |
101 | /* | |
102 | * v4l2_device notification id. This is only for internal use in the kernel. | |
103 | * Sensor subdevs should issue S5P_FIMC_TX_END_NOTIFY notification in single | |
104 | * frame capture mode when there is only one VSYNC pulse issued by the sensor | |
105 | * at begining of the frame transmission. | |
106 | */ | |
107 | #define S5P_FIMC_TX_END_NOTIFY _IO('e', 0) | |
108 | ||
80f958f4 SN |
109 | #define FIMC_MAX_PLANES 3 |
110 | ||
111 | /** | |
112 | * struct fimc_fmt - color format data structure | |
113 | * @mbus_code: media bus pixel code, -1 if not applicable | |
114 | * @name: format description | |
115 | * @fourcc: fourcc code for this format, 0 if not applicable | |
116 | * @color: the driver's private color format id | |
117 | * @memplanes: number of physically non-contiguous data planes | |
118 | * @colplanes: number of physically contiguous data planes | |
119 | * @depth: per plane driver's private 'number of bits per pixel' | |
120 | * @mdataplanes: bitmask indicating meta data plane(s), (1 << plane_no) | |
121 | * @flags: flags indicating which operation mode format applies to | |
122 | */ | |
123 | struct fimc_fmt { | |
124 | enum v4l2_mbus_pixelcode mbus_code; | |
125 | char *name; | |
126 | u32 fourcc; | |
127 | u32 color; | |
128 | u16 memplanes; | |
129 | u16 colplanes; | |
130 | u8 depth[FIMC_MAX_PLANES]; | |
131 | u16 mdataplanes; | |
132 | u16 flags; | |
133 | #define FMT_FLAGS_CAM (1 << 0) | |
134 | #define FMT_FLAGS_M2M_IN (1 << 1) | |
135 | #define FMT_FLAGS_M2M_OUT (1 << 2) | |
136 | #define FMT_FLAGS_M2M (1 << 1 | 1 << 2) | |
137 | #define FMT_HAS_ALPHA (1 << 3) | |
138 | #define FMT_FLAGS_COMPRESSED (1 << 4) | |
139 | #define FMT_FLAGS_WRITEBACK (1 << 5) | |
e90ad659 SN |
140 | #define FMT_FLAGS_RAW_BAYER (1 << 6) |
141 | #define FMT_FLAGS_YUV (1 << 7) | |
80f958f4 SN |
142 | }; |
143 | ||
0f735f52 SN |
144 | enum fimc_subdev_index { |
145 | IDX_SENSOR, | |
146 | IDX_CSIS, | |
147 | IDX_FLITE, | |
e2985a26 | 148 | IDX_IS_ISP, |
0f735f52 SN |
149 | IDX_FIMC, |
150 | IDX_MAX, | |
151 | }; | |
152 | ||
153 | struct media_pipeline; | |
154 | struct v4l2_subdev; | |
155 | ||
156 | struct fimc_pipeline { | |
157 | struct v4l2_subdev *subdevs[IDX_MAX]; | |
158 | struct media_pipeline *m_pipeline; | |
159 | }; | |
160 | ||
bc7584b0 SN |
161 | struct exynos_video_entity { |
162 | struct video_device vdev; | |
163 | }; | |
164 | ||
b9ee31e6 SN |
165 | /* |
166 | * Media pipeline operations to be called from within the fimc(-lite) | |
167 | * video node when it is the last entity of the pipeline. Implemented | |
168 | * by corresponding media device driver. | |
169 | */ | |
170 | struct fimc_pipeline_ops { | |
171 | int (*open)(struct fimc_pipeline *p, struct media_entity *me, | |
172 | bool resume); | |
173 | int (*close)(struct fimc_pipeline *p); | |
174 | int (*set_stream)(struct fimc_pipeline *p, bool state); | |
175 | }; | |
176 | ||
177 | #define fimc_pipeline_call(f, op, p, args...) \ | |
178 | (!(f) ? -ENODEV : (((f)->pipeline_ops && (f)->pipeline_ops->op) ? \ | |
179 | (f)->pipeline_ops->op((p), ##args) : -ENOIOCTLCMD)) | |
180 | ||
df7e09a3 | 181 | #endif /* S5P_FIMC_H_ */ |