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b98d32f7 LP |
1 | /* |
2 | * omap3isp.h | |
3 | * | |
4 | * TI OMAP3 ISP - Platform data | |
5 | * | |
6 | * Copyright (C) 2011 Nokia Corporation | |
7 | * | |
8 | * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com> | |
9 | * Sakari Ailus <sakari.ailus@iki.fi> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but | |
16 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
23 | * 02110-1301 USA | |
24 | */ | |
25 | ||
26 | #ifndef __MEDIA_OMAP3ISP_H__ | |
27 | #define __MEDIA_OMAP3ISP_H__ | |
28 | ||
29 | struct i2c_board_info; | |
30 | struct isp_device; | |
31 | ||
32 | enum isp_interface_type { | |
33 | ISP_INTERFACE_PARALLEL, | |
34 | ISP_INTERFACE_CSI2A_PHY2, | |
35 | ISP_INTERFACE_CCP2B_PHY1, | |
36 | ISP_INTERFACE_CCP2B_PHY2, | |
37 | ISP_INTERFACE_CSI2C_PHY1, | |
38 | }; | |
39 | ||
b98d32f7 LP |
40 | enum { |
41 | ISP_LANE_SHIFT_0 = 0, | |
42 | ISP_LANE_SHIFT_2 = 1, | |
43 | ISP_LANE_SHIFT_4 = 2, | |
44 | ISP_LANE_SHIFT_6 = 3, | |
45 | }; | |
46 | ||
47 | /** | |
68908747 | 48 | * struct isp_parallel_cfg - Parallel interface configuration |
b98d32f7 LP |
49 | * @data_lane_shift: Data lane shifter |
50 | * ISP_LANE_SHIFT_0 - CAMEXT[13:0] -> CAM[13:0] | |
51 | * ISP_LANE_SHIFT_2 - CAMEXT[13:2] -> CAM[11:0] | |
52 | * ISP_LANE_SHIFT_4 - CAMEXT[13:4] -> CAM[9:0] | |
53 | * ISP_LANE_SHIFT_6 - CAMEXT[13:6] -> CAM[7:0] | |
54 | * @clk_pol: Pixel clock polarity | |
c1026c58 | 55 | * 0 - Sample on rising edge, 1 - Sample on falling edge |
b98d32f7 LP |
56 | * @hs_pol: Horizontal synchronization polarity |
57 | * 0 - Active high, 1 - Active low | |
58 | * @vs_pol: Vertical synchronization polarity | |
59 | * 0 - Active high, 1 - Active low | |
9a36d8ed LP |
60 | * @fld_pol: Field signal polarity |
61 | * 0 - Positive, 1 - Negative | |
73ea57eb LP |
62 | * @data_pol: Data polarity |
63 | * 0 - Normal, 1 - One's complement | |
b98d32f7 | 64 | */ |
68908747 | 65 | struct isp_parallel_cfg { |
b98d32f7 LP |
66 | unsigned int data_lane_shift:2; |
67 | unsigned int clk_pol:1; | |
68 | unsigned int hs_pol:1; | |
69 | unsigned int vs_pol:1; | |
9a36d8ed | 70 | unsigned int fld_pol:1; |
73ea57eb | 71 | unsigned int data_pol:1; |
b98d32f7 LP |
72 | }; |
73 | ||
74 | enum { | |
75 | ISP_CCP2_PHY_DATA_CLOCK = 0, | |
76 | ISP_CCP2_PHY_DATA_STROBE = 1, | |
77 | }; | |
78 | ||
79 | enum { | |
80 | ISP_CCP2_MODE_MIPI = 0, | |
81 | ISP_CCP2_MODE_CCP2 = 1, | |
82 | }; | |
83 | ||
fe6adc19 SA |
84 | /** |
85 | * struct isp_csiphy_lane: CCP2/CSI2 lane position and polarity | |
86 | * @pos: position of the lane | |
87 | * @pol: polarity of the lane | |
88 | */ | |
89 | struct isp_csiphy_lane { | |
90 | u8 pos; | |
91 | u8 pol; | |
92 | }; | |
93 | ||
94 | #define ISP_CSIPHY1_NUM_DATA_LANES 1 | |
95 | #define ISP_CSIPHY2_NUM_DATA_LANES 2 | |
96 | ||
97 | /** | |
98 | * struct isp_csiphy_lanes_cfg - CCP2/CSI2 lane configuration | |
99 | * @data: Configuration of one or two data lanes | |
100 | * @clk: Clock lane configuration | |
101 | */ | |
102 | struct isp_csiphy_lanes_cfg { | |
103 | struct isp_csiphy_lane data[ISP_CSIPHY2_NUM_DATA_LANES]; | |
104 | struct isp_csiphy_lane clk; | |
105 | }; | |
106 | ||
b98d32f7 | 107 | /** |
68908747 | 108 | * struct isp_ccp2_cfg - CCP2 interface configuration |
b98d32f7 LP |
109 | * @strobe_clk_pol: Strobe/clock polarity |
110 | * 0 - Non Inverted, 1 - Inverted | |
111 | * @crc: Enable the cyclic redundancy check | |
112 | * @ccp2_mode: Enable CCP2 compatibility mode | |
113 | * ISP_CCP2_MODE_MIPI - MIPI-CSI1 mode | |
114 | * ISP_CCP2_MODE_CCP2 - CCP2 mode | |
115 | * @phy_layer: Physical layer selection | |
116 | * ISP_CCP2_PHY_DATA_CLOCK - Data/clock physical layer | |
117 | * ISP_CCP2_PHY_DATA_STROBE - Data/strobe physical layer | |
118 | * @vpclk_div: Video port output clock control | |
119 | */ | |
68908747 | 120 | struct isp_ccp2_cfg { |
b98d32f7 LP |
121 | unsigned int strobe_clk_pol:1; |
122 | unsigned int crc:1; | |
123 | unsigned int ccp2_mode:1; | |
124 | unsigned int phy_layer:1; | |
125 | unsigned int vpclk_div:2; | |
fe6adc19 | 126 | struct isp_csiphy_lanes_cfg lanecfg; |
b98d32f7 LP |
127 | }; |
128 | ||
129 | /** | |
68908747 | 130 | * struct isp_csi2_cfg - CSI2 interface configuration |
b98d32f7 | 131 | * @crc: Enable the cyclic redundancy check |
b98d32f7 | 132 | */ |
68908747 | 133 | struct isp_csi2_cfg { |
b98d32f7 | 134 | unsigned crc:1; |
fe6adc19 | 135 | struct isp_csiphy_lanes_cfg lanecfg; |
b98d32f7 LP |
136 | }; |
137 | ||
68908747 | 138 | struct isp_bus_cfg { |
b98d32f7 LP |
139 | enum isp_interface_type interface; |
140 | union { | |
68908747 SA |
141 | struct isp_parallel_cfg parallel; |
142 | struct isp_ccp2_cfg ccp2; | |
143 | struct isp_csi2_cfg csi2; | |
b98d32f7 LP |
144 | } bus; /* gcc < 4.6.0 chokes on anonymous union initializers */ |
145 | }; | |
146 | ||
68908747 SA |
147 | struct isp_platform_subdev { |
148 | struct i2c_board_info *board_info; | |
149 | int i2c_adapter_id; | |
150 | struct isp_bus_cfg *bus; | |
151 | }; | |
152 | ||
b98d32f7 | 153 | struct isp_platform_data { |
68908747 | 154 | struct isp_platform_subdev *subdevs; |
b98d32f7 LP |
155 | void (*set_constraints)(struct isp_device *isp, bool enable); |
156 | }; | |
157 | ||
158 | #endif /* __MEDIA_OMAP3ISP_H__ */ |