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c942fddf | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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2 | /* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics |
3 | * Digitizer with Horizontal PLL registers | |
4 | * | |
5 | * Copyright (C) 2009 Texas Instruments Inc | |
6 | * Author: Santiago Nunez-Corrales <santiago.nunez@ridgerun.com> | |
7 | * | |
8 | * This code is partially based upon the TVP5150 driver | |
32590819 | 9 | * written by Mauro Carvalho Chehab <mchehab@kernel.org>, |
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10 | * the TVP514x driver written by Vaibhav Hiremath <hvaibhav@ti.com> |
11 | * and the TVP7002 driver in the TI LSP 2.10.00.14 | |
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12 | */ |
13 | #ifndef _TVP7002_H_ | |
14 | #define _TVP7002_H_ | |
15 | ||
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16 | #define TVP7002_MODULE_NAME "tvp7002" |
17 | ||
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18 | /** |
19 | * struct tvp7002_config - Platform dependent data | |
20 | *@clk_polarity: Clock polarity | |
21 | * 0 - Data clocked out on rising edge of DATACLK signal | |
22 | * 1 - Data clocked out on falling edge of DATACLK signal | |
23 | *@hs_polarity: HSYNC polarity | |
24 | * 0 - Active low HSYNC output, 1 - Active high HSYNC output | |
25 | *@vs_polarity: VSYNC Polarity | |
26 | * 0 - Active low VSYNC output, 1 - Active high VSYNC output | |
27 | *@fid_polarity: Active-high Field ID polarity. | |
28 | * 0 - The field ID output is set to logic 1 for an odd field | |
29 | * (field 1) and set to logic 0 for an even field (field 0). | |
30 | * 1 - Operation with polarity inverted. | |
31 | *@sog_polarity: Active high Sync on Green output polarity. | |
32 | * 0 - Normal operation, 1 - Operation with polarity inverted | |
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33 | */ |
34 | struct tvp7002_config { | |
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35 | bool clk_polarity; |
36 | bool hs_polarity; | |
37 | bool vs_polarity; | |
38 | bool fid_polarity; | |
39 | bool sog_polarity; | |
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40 | }; |
41 | #endif |