[linux-block.git] / include / linux / vfio_pci_core.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2012 Red Hat, Inc.  All rights reserved.
 *     Author: Alex Williamson <alex.williamson@redhat.com>
 *
 * Derived from original vfio:
 * Copyright 2010 Cisco Systems, Inc.  All rights reserved.
 * Author: Tom Lyon, pugs@cisco.com
 */

#include <linux/mutex.h>
#include <linux/pci.h>
#include <linux/vfio.h>
#include <linux/irqbypass.h>
#include <linux/types.h>
#include <linux/uuid.h>
#include <linux/notifier.h>

#ifndef VFIO_PCI_CORE_H
#define VFIO_PCI_CORE_H

#define VFIO_PCI_OFFSET_SHIFT   40

#define VFIO_PCI_OFFSET_TO_INDEX(off)	(off >> VFIO_PCI_OFFSET_SHIFT)
#define VFIO_PCI_INDEX_TO_OFFSET(index)	((u64)(index) << VFIO_PCI_OFFSET_SHIFT)
#define VFIO_PCI_OFFSET_MASK	(((u64)(1) << VFIO_PCI_OFFSET_SHIFT) - 1)

/* Special capability IDs predefined access */
#define PCI_CAP_ID_INVALID		0xFF	/* default raw access */
#define PCI_CAP_ID_INVALID_VIRT		0xFE	/* default virt access */

/* Cap maximum number of ioeventfds per device (arbitrary) */
#define VFIO_PCI_IOEVENTFD_MAX		1000

struct vfio_pci_ioeventfd {
	struct list_head	next;
	struct vfio_pci_core_device	*vdev;
	struct virqfd		*virqfd;
	void __iomem		*addr;
	uint64_t		data;
	loff_t			pos;
	int			bar;
	int			count;
	bool			test_mem;
};

struct vfio_pci_irq_ctx {
	struct eventfd_ctx	*trigger;
	struct virqfd		*unmask;
	struct virqfd		*mask;
	char			*name;
	bool			masked;
	struct irq_bypass_producer	producer;
};

struct vfio_pci_core_device;
struct vfio_pci_region;

struct vfio_pci_regops {
	ssize_t (*rw)(struct vfio_pci_core_device *vdev, char __user *buf,
		      size_t count, loff_t *ppos, bool iswrite);
	void	(*release)(struct vfio_pci_core_device *vdev,
			   struct vfio_pci_region *region);
	int	(*mmap)(struct vfio_pci_core_device *vdev,
			struct vfio_pci_region *region,
			struct vm_area_struct *vma);
	int	(*add_capability)(struct vfio_pci_core_device *vdev,
				  struct vfio_pci_region *region,
				  struct vfio_info_cap *caps);
};

struct vfio_pci_region {
	u32				type;
	u32				subtype;
	const struct vfio_pci_regops	*ops;
	void				*data;
	size_t				size;
	u32				flags;
};

struct vfio_pci_dummy_resource {
	struct resource		resource;
	int			index;
	struct list_head	res_next;
};

struct vfio_pci_vf_token {
	struct mutex		lock;
	uuid_t			uuid;
	int			users;
};

struct vfio_pci_mmap_vma {
	struct vm_area_struct	*vma;
	struct list_head	vma_next;
};

struct vfio_pci_core_device {
	struct vfio_device	vdev;
	struct pci_dev		*pdev;
	void __iomem		*barmap[PCI_STD_NUM_BARS];
	bool			bar_mmap_supported[PCI_STD_NUM_BARS];
	u8			*pci_config_map;
	u8			*vconfig;
	struct perm_bits	*msi_perm;
	spinlock_t		irqlock;
	struct mutex		igate;
	struct vfio_pci_irq_ctx	*ctx;
	int			num_ctx;
	int			irq_type;
	int			num_regions;
	struct vfio_pci_region	*region;
	u8			msi_qmax;
	u8			msix_bar;
	u16			msix_size;
	u32			msix_offset;
	u32			rbar[7];
	bool			pci_2_3;
	bool			virq_disabled;
	bool			reset_works;
	bool			extended_caps;
	bool			bardirty;
	bool			has_vga;
	bool			needs_reset;
	bool			nointx;
	bool			needs_pm_restore;
	struct pci_saved_state	*pci_saved_state;
	struct pci_saved_state	*pm_save;
	int			ioeventfds_nr;
	struct eventfd_ctx	*err_trigger;
	struct eventfd_ctx	*req_trigger;
	struct list_head	dummy_resources_list;
	struct mutex		ioeventfds_lock;
	struct list_head	ioeventfds_list;
	struct vfio_pci_vf_token	*vf_token;
	struct list_head		sriov_pfs_item;
	struct vfio_pci_core_device	*sriov_pf_core_dev;
	struct notifier_block	nb;
	struct mutex		vma_lock;
	struct list_head	vma_list;
	struct rw_semaphore	memory_lock;
};

#define is_intx(vdev) (vdev->irq_type == VFIO_PCI_INTX_IRQ_INDEX)
#define is_msi(vdev) (vdev->irq_type == VFIO_PCI_MSI_IRQ_INDEX)
#define is_msix(vdev) (vdev->irq_type == VFIO_PCI_MSIX_IRQ_INDEX)
#define is_irq_none(vdev) (!(is_intx(vdev) || is_msi(vdev) || is_msix(vdev)))
#define irq_is(vdev, type) (vdev->irq_type == type)

extern void vfio_pci_intx_mask(struct vfio_pci_core_device *vdev);
extern void vfio_pci_intx_unmask(struct vfio_pci_core_device *vdev);

extern int vfio_pci_set_irqs_ioctl(struct vfio_pci_core_device *vdev,
				   uint32_t flags, unsigned index,
				   unsigned start, unsigned count, void *data);

extern ssize_t vfio_pci_config_rw(struct vfio_pci_core_device *vdev,
				  char __user *buf, size_t count,
				  loff_t *ppos, bool iswrite);

extern ssize_t vfio_pci_bar_rw(struct vfio_pci_core_device *vdev, char __user *buf,
			       size_t count, loff_t *ppos, bool iswrite);

#ifdef CONFIG_VFIO_PCI_VGA
extern ssize_t vfio_pci_vga_rw(struct vfio_pci_core_device *vdev, char __user *buf,
			       size_t count, loff_t *ppos, bool iswrite);
#else
static inline ssize_t vfio_pci_vga_rw(struct vfio_pci_core_device *vdev,
				      char __user *buf, size_t count,
				      loff_t *ppos, bool iswrite)
{
	return -EINVAL;
}
#endif

extern long vfio_pci_ioeventfd(struct vfio_pci_core_device *vdev, loff_t offset,
			       uint64_t data, int count, int fd);

extern int vfio_pci_init_perm_bits(void);
extern void vfio_pci_uninit_perm_bits(void);

extern int vfio_config_init(struct vfio_pci_core_device *vdev);
extern void vfio_config_free(struct vfio_pci_core_device *vdev);

extern int vfio_pci_register_dev_region(struct vfio_pci_core_device *vdev,
					unsigned int type, unsigned int subtype,
					const struct vfio_pci_regops *ops,
					size_t size, u32 flags, void *data);

extern int vfio_pci_set_power_state(struct vfio_pci_core_device *vdev,
				    pci_power_t state);

extern bool __vfio_pci_memory_enabled(struct vfio_pci_core_device *vdev);
extern void vfio_pci_zap_and_down_write_memory_lock(struct vfio_pci_core_device
						    *vdev);
extern u16 vfio_pci_memory_lock_and_enable(struct vfio_pci_core_device *vdev);
extern void vfio_pci_memory_unlock_and_restore(struct vfio_pci_core_device *vdev,
					       u16 cmd);

#ifdef CONFIG_VFIO_PCI_IGD
extern int vfio_pci_igd_init(struct vfio_pci_core_device *vdev);
#else
static inline int vfio_pci_igd_init(struct vfio_pci_core_device *vdev)
{
	return -ENODEV;
}
#endif

#ifdef CONFIG_S390
extern int vfio_pci_info_zdev_add_caps(struct vfio_pci_core_device *vdev,
				       struct vfio_info_cap *caps);
#else
static inline int vfio_pci_info_zdev_add_caps(struct vfio_pci_core_device *vdev,
					      struct vfio_info_cap *caps)
{
	return -ENODEV;
}
#endif

/* Will be exported for vfio pci drivers usage */
void vfio_pci_core_set_params(bool nointxmask, bool is_disable_vga,
			      bool is_disable_idle_d3);
void vfio_pci_core_close_device(struct vfio_device *core_vdev);
void vfio_pci_core_init_device(struct vfio_pci_core_device *vdev,
			       struct pci_dev *pdev,
			       const struct vfio_device_ops *vfio_pci_ops);
int vfio_pci_core_register_device(struct vfio_pci_core_device *vdev);
void vfio_pci_core_uninit_device(struct vfio_pci_core_device *vdev);
void vfio_pci_core_unregister_device(struct vfio_pci_core_device *vdev);
int vfio_pci_core_sriov_configure(struct pci_dev *pdev, int nr_virtfn);
extern const struct pci_error_handlers vfio_pci_core_err_handlers;
long vfio_pci_core_ioctl(struct vfio_device *core_vdev, unsigned int cmd,
		unsigned long arg);
int vfio_pci_core_ioctl_feature(struct vfio_device *device, u32 flags,
				void __user *arg, size_t argsz);
ssize_t vfio_pci_core_read(struct vfio_device *core_vdev, char __user *buf,
		size_t count, loff_t *ppos);
ssize_t vfio_pci_core_write(struct vfio_device *core_vdev, const char __user *buf,
		size_t count, loff_t *ppos);
int vfio_pci_core_mmap(struct vfio_device *core_vdev, struct vm_area_struct *vma);
void vfio_pci_core_request(struct vfio_device *core_vdev, unsigned int count);
int vfio_pci_core_match(struct vfio_device *core_vdev, char *buf);
int vfio_pci_core_enable(struct vfio_pci_core_device *vdev);
void vfio_pci_core_disable(struct vfio_pci_core_device *vdev);
void vfio_pci_core_finish_enable(struct vfio_pci_core_device *vdev);
pci_ers_result_t vfio_pci_core_aer_err_detected(struct pci_dev *pdev,
						pci_channel_state_t state);

static inline bool vfio_pci_is_vga(struct pci_dev *pdev)
{
	return (pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA;
}

#endif /* VFIO_PCI_CORE_H */
Commit	Line	Data
d2912cb1	1	/* SPDX-License-Identifier: GPL-2.0-only */
89e1f7d4 AW	2	/*
	3	* Copyright (C) 2012 Red Hat, Inc. All rights reserved.
	4	* Author: Alex Williamson <alex.williamson@redhat.com>
	5	*
89e1f7d4 AW	6	* Derived from original vfio:
	7	* Copyright 2010 Cisco Systems, Inc. All rights reserved.
	8	* Author: Tom Lyon, pugs@cisco.com
	9	*/
	10
	11	#include <linux/mutex.h>
	12	#include <linux/pci.h>
c39f8fa7	13	#include <linux/vfio.h>
6d7425f1	14	#include <linux/irqbypass.h>
28541d41	15	#include <linux/types.h>
cc20d799	16	#include <linux/uuid.h>
137e5531	17	#include <linux/notifier.h>
89e1f7d4	18
9a389938 MG	19	#ifndef VFIO_PCI_CORE_H
9a389938 MG	20	#define VFIO_PCI_CORE_H
89e1f7d4 AW	21
	22	#define VFIO_PCI_OFFSET_SHIFT 40
	23
	24	#define VFIO_PCI_OFFSET_TO_INDEX(off) (off >> VFIO_PCI_OFFSET_SHIFT)
	25	#define VFIO_PCI_INDEX_TO_OFFSET(index) ((u64)(index) << VFIO_PCI_OFFSET_SHIFT)
	26	#define VFIO_PCI_OFFSET_MASK (((u64)(1) << VFIO_PCI_OFFSET_SHIFT) - 1)
	27
345d7104 AW	28	/* Special capability IDs predefined access */
	29	#define PCI_CAP_ID_INVALID 0xFF /* default raw access */
	30	#define PCI_CAP_ID_INVALID_VIRT 0xFE /* default virt access */
	31
30656177 AW	32	/* Cap maximum number of ioeventfds per device (arbitrary) */
	33	#define VFIO_PCI_IOEVENTFD_MAX 1000
	34
	35	struct vfio_pci_ioeventfd {
	36	struct list_head next;
53647510	37	struct vfio_pci_core_device *vdev;
30656177 AW	38	struct virqfd *virqfd;
	39	void __iomem *addr;
	40	uint64_t data;
	41	loff_t pos;
	42	int bar;
	43	int count;
bc93b9ae	44	bool test_mem;
30656177 AW	45	};
30656177 AW	46
89e1f7d4 AW	47	struct vfio_pci_irq_ctx {
	48	struct eventfd_ctx *trigger;
	49	struct virqfd *unmask;
	50	struct virqfd *mask;
	51	char *name;
	52	bool masked;
6d7425f1	53	struct irq_bypass_producer producer;
89e1f7d4 AW	54	};
89e1f7d4 AW	55
53647510	56	struct vfio_pci_core_device;
28541d41 AW	57	struct vfio_pci_region;
	58
	59	struct vfio_pci_regops {
53647510	60	ssize_t (rw)(struct vfio_pci_core_device vdev, char __user *buf,
28541d41	61	size_t count, loff_t *ppos, bool iswrite);
53647510	62	void (release)(struct vfio_pci_core_device vdev,
28541d41	63	struct vfio_pci_region *region);
53647510	64	int (mmap)(struct vfio_pci_core_device vdev,
a15b1883 AK	65	struct vfio_pci_region *region,
a15b1883 AK	66	struct vm_area_struct *vma);
53647510	67	int (add_capability)(struct vfio_pci_core_device vdev,
c2c0f1cd AK	68	struct vfio_pci_region *region,
c2c0f1cd AK	69	struct vfio_info_cap *caps);
28541d41 AW	70	};
	71
	72	struct vfio_pci_region {
	73	u32 type;
	74	u32 subtype;
	75	const struct vfio_pci_regops *ops;
	76	void *data;
	77	size_t size;
	78	u32 flags;
	79	};
	80
05f0c03f YX	81	struct vfio_pci_dummy_resource {
	82	struct resource resource;
	83	int index;
	84	struct list_head res_next;
	85	};
	86
cc20d799 AW	87	struct vfio_pci_vf_token {
	88	struct mutex lock;
	89	uuid_t uuid;
	90	int users;
	91	};
	92
11c4cd07 AW	93	struct vfio_pci_mmap_vma {
	94	struct vm_area_struct *vma;
	95	struct list_head vma_next;
	96	};
	97
53647510	98	struct vfio_pci_core_device {
6b018e20	99	struct vfio_device vdev;
89e1f7d4	100	struct pci_dev *pdev;
c9c13ba4 DE	101	void __iomem *barmap[PCI_STD_NUM_BARS];
c9c13ba4 DE	102	bool bar_mmap_supported[PCI_STD_NUM_BARS];
89e1f7d4 AW	103	u8 *pci_config_map;
	104	u8 *vconfig;
	105	struct perm_bits *msi_perm;
	106	spinlock_t irqlock;
	107	struct mutex igate;
89e1f7d4 AW	108	struct vfio_pci_irq_ctx *ctx;
	109	int num_ctx;
	110	int irq_type;
28541d41 AW	111	int num_regions;
28541d41 AW	112	struct vfio_pci_region *region;
89e1f7d4 AW	113	u8 msi_qmax;
	114	u8 msix_bar;
	115	u16 msix_size;
	116	u32 msix_offset;
	117	u32 rbar[7];
	118	bool pci_2_3;
	119	bool virq_disabled;
	120	bool reset_works;
	121	bool extended_caps;
	122	bool bardirty;
84237a82	123	bool has_vga;
bc4fba77	124	bool needs_reset;
45074405	125	bool nointx;
51ef3a00	126	bool needs_pm_restore;
89e1f7d4	127	struct pci_saved_state *pci_saved_state;
51ef3a00	128	struct pci_saved_state *pm_save;
30656177	129	int ioeventfds_nr;
dad9f897	130	struct eventfd_ctx *err_trigger;
6140a8f5	131	struct eventfd_ctx *req_trigger;
05f0c03f	132	struct list_head dummy_resources_list;
30656177 AW	133	struct mutex ioeventfds_lock;
30656177 AW	134	struct list_head ioeventfds_list;
cc20d799	135	struct vfio_pci_vf_token *vf_token;
1ef3342a JG	136	struct list_head sriov_pfs_item;
1ef3342a JG	137	struct vfio_pci_core_device *sriov_pf_core_dev;
137e5531	138	struct notifier_block nb;
11c4cd07 AW	139	struct mutex vma_lock;
11c4cd07 AW	140	struct list_head vma_list;
abafbc55	141	struct rw_semaphore memory_lock;
89e1f7d4 AW	142	};
	143
	144	#define is_intx(vdev) (vdev->irq_type == VFIO_PCI_INTX_IRQ_INDEX)
	145	#define is_msi(vdev) (vdev->irq_type == VFIO_PCI_MSI_IRQ_INDEX)
	146	#define is_msix(vdev) (vdev->irq_type == VFIO_PCI_MSIX_IRQ_INDEX)
	147	#define is_irq_none(vdev) (!(is_intx(vdev) \|\| is_msi(vdev) \|\| is_msix(vdev)))
	148	#define irq_is(vdev, type) (vdev->irq_type == type)
	149
53647510 MG	150	extern void vfio_pci_intx_mask(struct vfio_pci_core_device *vdev);
53647510 MG	151	extern void vfio_pci_intx_unmask(struct vfio_pci_core_device *vdev);
89e1f7d4	152
53647510	153	extern int vfio_pci_set_irqs_ioctl(struct vfio_pci_core_device *vdev,
89e1f7d4 AW	154	uint32_t flags, unsigned index,
	155	unsigned start, unsigned count, void *data);
	156
53647510	157	extern ssize_t vfio_pci_config_rw(struct vfio_pci_core_device *vdev,
906ee99d AW	158	char __user *buf, size_t count,
	159	loff_t *ppos, bool iswrite);
	160
53647510	161	extern ssize_t vfio_pci_bar_rw(struct vfio_pci_core_device vdev, char __user buf,
906ee99d	162	size_t count, loff_t *ppos, bool iswrite);
89e1f7d4	163
6e031ec0	164	#ifdef CONFIG_VFIO_PCI_VGA
53647510	165	extern ssize_t vfio_pci_vga_rw(struct vfio_pci_core_device vdev, char __user buf,
84237a82	166	size_t count, loff_t *ppos, bool iswrite);
6e031ec0 AW	167	#else
	168	static inline ssize_t vfio_pci_vga_rw(struct vfio_pci_core_device *vdev,
	169	char __user *buf, size_t count,
	170	loff_t *ppos, bool iswrite)
	171	{
	172	return -EINVAL;
	173	}
	174	#endif
84237a82	175
53647510	176	extern long vfio_pci_ioeventfd(struct vfio_pci_core_device *vdev, loff_t offset,
30656177 AW	177	uint64_t data, int count, int fd);
30656177 AW	178
89e1f7d4 AW	179	extern int vfio_pci_init_perm_bits(void);
	180	extern void vfio_pci_uninit_perm_bits(void);
	181
53647510 MG	182	extern int vfio_config_init(struct vfio_pci_core_device *vdev);
53647510 MG	183	extern void vfio_config_free(struct vfio_pci_core_device *vdev);
28541d41	184
53647510	185	extern int vfio_pci_register_dev_region(struct vfio_pci_core_device *vdev,
28541d41 AW	186	unsigned int type, unsigned int subtype,
	187	const struct vfio_pci_regops *ops,
	188	size_t size, u32 flags, void *data);
51ef3a00	189
53647510	190	extern int vfio_pci_set_power_state(struct vfio_pci_core_device *vdev,
51ef3a00 AW	191	pci_power_t state);
51ef3a00 AW	192
53647510 MG	193	extern bool __vfio_pci_memory_enabled(struct vfio_pci_core_device *vdev);
53647510 MG	194	extern void vfio_pci_zap_and_down_write_memory_lock(struct vfio_pci_core_device
abafbc55	195	*vdev);
53647510 MG	196	extern u16 vfio_pci_memory_lock_and_enable(struct vfio_pci_core_device *vdev);
53647510 MG	197	extern void vfio_pci_memory_unlock_and_restore(struct vfio_pci_core_device *vdev,
abafbc55 AW	198	u16 cmd);
abafbc55 AW	199
5846ff54	200	#ifdef CONFIG_VFIO_PCI_IGD
53647510	201	extern int vfio_pci_igd_init(struct vfio_pci_core_device *vdev);
5846ff54	202	#else
53647510	203	static inline int vfio_pci_igd_init(struct vfio_pci_core_device *vdev)
5846ff54 AW	204	{
	205	return -ENODEV;
	206	}
	207	#endif
e6b817d4	208
b9abef43	209	#ifdef CONFIG_S390
53647510	210	extern int vfio_pci_info_zdev_add_caps(struct vfio_pci_core_device *vdev,
e6b817d4 MR	211	struct vfio_info_cap *caps);
e6b817d4 MR	212	#else
53647510	213	static inline int vfio_pci_info_zdev_add_caps(struct vfio_pci_core_device *vdev,
e6b817d4 MR	214	struct vfio_info_cap *caps)
	215	{
	216	return -ENODEV;
	217	}
	218	#endif
	219
ff53edf6	220	/* Will be exported for vfio pci drivers usage */
c61302aa YH	221	void vfio_pci_core_set_params(bool nointxmask, bool is_disable_vga,
c61302aa YH	222	bool is_disable_idle_d3);
ff53edf6	223	void vfio_pci_core_close_device(struct vfio_device *core_vdev);
ff53edf6 MG	224	void vfio_pci_core_init_device(struct vfio_pci_core_device *vdev,
	225	struct pci_dev *pdev,
	226	const struct vfio_device_ops *vfio_pci_ops);
	227	int vfio_pci_core_register_device(struct vfio_pci_core_device *vdev);
	228	void vfio_pci_core_uninit_device(struct vfio_pci_core_device *vdev);
	229	void vfio_pci_core_unregister_device(struct vfio_pci_core_device *vdev);
	230	int vfio_pci_core_sriov_configure(struct pci_dev *pdev, int nr_virtfn);
	231	extern const struct pci_error_handlers vfio_pci_core_err_handlers;
	232	long vfio_pci_core_ioctl(struct vfio_device *core_vdev, unsigned int cmd,
	233	unsigned long arg);
445ad495 JG	234	int vfio_pci_core_ioctl_feature(struct vfio_device *device, u32 flags,
445ad495 JG	235	void __user *arg, size_t argsz);
ff53edf6 MG	236	ssize_t vfio_pci_core_read(struct vfio_device core_vdev, char __user buf,
	237	size_t count, loff_t *ppos);
	238	ssize_t vfio_pci_core_write(struct vfio_device core_vdev, const char __user buf,
	239	size_t count, loff_t *ppos);
	240	int vfio_pci_core_mmap(struct vfio_device core_vdev, struct vm_area_struct vma);
	241	void vfio_pci_core_request(struct vfio_device *core_vdev, unsigned int count);
	242	int vfio_pci_core_match(struct vfio_device core_vdev, char buf);
2fb89f56 MG	243	int vfio_pci_core_enable(struct vfio_pci_core_device *vdev);
	244	void vfio_pci_core_disable(struct vfio_pci_core_device *vdev);
	245	void vfio_pci_core_finish_enable(struct vfio_pci_core_device *vdev);
915076f7 YH	246	pci_ers_result_t vfio_pci_core_aer_err_detected(struct pci_dev *pdev,
915076f7 YH	247	pci_channel_state_t state);
2fb89f56 MG	248
	249	static inline bool vfio_pci_is_vga(struct pci_dev *pdev)
	250	{
	251	return (pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA;
	252	}
ff53edf6	253
9a389938	254	#endif /* VFIO_PCI_CORE_H */