[linux-block.git] / include / linux / ti-emif-sram.h

/*
 * TI AM33XX EMIF Routines
 *
 * Copyright (C) 2016-2017 Texas Instruments Inc.
 *	Dave Gerlach
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
#ifndef __LINUX_TI_EMIF_H
#define __LINUX_TI_EMIF_H

#include <linux/kbuild.h>
#include <linux/types.h>
#ifndef __ASSEMBLY__

struct emif_regs_amx3 {
	u32 emif_sdcfg_val;
	u32 emif_timing1_val;
	u32 emif_timing2_val;
	u32 emif_timing3_val;
	u32 emif_ref_ctrl_val;
	u32 emif_zqcfg_val;
	u32 emif_pmcr_val;
	u32 emif_pmcr_shdw_val;
	u32 emif_rd_wr_level_ramp_ctrl;
	u32 emif_rd_wr_exec_thresh;
	u32 emif_cos_config;
	u32 emif_priority_to_cos_mapping;
	u32 emif_connect_id_serv_1_map;
	u32 emif_connect_id_serv_2_map;
	u32 emif_ocp_config_val;
	u32 emif_lpddr2_nvm_tim;
	u32 emif_lpddr2_nvm_tim_shdw;
	u32 emif_dll_calib_ctrl_val;
	u32 emif_dll_calib_ctrl_val_shdw;
	u32 emif_ddr_phy_ctlr_1;
	u32 emif_ext_phy_ctrl_vals[120];
};

struct ti_emif_pm_data {
	void __iomem *ti_emif_base_addr_virt;
	phys_addr_t ti_emif_base_addr_phys;
	unsigned long ti_emif_sram_config;
	struct emif_regs_amx3 *regs_virt;
	phys_addr_t regs_phys;
} __packed __aligned(8);

struct ti_emif_pm_functions {
	u32 save_context;
	u32 restore_context;
	u32 enter_sr;
	u32 exit_sr;
	u32 abort_sr;
} __packed __aligned(8);

static inline void ti_emif_asm_offsets(void)
{
	DEFINE(EMIF_SDCFG_VAL_OFFSET,
	       offsetof(struct emif_regs_amx3, emif_sdcfg_val));
	DEFINE(EMIF_TIMING1_VAL_OFFSET,
	       offsetof(struct emif_regs_amx3, emif_timing1_val));
	DEFINE(EMIF_TIMING2_VAL_OFFSET,
	       offsetof(struct emif_regs_amx3, emif_timing2_val));
	DEFINE(EMIF_TIMING3_VAL_OFFSET,
	       offsetof(struct emif_regs_amx3, emif_timing3_val));
	DEFINE(EMIF_REF_CTRL_VAL_OFFSET,
	       offsetof(struct emif_regs_amx3, emif_ref_ctrl_val));
	DEFINE(EMIF_ZQCFG_VAL_OFFSET,
	       offsetof(struct emif_regs_amx3, emif_zqcfg_val));
	DEFINE(EMIF_PMCR_VAL_OFFSET,
	       offsetof(struct emif_regs_amx3, emif_pmcr_val));
	DEFINE(EMIF_PMCR_SHDW_VAL_OFFSET,
	       offsetof(struct emif_regs_amx3, emif_pmcr_shdw_val));
	DEFINE(EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET,
	       offsetof(struct emif_regs_amx3, emif_rd_wr_level_ramp_ctrl));
	DEFINE(EMIF_RD_WR_EXEC_THRESH_OFFSET,
	       offsetof(struct emif_regs_amx3, emif_rd_wr_exec_thresh));
	DEFINE(EMIF_COS_CONFIG_OFFSET,
	       offsetof(struct emif_regs_amx3, emif_cos_config));
	DEFINE(EMIF_PRIORITY_TO_COS_MAPPING_OFFSET,
	       offsetof(struct emif_regs_amx3, emif_priority_to_cos_mapping));
	DEFINE(EMIF_CONNECT_ID_SERV_1_MAP_OFFSET,
	       offsetof(struct emif_regs_amx3, emif_connect_id_serv_1_map));
	DEFINE(EMIF_CONNECT_ID_SERV_2_MAP_OFFSET,
	       offsetof(struct emif_regs_amx3, emif_connect_id_serv_2_map));
	DEFINE(EMIF_OCP_CONFIG_VAL_OFFSET,
	       offsetof(struct emif_regs_amx3, emif_ocp_config_val));
	DEFINE(EMIF_LPDDR2_NVM_TIM_OFFSET,
	       offsetof(struct emif_regs_amx3, emif_lpddr2_nvm_tim));
	DEFINE(EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET,
	       offsetof(struct emif_regs_amx3, emif_lpddr2_nvm_tim_shdw));
	DEFINE(EMIF_DLL_CALIB_CTRL_VAL_OFFSET,
	       offsetof(struct emif_regs_amx3, emif_dll_calib_ctrl_val));
	DEFINE(EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET,
	       offsetof(struct emif_regs_amx3, emif_dll_calib_ctrl_val_shdw));
	DEFINE(EMIF_DDR_PHY_CTLR_1_OFFSET,
	       offsetof(struct emif_regs_amx3, emif_ddr_phy_ctlr_1));
	DEFINE(EMIF_EXT_PHY_CTRL_VALS_OFFSET,
	       offsetof(struct emif_regs_amx3, emif_ext_phy_ctrl_vals));
	DEFINE(EMIF_REGS_AMX3_SIZE, sizeof(struct emif_regs_amx3));

	BLANK();

	DEFINE(EMIF_PM_BASE_ADDR_VIRT_OFFSET,
	       offsetof(struct ti_emif_pm_data, ti_emif_base_addr_virt));
	DEFINE(EMIF_PM_BASE_ADDR_PHYS_OFFSET,
	       offsetof(struct ti_emif_pm_data, ti_emif_base_addr_phys));
	DEFINE(EMIF_PM_CONFIG_OFFSET,
	       offsetof(struct ti_emif_pm_data, ti_emif_sram_config));
	DEFINE(EMIF_PM_REGS_VIRT_OFFSET,
	       offsetof(struct ti_emif_pm_data, regs_virt));
	DEFINE(EMIF_PM_REGS_PHYS_OFFSET,
	       offsetof(struct ti_emif_pm_data, regs_phys));
	DEFINE(EMIF_PM_DATA_SIZE, sizeof(struct ti_emif_pm_data));

	BLANK();

	DEFINE(EMIF_PM_SAVE_CONTEXT_OFFSET,
	       offsetof(struct ti_emif_pm_functions, save_context));
	DEFINE(EMIF_PM_RESTORE_CONTEXT_OFFSET,
	       offsetof(struct ti_emif_pm_functions, restore_context));
	DEFINE(EMIF_PM_ENTER_SR_OFFSET,
	       offsetof(struct ti_emif_pm_functions, enter_sr));
	DEFINE(EMIF_PM_EXIT_SR_OFFSET,
	       offsetof(struct ti_emif_pm_functions, exit_sr));
	DEFINE(EMIF_PM_ABORT_SR_OFFSET,
	       offsetof(struct ti_emif_pm_functions, abort_sr));
	DEFINE(EMIF_PM_FUNCTIONS_SIZE, sizeof(struct ti_emif_pm_functions));
}

struct gen_pool;

int ti_emif_copy_pm_function_table(struct gen_pool *sram_pool, void *dst);
int ti_emif_get_mem_type(void);

#endif
#endif /* __LINUX_TI_EMIF_H */
Commit	Line	Data
8428e5ad DG	1	/*
	2	* TI AM33XX EMIF Routines
	3	*
	4	* Copyright (C) 2016-2017 Texas Instruments Inc.
	5	* Dave Gerlach
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation version 2.
	10	*
	11	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	12	* kind, whether express or implied; without even the implied warranty
	13	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*/
	16	#ifndef __LINUX_TI_EMIF_H
	17	#define __LINUX_TI_EMIF_H
	18
	19	#include <linux/kbuild.h>
	20	#include <linux/types.h>
	21	#ifndef __ASSEMBLY__
	22
	23	struct emif_regs_amx3 {
	24	u32 emif_sdcfg_val;
	25	u32 emif_timing1_val;
	26	u32 emif_timing2_val;
	27	u32 emif_timing3_val;
	28	u32 emif_ref_ctrl_val;
	29	u32 emif_zqcfg_val;
	30	u32 emif_pmcr_val;
	31	u32 emif_pmcr_shdw_val;
	32	u32 emif_rd_wr_level_ramp_ctrl;
	33	u32 emif_rd_wr_exec_thresh;
	34	u32 emif_cos_config;
	35	u32 emif_priority_to_cos_mapping;
	36	u32 emif_connect_id_serv_1_map;
	37	u32 emif_connect_id_serv_2_map;
	38	u32 emif_ocp_config_val;
	39	u32 emif_lpddr2_nvm_tim;
	40	u32 emif_lpddr2_nvm_tim_shdw;
	41	u32 emif_dll_calib_ctrl_val;
	42	u32 emif_dll_calib_ctrl_val_shdw;
	43	u32 emif_ddr_phy_ctlr_1;
	44	u32 emif_ext_phy_ctrl_vals[120];
	45	};
	46
	47	struct ti_emif_pm_data {
	48	void __iomem *ti_emif_base_addr_virt;
	49	phys_addr_t ti_emif_base_addr_phys;
	50	unsigned long ti_emif_sram_config;
	51	struct emif_regs_amx3 *regs_virt;
	52	phys_addr_t regs_phys;
	53	} __packed __aligned(8);
	54
	55	struct ti_emif_pm_functions {
	56	u32 save_context;
	57	u32 restore_context;
	58	u32 enter_sr;
	59	u32 exit_sr;
	60	u32 abort_sr;
	61	} __packed __aligned(8);
	62
5692fcee DG	63	static inline void ti_emif_asm_offsets(void)
	64	{
	65	DEFINE(EMIF_SDCFG_VAL_OFFSET,
	66	offsetof(struct emif_regs_amx3, emif_sdcfg_val));
	67	DEFINE(EMIF_TIMING1_VAL_OFFSET,
	68	offsetof(struct emif_regs_amx3, emif_timing1_val));
	69	DEFINE(EMIF_TIMING2_VAL_OFFSET,
	70	offsetof(struct emif_regs_amx3, emif_timing2_val));
	71	DEFINE(EMIF_TIMING3_VAL_OFFSET,
	72	offsetof(struct emif_regs_amx3, emif_timing3_val));
	73	DEFINE(EMIF_REF_CTRL_VAL_OFFSET,
	74	offsetof(struct emif_regs_amx3, emif_ref_ctrl_val));
	75	DEFINE(EMIF_ZQCFG_VAL_OFFSET,
	76	offsetof(struct emif_regs_amx3, emif_zqcfg_val));
	77	DEFINE(EMIF_PMCR_VAL_OFFSET,
	78	offsetof(struct emif_regs_amx3, emif_pmcr_val));
	79	DEFINE(EMIF_PMCR_SHDW_VAL_OFFSET,
	80	offsetof(struct emif_regs_amx3, emif_pmcr_shdw_val));
	81	DEFINE(EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET,
	82	offsetof(struct emif_regs_amx3, emif_rd_wr_level_ramp_ctrl));
	83	DEFINE(EMIF_RD_WR_EXEC_THRESH_OFFSET,
	84	offsetof(struct emif_regs_amx3, emif_rd_wr_exec_thresh));
	85	DEFINE(EMIF_COS_CONFIG_OFFSET,
	86	offsetof(struct emif_regs_amx3, emif_cos_config));
	87	DEFINE(EMIF_PRIORITY_TO_COS_MAPPING_OFFSET,
	88	offsetof(struct emif_regs_amx3, emif_priority_to_cos_mapping));
	89	DEFINE(EMIF_CONNECT_ID_SERV_1_MAP_OFFSET,
	90	offsetof(struct emif_regs_amx3, emif_connect_id_serv_1_map));
	91	DEFINE(EMIF_CONNECT_ID_SERV_2_MAP_OFFSET,
	92	offsetof(struct emif_regs_amx3, emif_connect_id_serv_2_map));
	93	DEFINE(EMIF_OCP_CONFIG_VAL_OFFSET,
	94	offsetof(struct emif_regs_amx3, emif_ocp_config_val));
	95	DEFINE(EMIF_LPDDR2_NVM_TIM_OFFSET,
	96	offsetof(struct emif_regs_amx3, emif_lpddr2_nvm_tim));
	97	DEFINE(EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET,
	98	offsetof(struct emif_regs_amx3, emif_lpddr2_nvm_tim_shdw));
	99	DEFINE(EMIF_DLL_CALIB_CTRL_VAL_OFFSET,
	100	offsetof(struct emif_regs_amx3, emif_dll_calib_ctrl_val));
	101	DEFINE(EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET,
	102	offsetof(struct emif_regs_amx3, emif_dll_calib_ctrl_val_shdw));
	103	DEFINE(EMIF_DDR_PHY_CTLR_1_OFFSET,
	104	offsetof(struct emif_regs_amx3, emif_ddr_phy_ctlr_1));
	105	DEFINE(EMIF_EXT_PHY_CTRL_VALS_OFFSET,
	106	offsetof(struct emif_regs_amx3, emif_ext_phy_ctrl_vals));
	107	DEFINE(EMIF_REGS_AMX3_SIZE, sizeof(struct emif_regs_amx3));
	108
	109	BLANK();
	110
	111	DEFINE(EMIF_PM_BASE_ADDR_VIRT_OFFSET,
	112	offsetof(struct ti_emif_pm_data, ti_emif_base_addr_virt));
	113	DEFINE(EMIF_PM_BASE_ADDR_PHYS_OFFSET,
	114	offsetof(struct ti_emif_pm_data, ti_emif_base_addr_phys));
	115	DEFINE(EMIF_PM_CONFIG_OFFSET,
	116	offsetof(struct ti_emif_pm_data, ti_emif_sram_config));
	117	DEFINE(EMIF_PM_REGS_VIRT_OFFSET,
	118	offsetof(struct ti_emif_pm_data, regs_virt));
	119	DEFINE(EMIF_PM_REGS_PHYS_OFFSET,
	120	offsetof(struct ti_emif_pm_data, regs_phys));
	121	DEFINE(EMIF_PM_DATA_SIZE, sizeof(struct ti_emif_pm_data));
	122
	123	BLANK();
	124
	125	DEFINE(EMIF_PM_SAVE_CONTEXT_OFFSET,
	126	offsetof(struct ti_emif_pm_functions, save_context));
127	DEFINE(EMIF_PM_RESTORE_CONTEXT_OFFSET,
128	offsetof(struct ti_emif_pm_functions, restore_context));
129	DEFINE(EMIF_PM_ENTER_SR_OFFSET,
130	offsetof(struct ti_emif_pm_functions, enter_sr));
131	DEFINE(EMIF_PM_EXIT_SR_OFFSET,
132	offsetof(struct ti_emif_pm_functions, exit_sr));
133	DEFINE(EMIF_PM_ABORT_SR_OFFSET,
134	offsetof(struct ti_emif_pm_functions, abort_sr));
135	DEFINE(EMIF_PM_FUNCTIONS_SIZE, sizeof(struct ti_emif_pm_functions));
136	}
137
8428e5ad DG	138	struct gen_pool;
	139
	140	int ti_emif_copy_pm_function_table(struct gen_pool sram_pool, void dst);
	141	int ti_emif_get_mem_type(void);
	142
	143	#endif
	144	#endif /* __LINUX_TI_EMIF_H */