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ce1e3262 | 1 | /* |
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2 | * Copyright (c) 2010 Google, Inc |
3 | * | |
4 | * Author: | |
5 | * Colin Cross <ccross@google.com> | |
6 | * | |
7 | * This software is licensed under the terms of the GNU General Public | |
8 | * License version 2, as published by the Free Software Foundation, and | |
9 | * may be copied, distributed, and modified under those terms. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | */ | |
17 | ||
18 | #ifndef _MACH_TEGRA_POWERGATE_H_ | |
19 | #define _MACH_TEGRA_POWERGATE_H_ | |
20 | ||
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21 | struct clk; |
22 | ||
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23 | #define TEGRA_POWERGATE_CPU 0 |
24 | #define TEGRA_POWERGATE_3D 1 | |
25 | #define TEGRA_POWERGATE_VENC 2 | |
26 | #define TEGRA_POWERGATE_PCIE 3 | |
27 | #define TEGRA_POWERGATE_VDEC 4 | |
28 | #define TEGRA_POWERGATE_L2 5 | |
29 | #define TEGRA_POWERGATE_MPE 6 | |
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30 | #define TEGRA_POWERGATE_HEG 7 |
31 | #define TEGRA_POWERGATE_SATA 8 | |
32 | #define TEGRA_POWERGATE_CPU1 9 | |
33 | #define TEGRA_POWERGATE_CPU2 10 | |
34 | #define TEGRA_POWERGATE_CPU3 11 | |
35 | #define TEGRA_POWERGATE_CELP 12 | |
36 | #define TEGRA_POWERGATE_3D1 13 | |
37 | ||
38 | #define TEGRA_POWERGATE_CPU0 TEGRA_POWERGATE_CPU | |
39 | #define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D | |
ce1e3262 | 40 | |
6ac8cb5c | 41 | int tegra_powergate_is_powered(int id); |
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42 | int tegra_powergate_power_on(int id); |
43 | int tegra_powergate_power_off(int id); | |
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44 | int tegra_powergate_remove_clamping(int id); |
45 | ||
46 | /* Must be called with clk disabled, and returns with clk enabled */ | |
47 | int tegra_powergate_sequence_power_up(int id, struct clk *clk); | |
48 | ||
49 | #endif /* _MACH_TEGRA_POWERGATE_H_ */ |