[linux-block.git] / include / linux / switchtec.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Microsemi Switchtec PCIe Driver
 * Copyright (c) 2017, Microsemi Corporation
 */

#ifndef _SWITCHTEC_H
#define _SWITCHTEC_H

#include <linux/pci.h>
#include <linux/cdev.h>

#define SWITCHTEC_MRPC_PAYLOAD_SIZE 1024
#define SWITCHTEC_MAX_PFF_CSR 255

#define SWITCHTEC_EVENT_OCCURRED BIT(0)
#define SWITCHTEC_EVENT_CLEAR    BIT(0)
#define SWITCHTEC_EVENT_EN_LOG   BIT(1)
#define SWITCHTEC_EVENT_EN_CLI   BIT(2)
#define SWITCHTEC_EVENT_EN_IRQ   BIT(3)
#define SWITCHTEC_EVENT_FATAL    BIT(4)

#define SWITCHTEC_DMA_MRPC_EN	BIT(0)
enum {
	SWITCHTEC_GAS_MRPC_OFFSET       = 0x0000,
	SWITCHTEC_GAS_TOP_CFG_OFFSET    = 0x1000,
	SWITCHTEC_GAS_SW_EVENT_OFFSET   = 0x1800,
	SWITCHTEC_GAS_SYS_INFO_OFFSET   = 0x2000,
	SWITCHTEC_GAS_FLASH_INFO_OFFSET = 0x2200,
	SWITCHTEC_GAS_PART_CFG_OFFSET   = 0x4000,
	SWITCHTEC_GAS_NTB_OFFSET        = 0x10000,
	SWITCHTEC_GAS_PFF_CSR_OFFSET    = 0x134000,
};

enum switchtec_gen {
	SWITCHTEC_GEN3,
	SWITCHTEC_GEN4,
};

struct mrpc_regs {
	u8 input_data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
	u8 output_data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
	u32 cmd;
	u32 status;
	u32 ret_value;
	u32 dma_en;
	u64 dma_addr;
	u32 dma_vector;
	u32 dma_ver;
} __packed;

enum mrpc_status {
	SWITCHTEC_MRPC_STATUS_INPROGRESS = 1,
	SWITCHTEC_MRPC_STATUS_DONE = 2,
	SWITCHTEC_MRPC_STATUS_ERROR = 0xFF,
	SWITCHTEC_MRPC_STATUS_INTERRUPTED = 0x100,
};

struct sw_event_regs {
	u64 event_report_ctrl;
	u64 reserved1;
	u64 part_event_bitmap;
	u64 reserved2;
	u32 global_summary;
	u32 reserved3[3];
	u32 stack_error_event_hdr;
	u32 stack_error_event_data;
	u32 reserved4[4];
	u32 ppu_error_event_hdr;
	u32 ppu_error_event_data;
	u32 reserved5[4];
	u32 isp_error_event_hdr;
	u32 isp_error_event_data;
	u32 reserved6[4];
	u32 sys_reset_event_hdr;
	u32 reserved7[5];
	u32 fw_exception_hdr;
	u32 reserved8[5];
	u32 fw_nmi_hdr;
	u32 reserved9[5];
	u32 fw_non_fatal_hdr;
	u32 reserved10[5];
	u32 fw_fatal_hdr;
	u32 reserved11[5];
	u32 twi_mrpc_comp_hdr;
	u32 twi_mrpc_comp_data;
	u32 reserved12[4];
	u32 twi_mrpc_comp_async_hdr;
	u32 twi_mrpc_comp_async_data;
	u32 reserved13[4];
	u32 cli_mrpc_comp_hdr;
	u32 cli_mrpc_comp_data;
	u32 reserved14[4];
	u32 cli_mrpc_comp_async_hdr;
	u32 cli_mrpc_comp_async_data;
	u32 reserved15[4];
	u32 gpio_interrupt_hdr;
	u32 gpio_interrupt_data;
	u32 reserved16[4];
	u32 gfms_event_hdr;
	u32 gfms_event_data;
	u32 reserved17[4];
} __packed;

enum {
	SWITCHTEC_GEN3_CFG0_RUNNING = 0x04,
	SWITCHTEC_GEN3_CFG1_RUNNING = 0x05,
	SWITCHTEC_GEN3_IMG0_RUNNING = 0x03,
	SWITCHTEC_GEN3_IMG1_RUNNING = 0x07,
};

enum {
	SWITCHTEC_GEN4_MAP0_RUNNING = 0x00,
	SWITCHTEC_GEN4_MAP1_RUNNING = 0x01,
	SWITCHTEC_GEN4_KEY0_RUNNING = 0x02,
	SWITCHTEC_GEN4_KEY1_RUNNING = 0x03,
	SWITCHTEC_GEN4_BL2_0_RUNNING = 0x04,
	SWITCHTEC_GEN4_BL2_1_RUNNING = 0x05,
	SWITCHTEC_GEN4_CFG0_RUNNING = 0x06,
	SWITCHTEC_GEN4_CFG1_RUNNING = 0x07,
	SWITCHTEC_GEN4_IMG0_RUNNING = 0x08,
	SWITCHTEC_GEN4_IMG1_RUNNING = 0x09,
};

enum {
	SWITCHTEC_GEN4_KEY0_ACTIVE = 0,
	SWITCHTEC_GEN4_KEY1_ACTIVE = 1,
	SWITCHTEC_GEN4_BL2_0_ACTIVE = 0,
	SWITCHTEC_GEN4_BL2_1_ACTIVE = 1,
	SWITCHTEC_GEN4_CFG0_ACTIVE = 0,
	SWITCHTEC_GEN4_CFG1_ACTIVE = 1,
	SWITCHTEC_GEN4_IMG0_ACTIVE = 0,
	SWITCHTEC_GEN4_IMG1_ACTIVE = 1,
};

struct sys_info_regs_gen3 {
	u32 reserved1;
	u32 vendor_table_revision;
	u32 table_format_version;
	u32 partition_id;
	u32 cfg_file_fmt_version;
	u16 cfg_running;
	u16 img_running;
	u32 reserved2[57];
	char vendor_id[8];
	char product_id[16];
	char product_revision[4];
	char component_vendor[8];
	u16 component_id;
	u8 component_revision;
} __packed;

struct sys_info_regs_gen4 {
	u16 gas_layout_ver;
	u8 evlist_ver;
	u8 reserved1;
	u16 mgmt_cmd_set_ver;
	u16 fabric_cmd_set_ver;
	u32 reserved2[2];
	u8 mrpc_uart_ver;
	u8 mrpc_twi_ver;
	u8 mrpc_eth_ver;
	u8 mrpc_inband_ver;
	u32 reserved3[7];
	u32 fw_update_tmo;
	u32 xml_version_cfg;
	u32 xml_version_img;
	u32 partition_id;
	u16 bl2_running;
	u16 cfg_running;
	u16 img_running;
	u16 key_running;
	u32 reserved4[43];
	u32 vendor_seeprom_twi;
	u32 vendor_table_revision;
	u32 vendor_specific_info[2];
	u16 p2p_vendor_id;
	u16 p2p_device_id;
	u8 p2p_revision_id;
	u8 reserved5[3];
	u32 p2p_class_id;
	u16 subsystem_vendor_id;
	u16 subsystem_id;
	u32 p2p_serial_number[2];
	u8 mac_addr[6];
	u8 reserved6[2];
	u32 reserved7[3];
	char vendor_id[8];
	char product_id[24];
	char  product_revision[2];
	u16 reserved8;
} __packed;

struct sys_info_regs {
	u32 device_id;
	u32 device_version;
	u32 firmware_version;
	union {
		struct sys_info_regs_gen3 gen3;
		struct sys_info_regs_gen4 gen4;
	};
} __packed;

struct partition_info {
	u32 address;
	u32 length;
};

struct flash_info_regs_gen3 {
	u32 flash_part_map_upd_idx;

	struct active_partition_info_gen3 {
		u32 address;
		u32 build_version;
		u32 build_string;
	} active_img;

	struct active_partition_info_gen3 active_cfg;
	struct active_partition_info_gen3 inactive_img;
	struct active_partition_info_gen3 inactive_cfg;

	u32 flash_length;

	struct partition_info cfg0;
	struct partition_info cfg1;
	struct partition_info img0;
	struct partition_info img1;
	struct partition_info nvlog;
	struct partition_info vendor[8];
};

struct flash_info_regs_gen4 {
	u32 flash_address;
	u32 flash_length;

	struct active_partition_info_gen4 {
		unsigned char bl2;
		unsigned char cfg;
		unsigned char img;
		unsigned char key;
	} active_flag;

	u32 reserved[3];

	struct partition_info map0;
	struct partition_info map1;
	struct partition_info key0;
	struct partition_info key1;
	struct partition_info bl2_0;
	struct partition_info bl2_1;
	struct partition_info cfg0;
	struct partition_info cfg1;
	struct partition_info img0;
	struct partition_info img1;
	struct partition_info nvlog;
	struct partition_info vendor[8];
};

struct flash_info_regs {
	union {
		struct flash_info_regs_gen3 gen3;
		struct flash_info_regs_gen4 gen4;
	};
};

enum {
	SWITCHTEC_NTB_REG_INFO_OFFSET   = 0x0000,
	SWITCHTEC_NTB_REG_CTRL_OFFSET   = 0x4000,
	SWITCHTEC_NTB_REG_DBMSG_OFFSET  = 0x64000,
};

struct ntb_info_regs {
	u8  partition_count;
	u8  partition_id;
	u16 reserved1;
	u64 ep_map;
	u16 requester_id;
	u16 reserved2;
	u32 reserved3[4];
	struct nt_partition_info {
		u32 xlink_enabled;
		u32 target_part_low;
		u32 target_part_high;
		u32 reserved;
	} ntp_info[48];
} __packed;

struct part_cfg_regs {
	u32 status;
	u32 state;
	u32 port_cnt;
	u32 usp_port_mode;
	u32 usp_pff_inst_id;
	u32 vep_pff_inst_id;
	u32 dsp_pff_inst_id[47];
	u32 reserved1[11];
	u16 vep_vector_number;
	u16 usp_vector_number;
	u32 port_event_bitmap;
	u32 reserved2[3];
	u32 part_event_summary;
	u32 reserved3[3];
	u32 part_reset_hdr;
	u32 part_reset_data[5];
	u32 mrpc_comp_hdr;
	u32 mrpc_comp_data[5];
	u32 mrpc_comp_async_hdr;
	u32 mrpc_comp_async_data[5];
	u32 dyn_binding_hdr;
	u32 dyn_binding_data[5];
	u32 intercomm_notify_hdr;
	u32 intercomm_notify_data[5];
	u32 reserved4[153];
} __packed;

enum {
	NTB_CTRL_PART_OP_LOCK = 0x1,
	NTB_CTRL_PART_OP_CFG = 0x2,
	NTB_CTRL_PART_OP_RESET = 0x3,

	NTB_CTRL_PART_STATUS_NORMAL = 0x1,
	NTB_CTRL_PART_STATUS_LOCKED = 0x2,
	NTB_CTRL_PART_STATUS_LOCKING = 0x3,
	NTB_CTRL_PART_STATUS_CONFIGURING = 0x4,
	NTB_CTRL_PART_STATUS_RESETTING = 0x5,

	NTB_CTRL_BAR_VALID = 1 << 0,
	NTB_CTRL_BAR_DIR_WIN_EN = 1 << 4,
	NTB_CTRL_BAR_LUT_WIN_EN = 1 << 5,

	NTB_CTRL_REQ_ID_EN = 1 << 0,

	NTB_CTRL_LUT_EN = 1 << 0,

	NTB_PART_CTRL_ID_PROT_DIS = 1 << 0,
};

struct ntb_ctrl_regs {
	u32 partition_status;
	u32 partition_op;
	u32 partition_ctrl;
	u32 bar_setup;
	u32 bar_error;
	u16 lut_table_entries;
	u16 lut_table_offset;
	u32 lut_error;
	u16 req_id_table_size;
	u16 req_id_table_offset;
	u32 req_id_error;
	u32 reserved1[7];
	struct {
		u32 ctl;
		u32 win_size;
		u64 xlate_addr;
	} bar_entry[6];
	struct {
		u32 win_size;
		u32 reserved[3];
	} bar_ext_entry[6];
	u32 reserved2[192];
	u32 req_id_table[512];
	u32 reserved3[256];
	u64 lut_entry[512];
} __packed;

#define NTB_DBMSG_IMSG_STATUS BIT_ULL(32)
#define NTB_DBMSG_IMSG_MASK   BIT_ULL(40)

struct ntb_dbmsg_regs {
	u32 reserved1[1024];
	u64 odb;
	u64 odb_mask;
	u64 idb;
	u64 idb_mask;
	u8  idb_vec_map[64];
	u32 msg_map;
	u32 reserved2;
	struct {
		u32 msg;
		u32 status;
	} omsg[4];

	struct {
		u32 msg;
		u8  status;
		u8  mask;
		u8  src;
		u8  reserved;
	} imsg[4];

	u8 reserved3[3928];
	u8 msix_table[1024];
	u8 reserved4[3072];
	u8 pba[24];
	u8 reserved5[4072];
} __packed;

enum {
	SWITCHTEC_PART_CFG_EVENT_RESET = 1 << 0,
	SWITCHTEC_PART_CFG_EVENT_MRPC_CMP = 1 << 1,
	SWITCHTEC_PART_CFG_EVENT_MRPC_ASYNC_CMP = 1 << 2,
	SWITCHTEC_PART_CFG_EVENT_DYN_PART_CMP = 1 << 3,
};

struct pff_csr_regs {
	u16 vendor_id;
	u16 device_id;
	u16 pcicmd;
	u16 pcists;
	u32 pci_class;
	u32 pci_opts;
	union {
		u32 pci_bar[6];
		u64 pci_bar64[3];
	};
	u32 pci_cardbus;
	u32 pci_subsystem_id;
	u32 pci_expansion_rom;
	u32 pci_cap_ptr;
	u32 reserved1;
	u32 pci_irq;
	u32 pci_cap_region[48];
	u32 pcie_cap_region[448];
	u32 indirect_gas_window[128];
	u32 indirect_gas_window_off;
	u32 reserved[127];
	u32 pff_event_summary;
	u32 reserved2[3];
	u32 aer_in_p2p_hdr;
	u32 aer_in_p2p_data[5];
	u32 aer_in_vep_hdr;
	u32 aer_in_vep_data[5];
	u32 dpc_hdr;
	u32 dpc_data[5];
	u32 cts_hdr;
	u32 cts_data[5];
	u32 uec_hdr;
	u32 uec_data[5];
	u32 hotplug_hdr;
	u32 hotplug_data[5];
	u32 ier_hdr;
	u32 ier_data[5];
	u32 threshold_hdr;
	u32 threshold_data[5];
	u32 power_mgmt_hdr;
	u32 power_mgmt_data[5];
	u32 tlp_throttling_hdr;
	u32 tlp_throttling_data[5];
	u32 force_speed_hdr;
	u32 force_speed_data[5];
	u32 credit_timeout_hdr;
	u32 credit_timeout_data[5];
	u32 link_state_hdr;
	u32 link_state_data[5];
	u32 reserved4[174];
} __packed;

struct switchtec_ntb;

struct dma_mrpc_output {
	u32 status;
	u32 cmd_id;
	u32 rtn_code;
	u32 output_size;
	u8 data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
};

struct switchtec_dev {
	struct pci_dev *pdev;
	struct device dev;
	struct cdev cdev;

	enum switchtec_gen gen;

	int partition;
	int partition_count;
	int pff_csr_count;
	char pff_local[SWITCHTEC_MAX_PFF_CSR];

	void __iomem *mmio;
	struct mrpc_regs __iomem *mmio_mrpc;
	struct sw_event_regs __iomem *mmio_sw_event;
	struct sys_info_regs __iomem *mmio_sys_info;
	struct flash_info_regs __iomem *mmio_flash_info;
	struct ntb_info_regs __iomem *mmio_ntb;
	struct part_cfg_regs __iomem *mmio_part_cfg;
	struct part_cfg_regs __iomem *mmio_part_cfg_all;
	struct pff_csr_regs __iomem *mmio_pff_csr;

	/*
	 * The mrpc mutex must be held when accessing the other
	 * mrpc_ fields, alive flag and stuser->state field
	 */
	struct mutex mrpc_mutex;
	struct list_head mrpc_queue;
	int mrpc_busy;
	struct work_struct mrpc_work;
	struct delayed_work mrpc_timeout;
	bool alive;

	wait_queue_head_t event_wq;
	atomic_t event_cnt;

	struct work_struct link_event_work;
	void (*link_notifier)(struct switchtec_dev *stdev);
	u8 link_event_count[SWITCHTEC_MAX_PFF_CSR];

	struct switchtec_ntb *sndev;

	struct dma_mrpc_output *dma_mrpc;
	dma_addr_t dma_mrpc_dma_addr;
};

static inline struct switchtec_dev *to_stdev(struct device *dev)
{
	return container_of(dev, struct switchtec_dev, dev);
}

extern struct class *switchtec_class;

#endif
Commit	Line	Data
2025cf9e	1	/* SPDX-License-Identifier: GPL-2.0-only */
5a1c269f LG	2	/*
	3	* Microsemi Switchtec PCIe Driver
	4	* Copyright (c) 2017, Microsemi Corporation
5a1c269f LG	5	*/
	6
	7	#ifndef _SWITCHTEC_H
	8	#define _SWITCHTEC_H
	9
	10	#include <linux/pci.h>
	11	#include <linux/cdev.h>
	12
5a1c269f	13	#define SWITCHTEC_MRPC_PAYLOAD_SIZE 1024
ba8a3982	14	#define SWITCHTEC_MAX_PFF_CSR 255
5a1c269f LG	15
	16	#define SWITCHTEC_EVENT_OCCURRED BIT(0)
	17	#define SWITCHTEC_EVENT_CLEAR BIT(0)
	18	#define SWITCHTEC_EVENT_EN_LOG BIT(1)
	19	#define SWITCHTEC_EVENT_EN_CLI BIT(2)
	20	#define SWITCHTEC_EVENT_EN_IRQ BIT(3)
	21	#define SWITCHTEC_EVENT_FATAL BIT(4)
	22
f7eb7b8a	23	#define SWITCHTEC_DMA_MRPC_EN BIT(0)
5a1c269f LG	24	enum {
	25	SWITCHTEC_GAS_MRPC_OFFSET = 0x0000,
	26	SWITCHTEC_GAS_TOP_CFG_OFFSET = 0x1000,
	27	SWITCHTEC_GAS_SW_EVENT_OFFSET = 0x1800,
	28	SWITCHTEC_GAS_SYS_INFO_OFFSET = 0x2000,
	29	SWITCHTEC_GAS_FLASH_INFO_OFFSET = 0x2200,
	30	SWITCHTEC_GAS_PART_CFG_OFFSET = 0x4000,
	31	SWITCHTEC_GAS_NTB_OFFSET = 0x10000,
	32	SWITCHTEC_GAS_PFF_CSR_OFFSET = 0x134000,
	33	};
	34
b13313a0 LG	35	enum switchtec_gen {
b13313a0 LG	36	SWITCHTEC_GEN3,
a3321ca3	37	SWITCHTEC_GEN4,
b13313a0 LG	38	};
b13313a0 LG	39
5a1c269f LG	40	struct mrpc_regs {
	41	u8 input_data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
	42	u8 output_data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
	43	u32 cmd;
	44	u32 status;
	45	u32 ret_value;
f7eb7b8a WS	46	u32 dma_en;
	47	u64 dma_addr;
	48	u32 dma_vector;
	49	u32 dma_ver;
5a1c269f LG	50	} __packed;
	51
	52	enum mrpc_status {
	53	SWITCHTEC_MRPC_STATUS_INPROGRESS = 1,
	54	SWITCHTEC_MRPC_STATUS_DONE = 2,
	55	SWITCHTEC_MRPC_STATUS_ERROR = 0xFF,
	56	SWITCHTEC_MRPC_STATUS_INTERRUPTED = 0x100,
	57	};
	58
	59	struct sw_event_regs {
	60	u64 event_report_ctrl;
	61	u64 reserved1;
	62	u64 part_event_bitmap;
	63	u64 reserved2;
	64	u32 global_summary;
	65	u32 reserved3[3];
	66	u32 stack_error_event_hdr;
	67	u32 stack_error_event_data;
	68	u32 reserved4[4];
	69	u32 ppu_error_event_hdr;
	70	u32 ppu_error_event_data;
	71	u32 reserved5[4];
	72	u32 isp_error_event_hdr;
	73	u32 isp_error_event_data;
	74	u32 reserved6[4];
	75	u32 sys_reset_event_hdr;
	76	u32 reserved7[5];
	77	u32 fw_exception_hdr;
	78	u32 reserved8[5];
	79	u32 fw_nmi_hdr;
	80	u32 reserved9[5];
	81	u32 fw_non_fatal_hdr;
	82	u32 reserved10[5];
	83	u32 fw_fatal_hdr;
	84	u32 reserved11[5];
	85	u32 twi_mrpc_comp_hdr;
	86	u32 twi_mrpc_comp_data;
	87	u32 reserved12[4];
	88	u32 twi_mrpc_comp_async_hdr;
	89	u32 twi_mrpc_comp_async_data;
	90	u32 reserved13[4];
	91	u32 cli_mrpc_comp_hdr;
	92	u32 cli_mrpc_comp_data;
	93	u32 reserved14[4];
	94	u32 cli_mrpc_comp_async_hdr;
	95	u32 cli_mrpc_comp_async_data;
	96	u32 reserved15[4];
	97	u32 gpio_interrupt_hdr;
	98	u32 gpio_interrupt_data;
	99	u32 reserved16[4];
f0edce7a LG	100	u32 gfms_event_hdr;
	101	u32 gfms_event_data;
	102	u32 reserved17[4];
5a1c269f LG	103	} __packed;
	104
	105	enum {
fcccd282 LG	106	SWITCHTEC_GEN3_CFG0_RUNNING = 0x04,
	107	SWITCHTEC_GEN3_CFG1_RUNNING = 0x05,
	108	SWITCHTEC_GEN3_IMG0_RUNNING = 0x03,
	109	SWITCHTEC_GEN3_IMG1_RUNNING = 0x07,
5a1c269f LG	110	};
5a1c269f LG	111
4efa1d2e KC	112	enum {
	113	SWITCHTEC_GEN4_MAP0_RUNNING = 0x00,
	114	SWITCHTEC_GEN4_MAP1_RUNNING = 0x01,
	115	SWITCHTEC_GEN4_KEY0_RUNNING = 0x02,
	116	SWITCHTEC_GEN4_KEY1_RUNNING = 0x03,
	117	SWITCHTEC_GEN4_BL2_0_RUNNING = 0x04,
	118	SWITCHTEC_GEN4_BL2_1_RUNNING = 0x05,
	119	SWITCHTEC_GEN4_CFG0_RUNNING = 0x06,
	120	SWITCHTEC_GEN4_CFG1_RUNNING = 0x07,
	121	SWITCHTEC_GEN4_IMG0_RUNNING = 0x08,
	122	SWITCHTEC_GEN4_IMG1_RUNNING = 0x09,
	123	};
	124
	125	enum {
	126	SWITCHTEC_GEN4_KEY0_ACTIVE = 0,
	127	SWITCHTEC_GEN4_KEY1_ACTIVE = 1,
	128	SWITCHTEC_GEN4_BL2_0_ACTIVE = 0,
	129	SWITCHTEC_GEN4_BL2_1_ACTIVE = 1,
	130	SWITCHTEC_GEN4_CFG0_ACTIVE = 0,
	131	SWITCHTEC_GEN4_CFG1_ACTIVE = 1,
	132	SWITCHTEC_GEN4_IMG0_ACTIVE = 0,
	133	SWITCHTEC_GEN4_IMG1_ACTIVE = 1,
	134	};
	135
993d208d	136	struct sys_info_regs_gen3 {
5a1c269f LG	137	u32 reserved1;
	138	u32 vendor_table_revision;
	139	u32 table_format_version;
	140	u32 partition_id;
	141	u32 cfg_file_fmt_version;
	142	u16 cfg_running;
	143	u16 img_running;
	144	u32 reserved2[57];
	145	char vendor_id[8];
	146	char product_id[16];
	147	char product_revision[4];
	148	char component_vendor[8];
	149	u16 component_id;
	150	u8 component_revision;
	151	} __packed;
	152
a3321ca3 LG	153	struct sys_info_regs_gen4 {
	154	u16 gas_layout_ver;
	155	u8 evlist_ver;
	156	u8 reserved1;
	157	u16 mgmt_cmd_set_ver;
	158	u16 fabric_cmd_set_ver;
	159	u32 reserved2[2];
	160	u8 mrpc_uart_ver;
	161	u8 mrpc_twi_ver;
	162	u8 mrpc_eth_ver;
	163	u8 mrpc_inband_ver;
	164	u32 reserved3[7];
	165	u32 fw_update_tmo;
	166	u32 xml_version_cfg;
	167	u32 xml_version_img;
	168	u32 partition_id;
	169	u16 bl2_running;
	170	u16 cfg_running;
	171	u16 img_running;
	172	u16 key_running;
	173	u32 reserved4[43];
	174	u32 vendor_seeprom_twi;
	175	u32 vendor_table_revision;
	176	u32 vendor_specific_info[2];
	177	u16 p2p_vendor_id;
	178	u16 p2p_device_id;
	179	u8 p2p_revision_id;
	180	u8 reserved5[3];
	181	u32 p2p_class_id;
	182	u16 subsystem_vendor_id;
	183	u16 subsystem_id;
	184	u32 p2p_serial_number[2];
	185	u8 mac_addr[6];
	186	u8 reserved6[2];
	187	u32 reserved7[3];
	188	char vendor_id[8];
	189	char product_id[24];
	190	char product_revision[2];
	191	u16 reserved8;
	192	} __packed;
	193
993d208d LG	194	struct sys_info_regs {
	195	u32 device_id;
	196	u32 device_version;
	197	u32 firmware_version;
	198	union {
	199	struct sys_info_regs_gen3 gen3;
a3321ca3	200	struct sys_info_regs_gen4 gen4;
993d208d LG	201	};
	202	} __packed;
	203
	204	struct partition_info {
	205	u32 address;
	206	u32 length;
	207	};
	208
	209	struct flash_info_regs_gen3 {
5a1c269f LG	210	u32 flash_part_map_upd_idx;
5a1c269f LG	211
993d208d	212	struct active_partition_info_gen3 {
5a1c269f LG	213	u32 address;
	214	u32 build_version;
	215	u32 build_string;
	216	} active_img;
	217
993d208d LG	218	struct active_partition_info_gen3 active_cfg;
	219	struct active_partition_info_gen3 inactive_img;
	220	struct active_partition_info_gen3 inactive_cfg;
5a1c269f LG	221
	222	u32 flash_length;
	223
993d208d	224	struct partition_info cfg0;
5a1c269f LG	225	struct partition_info cfg1;
	226	struct partition_info img0;
	227	struct partition_info img1;
	228	struct partition_info nvlog;
	229	struct partition_info vendor[8];
	230	};
	231
4efa1d2e KC	232	struct flash_info_regs_gen4 {
	233	u32 flash_address;
	234	u32 flash_length;
	235
	236	struct active_partition_info_gen4 {
	237	unsigned char bl2;
	238	unsigned char cfg;
	239	unsigned char img;
	240	unsigned char key;
	241	} active_flag;
	242
	243	u32 reserved[3];
	244
	245	struct partition_info map0;
	246	struct partition_info map1;
	247	struct partition_info key0;
	248	struct partition_info key1;
	249	struct partition_info bl2_0;
	250	struct partition_info bl2_1;
	251	struct partition_info cfg0;
	252	struct partition_info cfg1;
	253	struct partition_info img0;
	254	struct partition_info img1;
	255	struct partition_info nvlog;
	256	struct partition_info vendor[8];
	257	};
	258
993d208d LG	259	struct flash_info_regs {
	260	union {
	261	struct flash_info_regs_gen3 gen3;
4efa1d2e	262	struct flash_info_regs_gen4 gen4;
993d208d LG	263	};
	264	};
	265
c082b04c LG	266	enum {
	267	SWITCHTEC_NTB_REG_INFO_OFFSET = 0x0000,
	268	SWITCHTEC_NTB_REG_CTRL_OFFSET = 0x4000,
	269	SWITCHTEC_NTB_REG_DBMSG_OFFSET = 0x64000,
	270	};
	271
5a1c269f LG	272	struct ntb_info_regs {
	273	u8 partition_count;
	274	u8 partition_id;
	275	u16 reserved1;
	276	u64 ep_map;
	277	u16 requester_id;
3df54c87 KC	278	u16 reserved2;
	279	u32 reserved3[4];
	280	struct nt_partition_info {
	281	u32 xlink_enabled;
	282	u32 target_part_low;
	283	u32 target_part_high;
	284	u32 reserved;
	285	} ntp_info[48];
5a1c269f LG	286	} __packed;
	287
	288	struct part_cfg_regs {
	289	u32 status;
	290	u32 state;
	291	u32 port_cnt;
	292	u32 usp_port_mode;
	293	u32 usp_pff_inst_id;
	294	u32 vep_pff_inst_id;
	295	u32 dsp_pff_inst_id[47];
	296	u32 reserved1[11];
	297	u16 vep_vector_number;
	298	u16 usp_vector_number;
	299	u32 port_event_bitmap;
	300	u32 reserved2[3];
	301	u32 part_event_summary;
	302	u32 reserved3[3];
	303	u32 part_reset_hdr;
	304	u32 part_reset_data[5];
	305	u32 mrpc_comp_hdr;
	306	u32 mrpc_comp_data[5];
	307	u32 mrpc_comp_async_hdr;
	308	u32 mrpc_comp_async_data[5];
	309	u32 dyn_binding_hdr;
	310	u32 dyn_binding_data[5];
a6b0ef9a LG	311	u32 intercomm_notify_hdr;
	312	u32 intercomm_notify_data[5];
	313	u32 reserved4[153];
5a1c269f LG	314	} __packed;
5a1c269f LG	315
c082b04c LG	316	enum {
	317	NTB_CTRL_PART_OP_LOCK = 0x1,
	318	NTB_CTRL_PART_OP_CFG = 0x2,
	319	NTB_CTRL_PART_OP_RESET = 0x3,
	320
	321	NTB_CTRL_PART_STATUS_NORMAL = 0x1,
	322	NTB_CTRL_PART_STATUS_LOCKED = 0x2,
	323	NTB_CTRL_PART_STATUS_LOCKING = 0x3,
	324	NTB_CTRL_PART_STATUS_CONFIGURING = 0x4,
	325	NTB_CTRL_PART_STATUS_RESETTING = 0x5,
	326
	327	NTB_CTRL_BAR_VALID = 1 << 0,
	328	NTB_CTRL_BAR_DIR_WIN_EN = 1 << 4,
	329	NTB_CTRL_BAR_LUT_WIN_EN = 1 << 5,
	330
	331	NTB_CTRL_REQ_ID_EN = 1 << 0,
	332
	333	NTB_CTRL_LUT_EN = 1 << 0,
	334
	335	NTB_PART_CTRL_ID_PROT_DIS = 1 << 0,
	336	};
	337
	338	struct ntb_ctrl_regs {
	339	u32 partition_status;
	340	u32 partition_op;
	341	u32 partition_ctrl;
	342	u32 bar_setup;
	343	u32 bar_error;
	344	u16 lut_table_entries;
	345	u16 lut_table_offset;
	346	u32 lut_error;
	347	u16 req_id_table_size;
	348	u16 req_id_table_offset;
	349	u32 req_id_error;
	350	u32 reserved1[7];
	351	struct {
	352	u32 ctl;
	353	u32 win_size;
	354	u64 xlate_addr;
	355	} bar_entry[6];
a2585cdc PS	356	struct {
	357	u32 win_size;
	358	u32 reserved[3];
	359	} bar_ext_entry[6];
	360	u32 reserved2[192];
d123fab7 WS	361	u32 req_id_table[512];
d123fab7 WS	362	u32 reserved3[256];
c082b04c LG	363	u64 lut_entry[512];
	364	} __packed;
	365
	366	#define NTB_DBMSG_IMSG_STATUS BIT_ULL(32)
	367	#define NTB_DBMSG_IMSG_MASK BIT_ULL(40)
	368
	369	struct ntb_dbmsg_regs {
	370	u32 reserved1[1024];
	371	u64 odb;
	372	u64 odb_mask;
	373	u64 idb;
	374	u64 idb_mask;
	375	u8 idb_vec_map[64];
	376	u32 msg_map;
	377	u32 reserved2;
	378	struct {
	379	u32 msg;
	380	u32 status;
	381	} omsg[4];
	382
	383	struct {
	384	u32 msg;
	385	u8 status;
	386	u8 mask;
	387	u8 src;
	388	u8 reserved;
	389	} imsg[4];
	390
	391	u8 reserved3[3928];
	392	u8 msix_table[1024];
	393	u8 reserved4[3072];
	394	u8 pba[24];
	395	u8 reserved5[4072];
	396	} __packed;
	397
5a1c269f LG	398	enum {
	399	SWITCHTEC_PART_CFG_EVENT_RESET = 1 << 0,
	400	SWITCHTEC_PART_CFG_EVENT_MRPC_CMP = 1 << 1,
	401	SWITCHTEC_PART_CFG_EVENT_MRPC_ASYNC_CMP = 1 << 2,
	402	SWITCHTEC_PART_CFG_EVENT_DYN_PART_CMP = 1 << 3,
	403	};
	404
	405	struct pff_csr_regs {
	406	u16 vendor_id;
	407	u16 device_id;
45f447de LG	408	u16 pcicmd;
	409	u16 pcists;
	410	u32 pci_class;
	411	u32 pci_opts;
	412	union {
	413	u32 pci_bar[6];
	414	u64 pci_bar64[3];
	415	};
	416	u32 pci_cardbus;
	417	u32 pci_subsystem_id;
	418	u32 pci_expansion_rom;
	419	u32 pci_cap_ptr;
	420	u32 reserved1;
	421	u32 pci_irq;
5a1c269f LG	422	u32 pci_cap_region[48];
	423	u32 pcie_cap_region[448];
	424	u32 indirect_gas_window[128];
	425	u32 indirect_gas_window_off;
	426	u32 reserved[127];
	427	u32 pff_event_summary;
	428	u32 reserved2[3];
	429	u32 aer_in_p2p_hdr;
	430	u32 aer_in_p2p_data[5];
	431	u32 aer_in_vep_hdr;
	432	u32 aer_in_vep_data[5];
	433	u32 dpc_hdr;
	434	u32 dpc_data[5];
	435	u32 cts_hdr;
	436	u32 cts_data[5];
a6b0ef9a LG	437	u32 uec_hdr;
a6b0ef9a LG	438	u32 uec_data[5];
5a1c269f LG	439	u32 hotplug_hdr;
	440	u32 hotplug_data[5];
	441	u32 ier_hdr;
	442	u32 ier_data[5];
	443	u32 threshold_hdr;
	444	u32 threshold_data[5];
	445	u32 power_mgmt_hdr;
	446	u32 power_mgmt_data[5];
	447	u32 tlp_throttling_hdr;
	448	u32 tlp_throttling_data[5];
	449	u32 force_speed_hdr;
	450	u32 force_speed_data[5];
	451	u32 credit_timeout_hdr;
	452	u32 credit_timeout_data[5];
	453	u32 link_state_hdr;
	454	u32 link_state_data[5];
	455	u32 reserved4[174];
	456	} __packed;
	457
33dea5aa LG	458	struct switchtec_ntb;
33dea5aa LG	459
f7eb7b8a WS	460	struct dma_mrpc_output {
	461	u32 status;
	462	u32 cmd_id;
	463	u32 rtn_code;
	464	u32 output_size;
	465	u8 data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
	466	};
	467
5a1c269f LG	468	struct switchtec_dev {
	469	struct pci_dev *pdev;
	470	struct device dev;
	471	struct cdev cdev;
	472
b13313a0 LG	473	enum switchtec_gen gen;
b13313a0 LG	474
5a1c269f LG	475	int partition;
	476	int partition_count;
	477	int pff_csr_count;
	478	char pff_local[SWITCHTEC_MAX_PFF_CSR];
	479
	480	void __iomem *mmio;
	481	struct mrpc_regs __iomem *mmio_mrpc;
	482	struct sw_event_regs __iomem *mmio_sw_event;
	483	struct sys_info_regs __iomem *mmio_sys_info;
	484	struct flash_info_regs __iomem *mmio_flash_info;
	485	struct ntb_info_regs __iomem *mmio_ntb;
	486	struct part_cfg_regs __iomem *mmio_part_cfg;
	487	struct part_cfg_regs __iomem *mmio_part_cfg_all;
	488	struct pff_csr_regs __iomem *mmio_pff_csr;
	489
	490	/*
	491	* The mrpc mutex must be held when accessing the other
	492	* mrpc_ fields, alive flag and stuser->state field
	493	*/
	494	struct mutex mrpc_mutex;
	495	struct list_head mrpc_queue;
	496	int mrpc_busy;
	497	struct work_struct mrpc_work;
	498	struct delayed_work mrpc_timeout;
	499	bool alive;
	500
	501	wait_queue_head_t event_wq;
	502	atomic_t event_cnt;
48c302dc LG	503
	504	struct work_struct link_event_work;
	505	void (link_notifier)(struct switchtec_dev stdev);
	506	u8 link_event_count[SWITCHTEC_MAX_PFF_CSR];
33dea5aa LG	507
33dea5aa LG	508	struct switchtec_ntb *sndev;
f7eb7b8a WS	509
	510	struct dma_mrpc_output *dma_mrpc;
	511	dma_addr_t dma_mrpc_dma_addr;
5a1c269f LG	512	};
	513
	514	static inline struct switchtec_dev to_stdev(struct device dev)
	515	{
	516	return container_of(dev, struct switchtec_dev, dev);
	517	}
	518
302e994d LG	519	extern struct class *switchtec_class;
302e994d LG	520
5a1c269f	521	#endif