[linux-2.6-block.git] / include / linux / switchtec.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Microsemi Switchtec PCIe Driver
 * Copyright (c) 2017, Microsemi Corporation
 */

#ifndef _SWITCHTEC_H
#define _SWITCHTEC_H

#include <linux/pci.h>
#include <linux/cdev.h>

#define SWITCHTEC_MRPC_PAYLOAD_SIZE 1024
#define SWITCHTEC_MAX_PFF_CSR 255

#define SWITCHTEC_EVENT_OCCURRED BIT(0)
#define SWITCHTEC_EVENT_CLEAR    BIT(0)
#define SWITCHTEC_EVENT_EN_LOG   BIT(1)
#define SWITCHTEC_EVENT_EN_CLI   BIT(2)
#define SWITCHTEC_EVENT_EN_IRQ   BIT(3)
#define SWITCHTEC_EVENT_FATAL    BIT(4)

#define SWITCHTEC_DMA_MRPC_EN	BIT(0)
enum {
	SWITCHTEC_GAS_MRPC_OFFSET       = 0x0000,
	SWITCHTEC_GAS_TOP_CFG_OFFSET    = 0x1000,
	SWITCHTEC_GAS_SW_EVENT_OFFSET   = 0x1800,
	SWITCHTEC_GAS_SYS_INFO_OFFSET   = 0x2000,
	SWITCHTEC_GAS_FLASH_INFO_OFFSET = 0x2200,
	SWITCHTEC_GAS_PART_CFG_OFFSET   = 0x4000,
	SWITCHTEC_GAS_NTB_OFFSET        = 0x10000,
	SWITCHTEC_GAS_PFF_CSR_OFFSET    = 0x134000,
};

struct mrpc_regs {
	u8 input_data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
	u8 output_data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
	u32 cmd;
	u32 status;
	u32 ret_value;
	u32 dma_en;
	u64 dma_addr;
	u32 dma_vector;
	u32 dma_ver;
} __packed;

enum mrpc_status {
	SWITCHTEC_MRPC_STATUS_INPROGRESS = 1,
	SWITCHTEC_MRPC_STATUS_DONE = 2,
	SWITCHTEC_MRPC_STATUS_ERROR = 0xFF,
	SWITCHTEC_MRPC_STATUS_INTERRUPTED = 0x100,
};

struct sw_event_regs {
	u64 event_report_ctrl;
	u64 reserved1;
	u64 part_event_bitmap;
	u64 reserved2;
	u32 global_summary;
	u32 reserved3[3];
	u32 stack_error_event_hdr;
	u32 stack_error_event_data;
	u32 reserved4[4];
	u32 ppu_error_event_hdr;
	u32 ppu_error_event_data;
	u32 reserved5[4];
	u32 isp_error_event_hdr;
	u32 isp_error_event_data;
	u32 reserved6[4];
	u32 sys_reset_event_hdr;
	u32 reserved7[5];
	u32 fw_exception_hdr;
	u32 reserved8[5];
	u32 fw_nmi_hdr;
	u32 reserved9[5];
	u32 fw_non_fatal_hdr;
	u32 reserved10[5];
	u32 fw_fatal_hdr;
	u32 reserved11[5];
	u32 twi_mrpc_comp_hdr;
	u32 twi_mrpc_comp_data;
	u32 reserved12[4];
	u32 twi_mrpc_comp_async_hdr;
	u32 twi_mrpc_comp_async_data;
	u32 reserved13[4];
	u32 cli_mrpc_comp_hdr;
	u32 cli_mrpc_comp_data;
	u32 reserved14[4];
	u32 cli_mrpc_comp_async_hdr;
	u32 cli_mrpc_comp_async_data;
	u32 reserved15[4];
	u32 gpio_interrupt_hdr;
	u32 gpio_interrupt_data;
	u32 reserved16[4];
	u32 gfms_event_hdr;
	u32 gfms_event_data;
	u32 reserved17[4];
} __packed;

enum {
	SWITCHTEC_CFG0_RUNNING = 0x04,
	SWITCHTEC_CFG1_RUNNING = 0x05,
	SWITCHTEC_IMG0_RUNNING = 0x03,
	SWITCHTEC_IMG1_RUNNING = 0x07,
};

struct sys_info_regs {
	u32 device_id;
	u32 device_version;
	u32 firmware_version;
	u32 reserved1;
	u32 vendor_table_revision;
	u32 table_format_version;
	u32 partition_id;
	u32 cfg_file_fmt_version;
	u16 cfg_running;
	u16 img_running;
	u32 reserved2[57];
	char vendor_id[8];
	char product_id[16];
	char product_revision[4];
	char component_vendor[8];
	u16 component_id;
	u8 component_revision;
} __packed;

struct flash_info_regs {
	u32 flash_part_map_upd_idx;

	struct active_partition_info {
		u32 address;
		u32 build_version;
		u32 build_string;
	} active_img;

	struct active_partition_info active_cfg;
	struct active_partition_info inactive_img;
	struct active_partition_info inactive_cfg;

	u32 flash_length;

	struct partition_info {
		u32 address;
		u32 length;
	} cfg0;

	struct partition_info cfg1;
	struct partition_info img0;
	struct partition_info img1;
	struct partition_info nvlog;
	struct partition_info vendor[8];
};

enum {
	SWITCHTEC_NTB_REG_INFO_OFFSET   = 0x0000,
	SWITCHTEC_NTB_REG_CTRL_OFFSET   = 0x4000,
	SWITCHTEC_NTB_REG_DBMSG_OFFSET  = 0x64000,
};

struct ntb_info_regs {
	u8  partition_count;
	u8  partition_id;
	u16 reserved1;
	u64 ep_map;
	u16 requester_id;
	u16 reserved2;
	u32 reserved3[4];
	struct nt_partition_info {
		u32 xlink_enabled;
		u32 target_part_low;
		u32 target_part_high;
		u32 reserved;
	} ntp_info[48];
} __packed;

struct part_cfg_regs {
	u32 status;
	u32 state;
	u32 port_cnt;
	u32 usp_port_mode;
	u32 usp_pff_inst_id;
	u32 vep_pff_inst_id;
	u32 dsp_pff_inst_id[47];
	u32 reserved1[11];
	u16 vep_vector_number;
	u16 usp_vector_number;
	u32 port_event_bitmap;
	u32 reserved2[3];
	u32 part_event_summary;
	u32 reserved3[3];
	u32 part_reset_hdr;
	u32 part_reset_data[5];
	u32 mrpc_comp_hdr;
	u32 mrpc_comp_data[5];
	u32 mrpc_comp_async_hdr;
	u32 mrpc_comp_async_data[5];
	u32 dyn_binding_hdr;
	u32 dyn_binding_data[5];
	u32 reserved4[159];
} __packed;

enum {
	NTB_CTRL_PART_OP_LOCK = 0x1,
	NTB_CTRL_PART_OP_CFG = 0x2,
	NTB_CTRL_PART_OP_RESET = 0x3,

	NTB_CTRL_PART_STATUS_NORMAL = 0x1,
	NTB_CTRL_PART_STATUS_LOCKED = 0x2,
	NTB_CTRL_PART_STATUS_LOCKING = 0x3,
	NTB_CTRL_PART_STATUS_CONFIGURING = 0x4,
	NTB_CTRL_PART_STATUS_RESETTING = 0x5,

	NTB_CTRL_BAR_VALID = 1 << 0,
	NTB_CTRL_BAR_DIR_WIN_EN = 1 << 4,
	NTB_CTRL_BAR_LUT_WIN_EN = 1 << 5,

	NTB_CTRL_REQ_ID_EN = 1 << 0,

	NTB_CTRL_LUT_EN = 1 << 0,

	NTB_PART_CTRL_ID_PROT_DIS = 1 << 0,
};

struct ntb_ctrl_regs {
	u32 partition_status;
	u32 partition_op;
	u32 partition_ctrl;
	u32 bar_setup;
	u32 bar_error;
	u16 lut_table_entries;
	u16 lut_table_offset;
	u32 lut_error;
	u16 req_id_table_size;
	u16 req_id_table_offset;
	u32 req_id_error;
	u32 reserved1[7];
	struct {
		u32 ctl;
		u32 win_size;
		u64 xlate_addr;
	} bar_entry[6];
	struct {
		u32 win_size;
		u32 reserved[3];
	} bar_ext_entry[6];
	u32 reserved2[192];
	u32 req_id_table[512];
	u32 reserved3[256];
	u64 lut_entry[512];
} __packed;

#define NTB_DBMSG_IMSG_STATUS BIT_ULL(32)
#define NTB_DBMSG_IMSG_MASK   BIT_ULL(40)

struct ntb_dbmsg_regs {
	u32 reserved1[1024];
	u64 odb;
	u64 odb_mask;
	u64 idb;
	u64 idb_mask;
	u8  idb_vec_map[64];
	u32 msg_map;
	u32 reserved2;
	struct {
		u32 msg;
		u32 status;
	} omsg[4];

	struct {
		u32 msg;
		u8  status;
		u8  mask;
		u8  src;
		u8  reserved;
	} imsg[4];

	u8 reserved3[3928];
	u8 msix_table[1024];
	u8 reserved4[3072];
	u8 pba[24];
	u8 reserved5[4072];
} __packed;

enum {
	SWITCHTEC_PART_CFG_EVENT_RESET = 1 << 0,
	SWITCHTEC_PART_CFG_EVENT_MRPC_CMP = 1 << 1,
	SWITCHTEC_PART_CFG_EVENT_MRPC_ASYNC_CMP = 1 << 2,
	SWITCHTEC_PART_CFG_EVENT_DYN_PART_CMP = 1 << 3,
};

struct pff_csr_regs {
	u16 vendor_id;
	u16 device_id;
	u16 pcicmd;
	u16 pcists;
	u32 pci_class;
	u32 pci_opts;
	union {
		u32 pci_bar[6];
		u64 pci_bar64[3];
	};
	u32 pci_cardbus;
	u32 pci_subsystem_id;
	u32 pci_expansion_rom;
	u32 pci_cap_ptr;
	u32 reserved1;
	u32 pci_irq;
	u32 pci_cap_region[48];
	u32 pcie_cap_region[448];
	u32 indirect_gas_window[128];
	u32 indirect_gas_window_off;
	u32 reserved[127];
	u32 pff_event_summary;
	u32 reserved2[3];
	u32 aer_in_p2p_hdr;
	u32 aer_in_p2p_data[5];
	u32 aer_in_vep_hdr;
	u32 aer_in_vep_data[5];
	u32 dpc_hdr;
	u32 dpc_data[5];
	u32 cts_hdr;
	u32 cts_data[5];
	u32 reserved3[6];
	u32 hotplug_hdr;
	u32 hotplug_data[5];
	u32 ier_hdr;
	u32 ier_data[5];
	u32 threshold_hdr;
	u32 threshold_data[5];
	u32 power_mgmt_hdr;
	u32 power_mgmt_data[5];
	u32 tlp_throttling_hdr;
	u32 tlp_throttling_data[5];
	u32 force_speed_hdr;
	u32 force_speed_data[5];
	u32 credit_timeout_hdr;
	u32 credit_timeout_data[5];
	u32 link_state_hdr;
	u32 link_state_data[5];
	u32 reserved4[174];
} __packed;

struct switchtec_ntb;

struct dma_mrpc_output {
	u32 status;
	u32 cmd_id;
	u32 rtn_code;
	u32 output_size;
	u8 data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
};

struct switchtec_dev {
	struct pci_dev *pdev;
	struct device dev;
	struct cdev cdev;

	int partition;
	int partition_count;
	int pff_csr_count;
	char pff_local[SWITCHTEC_MAX_PFF_CSR];

	void __iomem *mmio;
	struct mrpc_regs __iomem *mmio_mrpc;
	struct sw_event_regs __iomem *mmio_sw_event;
	struct sys_info_regs __iomem *mmio_sys_info;
	struct flash_info_regs __iomem *mmio_flash_info;
	struct ntb_info_regs __iomem *mmio_ntb;
	struct part_cfg_regs __iomem *mmio_part_cfg;
	struct part_cfg_regs __iomem *mmio_part_cfg_all;
	struct pff_csr_regs __iomem *mmio_pff_csr;

	/*
	 * The mrpc mutex must be held when accessing the other
	 * mrpc_ fields, alive flag and stuser->state field
	 */
	struct mutex mrpc_mutex;
	struct list_head mrpc_queue;
	int mrpc_busy;
	struct work_struct mrpc_work;
	struct delayed_work mrpc_timeout;
	bool alive;

	wait_queue_head_t event_wq;
	atomic_t event_cnt;

	struct work_struct link_event_work;
	void (*link_notifier)(struct switchtec_dev *stdev);
	u8 link_event_count[SWITCHTEC_MAX_PFF_CSR];

	struct switchtec_ntb *sndev;

	struct dma_mrpc_output *dma_mrpc;
	dma_addr_t dma_mrpc_dma_addr;
};

static inline struct switchtec_dev *to_stdev(struct device *dev)
{
	return container_of(dev, struct switchtec_dev, dev);
}

extern struct class *switchtec_class;

#endif
Commit	Line	Data
2025cf9e	1	/* SPDX-License-Identifier: GPL-2.0-only */
5a1c269f LG	2	/*
	3	* Microsemi Switchtec PCIe Driver
	4	* Copyright (c) 2017, Microsemi Corporation
5a1c269f LG	5	*/
	6
	7	#ifndef _SWITCHTEC_H
	8	#define _SWITCHTEC_H
	9
	10	#include <linux/pci.h>
	11	#include <linux/cdev.h>
	12
5a1c269f	13	#define SWITCHTEC_MRPC_PAYLOAD_SIZE 1024
ba8a3982	14	#define SWITCHTEC_MAX_PFF_CSR 255
5a1c269f LG	15
	16	#define SWITCHTEC_EVENT_OCCURRED BIT(0)
	17	#define SWITCHTEC_EVENT_CLEAR BIT(0)
	18	#define SWITCHTEC_EVENT_EN_LOG BIT(1)
	19	#define SWITCHTEC_EVENT_EN_CLI BIT(2)
	20	#define SWITCHTEC_EVENT_EN_IRQ BIT(3)
	21	#define SWITCHTEC_EVENT_FATAL BIT(4)
	22
f7eb7b8a	23	#define SWITCHTEC_DMA_MRPC_EN BIT(0)
5a1c269f LG	24	enum {
	25	SWITCHTEC_GAS_MRPC_OFFSET = 0x0000,
	26	SWITCHTEC_GAS_TOP_CFG_OFFSET = 0x1000,
	27	SWITCHTEC_GAS_SW_EVENT_OFFSET = 0x1800,
	28	SWITCHTEC_GAS_SYS_INFO_OFFSET = 0x2000,
	29	SWITCHTEC_GAS_FLASH_INFO_OFFSET = 0x2200,
	30	SWITCHTEC_GAS_PART_CFG_OFFSET = 0x4000,
	31	SWITCHTEC_GAS_NTB_OFFSET = 0x10000,
	32	SWITCHTEC_GAS_PFF_CSR_OFFSET = 0x134000,
	33	};
	34
	35	struct mrpc_regs {
	36	u8 input_data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
	37	u8 output_data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
	38	u32 cmd;
	39	u32 status;
	40	u32 ret_value;
f7eb7b8a WS	41	u32 dma_en;
	42	u64 dma_addr;
	43	u32 dma_vector;
	44	u32 dma_ver;
5a1c269f LG	45	} __packed;
	46
	47	enum mrpc_status {
	48	SWITCHTEC_MRPC_STATUS_INPROGRESS = 1,
	49	SWITCHTEC_MRPC_STATUS_DONE = 2,
	50	SWITCHTEC_MRPC_STATUS_ERROR = 0xFF,
	51	SWITCHTEC_MRPC_STATUS_INTERRUPTED = 0x100,
	52	};
	53
	54	struct sw_event_regs {
	55	u64 event_report_ctrl;
	56	u64 reserved1;
	57	u64 part_event_bitmap;
	58	u64 reserved2;
	59	u32 global_summary;
	60	u32 reserved3[3];
	61	u32 stack_error_event_hdr;
	62	u32 stack_error_event_data;
	63	u32 reserved4[4];
	64	u32 ppu_error_event_hdr;
	65	u32 ppu_error_event_data;
	66	u32 reserved5[4];
	67	u32 isp_error_event_hdr;
	68	u32 isp_error_event_data;
	69	u32 reserved6[4];
	70	u32 sys_reset_event_hdr;
	71	u32 reserved7[5];
	72	u32 fw_exception_hdr;
	73	u32 reserved8[5];
	74	u32 fw_nmi_hdr;
	75	u32 reserved9[5];
	76	u32 fw_non_fatal_hdr;
	77	u32 reserved10[5];
	78	u32 fw_fatal_hdr;
	79	u32 reserved11[5];
	80	u32 twi_mrpc_comp_hdr;
	81	u32 twi_mrpc_comp_data;
	82	u32 reserved12[4];
	83	u32 twi_mrpc_comp_async_hdr;
	84	u32 twi_mrpc_comp_async_data;
	85	u32 reserved13[4];
	86	u32 cli_mrpc_comp_hdr;
	87	u32 cli_mrpc_comp_data;
	88	u32 reserved14[4];
	89	u32 cli_mrpc_comp_async_hdr;
	90	u32 cli_mrpc_comp_async_data;
	91	u32 reserved15[4];
	92	u32 gpio_interrupt_hdr;
	93	u32 gpio_interrupt_data;
	94	u32 reserved16[4];
f0edce7a LG	95	u32 gfms_event_hdr;
	96	u32 gfms_event_data;
	97	u32 reserved17[4];
5a1c269f LG	98	} __packed;
	99
	100	enum {
	101	SWITCHTEC_CFG0_RUNNING = 0x04,
	102	SWITCHTEC_CFG1_RUNNING = 0x05,
	103	SWITCHTEC_IMG0_RUNNING = 0x03,
	104	SWITCHTEC_IMG1_RUNNING = 0x07,
	105	};
	106
	107	struct sys_info_regs {
	108	u32 device_id;
	109	u32 device_version;
	110	u32 firmware_version;
	111	u32 reserved1;
	112	u32 vendor_table_revision;
	113	u32 table_format_version;
	114	u32 partition_id;
	115	u32 cfg_file_fmt_version;
	116	u16 cfg_running;
	117	u16 img_running;
	118	u32 reserved2[57];
	119	char vendor_id[8];
	120	char product_id[16];
	121	char product_revision[4];
	122	char component_vendor[8];
	123	u16 component_id;
	124	u8 component_revision;
	125	} __packed;
	126
	127	struct flash_info_regs {
	128	u32 flash_part_map_upd_idx;
	129
	130	struct active_partition_info {
	131	u32 address;
	132	u32 build_version;
	133	u32 build_string;
	134	} active_img;
	135
	136	struct active_partition_info active_cfg;
	137	struct active_partition_info inactive_img;
	138	struct active_partition_info inactive_cfg;
	139
	140	u32 flash_length;
	141
	142	struct partition_info {
	143	u32 address;
	144	u32 length;
	145	} cfg0;
	146
	147	struct partition_info cfg1;
	148	struct partition_info img0;
	149	struct partition_info img1;
	150	struct partition_info nvlog;
	151	struct partition_info vendor[8];
	152	};
	153
c082b04c LG	154	enum {
	155	SWITCHTEC_NTB_REG_INFO_OFFSET = 0x0000,
	156	SWITCHTEC_NTB_REG_CTRL_OFFSET = 0x4000,
	157	SWITCHTEC_NTB_REG_DBMSG_OFFSET = 0x64000,
	158	};
	159
5a1c269f LG	160	struct ntb_info_regs {
	161	u8 partition_count;
	162	u8 partition_id;
	163	u16 reserved1;
	164	u64 ep_map;
	165	u16 requester_id;
3df54c87 KC	166	u16 reserved2;
	167	u32 reserved3[4];
	168	struct nt_partition_info {
	169	u32 xlink_enabled;
	170	u32 target_part_low;
	171	u32 target_part_high;
	172	u32 reserved;
	173	} ntp_info[48];
5a1c269f LG	174	} __packed;
	175
	176	struct part_cfg_regs {
	177	u32 status;
	178	u32 state;
	179	u32 port_cnt;
	180	u32 usp_port_mode;
	181	u32 usp_pff_inst_id;
	182	u32 vep_pff_inst_id;
	183	u32 dsp_pff_inst_id[47];
	184	u32 reserved1[11];
	185	u16 vep_vector_number;
	186	u16 usp_vector_number;
	187	u32 port_event_bitmap;
	188	u32 reserved2[3];
	189	u32 part_event_summary;
	190	u32 reserved3[3];
	191	u32 part_reset_hdr;
	192	u32 part_reset_data[5];
	193	u32 mrpc_comp_hdr;
	194	u32 mrpc_comp_data[5];
	195	u32 mrpc_comp_async_hdr;
	196	u32 mrpc_comp_async_data[5];
	197	u32 dyn_binding_hdr;
	198	u32 dyn_binding_data[5];
	199	u32 reserved4[159];
	200	} __packed;
	201
c082b04c LG	202	enum {
	203	NTB_CTRL_PART_OP_LOCK = 0x1,
	204	NTB_CTRL_PART_OP_CFG = 0x2,
	205	NTB_CTRL_PART_OP_RESET = 0x3,
	206
	207	NTB_CTRL_PART_STATUS_NORMAL = 0x1,
	208	NTB_CTRL_PART_STATUS_LOCKED = 0x2,
	209	NTB_CTRL_PART_STATUS_LOCKING = 0x3,
	210	NTB_CTRL_PART_STATUS_CONFIGURING = 0x4,
	211	NTB_CTRL_PART_STATUS_RESETTING = 0x5,
	212
	213	NTB_CTRL_BAR_VALID = 1 << 0,
	214	NTB_CTRL_BAR_DIR_WIN_EN = 1 << 4,
	215	NTB_CTRL_BAR_LUT_WIN_EN = 1 << 5,
	216
	217	NTB_CTRL_REQ_ID_EN = 1 << 0,
	218
	219	NTB_CTRL_LUT_EN = 1 << 0,
	220
	221	NTB_PART_CTRL_ID_PROT_DIS = 1 << 0,
	222	};
	223
	224	struct ntb_ctrl_regs {
	225	u32 partition_status;
	226	u32 partition_op;
	227	u32 partition_ctrl;
	228	u32 bar_setup;
	229	u32 bar_error;
	230	u16 lut_table_entries;
	231	u16 lut_table_offset;
	232	u32 lut_error;
	233	u16 req_id_table_size;
	234	u16 req_id_table_offset;
	235	u32 req_id_error;
	236	u32 reserved1[7];
	237	struct {
	238	u32 ctl;
	239	u32 win_size;
	240	u64 xlate_addr;
	241	} bar_entry[6];
a2585cdc PS	242	struct {
	243	u32 win_size;
	244	u32 reserved[3];
	245	} bar_ext_entry[6];
	246	u32 reserved2[192];
d123fab7 WS	247	u32 req_id_table[512];
d123fab7 WS	248	u32 reserved3[256];
c082b04c LG	249	u64 lut_entry[512];
	250	} __packed;
	251
	252	#define NTB_DBMSG_IMSG_STATUS BIT_ULL(32)
	253	#define NTB_DBMSG_IMSG_MASK BIT_ULL(40)
	254
	255	struct ntb_dbmsg_regs {
	256	u32 reserved1[1024];
	257	u64 odb;
	258	u64 odb_mask;
	259	u64 idb;
	260	u64 idb_mask;
	261	u8 idb_vec_map[64];
	262	u32 msg_map;
	263	u32 reserved2;
	264	struct {
	265	u32 msg;
	266	u32 status;
	267	} omsg[4];
	268
	269	struct {
	270	u32 msg;
	271	u8 status;
	272	u8 mask;
	273	u8 src;
	274	u8 reserved;
	275	} imsg[4];
	276
	277	u8 reserved3[3928];
	278	u8 msix_table[1024];
	279	u8 reserved4[3072];
	280	u8 pba[24];
	281	u8 reserved5[4072];
	282	} __packed;
	283
5a1c269f LG	284	enum {
	285	SWITCHTEC_PART_CFG_EVENT_RESET = 1 << 0,
	286	SWITCHTEC_PART_CFG_EVENT_MRPC_CMP = 1 << 1,
	287	SWITCHTEC_PART_CFG_EVENT_MRPC_ASYNC_CMP = 1 << 2,
	288	SWITCHTEC_PART_CFG_EVENT_DYN_PART_CMP = 1 << 3,
	289	};
	290
	291	struct pff_csr_regs {
	292	u16 vendor_id;
	293	u16 device_id;
45f447de LG	294	u16 pcicmd;
	295	u16 pcists;
	296	u32 pci_class;
	297	u32 pci_opts;
	298	union {
	299	u32 pci_bar[6];
	300	u64 pci_bar64[3];
	301	};
	302	u32 pci_cardbus;
	303	u32 pci_subsystem_id;
	304	u32 pci_expansion_rom;
	305	u32 pci_cap_ptr;
	306	u32 reserved1;
	307	u32 pci_irq;
5a1c269f LG	308	u32 pci_cap_region[48];
	309	u32 pcie_cap_region[448];
	310	u32 indirect_gas_window[128];
	311	u32 indirect_gas_window_off;
	312	u32 reserved[127];
	313	u32 pff_event_summary;
	314	u32 reserved2[3];
	315	u32 aer_in_p2p_hdr;
	316	u32 aer_in_p2p_data[5];
	317	u32 aer_in_vep_hdr;
	318	u32 aer_in_vep_data[5];
	319	u32 dpc_hdr;
	320	u32 dpc_data[5];
	321	u32 cts_hdr;
	322	u32 cts_data[5];
	323	u32 reserved3[6];
	324	u32 hotplug_hdr;
	325	u32 hotplug_data[5];
	326	u32 ier_hdr;
	327	u32 ier_data[5];
	328	u32 threshold_hdr;
	329	u32 threshold_data[5];
	330	u32 power_mgmt_hdr;
	331	u32 power_mgmt_data[5];
	332	u32 tlp_throttling_hdr;
	333	u32 tlp_throttling_data[5];
	334	u32 force_speed_hdr;
	335	u32 force_speed_data[5];
	336	u32 credit_timeout_hdr;
	337	u32 credit_timeout_data[5];
	338	u32 link_state_hdr;
	339	u32 link_state_data[5];
	340	u32 reserved4[174];
	341	} __packed;
	342
33dea5aa LG	343	struct switchtec_ntb;
33dea5aa LG	344
f7eb7b8a WS	345	struct dma_mrpc_output {
	346	u32 status;
	347	u32 cmd_id;
	348	u32 rtn_code;
	349	u32 output_size;
	350	u8 data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
	351	};
	352
5a1c269f LG	353	struct switchtec_dev {
	354	struct pci_dev *pdev;
	355	struct device dev;
	356	struct cdev cdev;
	357
	358	int partition;
	359	int partition_count;
	360	int pff_csr_count;
	361	char pff_local[SWITCHTEC_MAX_PFF_CSR];
	362
	363	void __iomem *mmio;
	364	struct mrpc_regs __iomem *mmio_mrpc;
	365	struct sw_event_regs __iomem *mmio_sw_event;
	366	struct sys_info_regs __iomem *mmio_sys_info;
	367	struct flash_info_regs __iomem *mmio_flash_info;
	368	struct ntb_info_regs __iomem *mmio_ntb;
	369	struct part_cfg_regs __iomem *mmio_part_cfg;
	370	struct part_cfg_regs __iomem *mmio_part_cfg_all;
	371	struct pff_csr_regs __iomem *mmio_pff_csr;
	372
	373	/*
	374	* The mrpc mutex must be held when accessing the other
	375	* mrpc_ fields, alive flag and stuser->state field
	376	*/
	377	struct mutex mrpc_mutex;
	378	struct list_head mrpc_queue;
	379	int mrpc_busy;
	380	struct work_struct mrpc_work;
	381	struct delayed_work mrpc_timeout;
	382	bool alive;
	383
	384	wait_queue_head_t event_wq;
	385	atomic_t event_cnt;
48c302dc LG	386
	387	struct work_struct link_event_work;
	388	void (link_notifier)(struct switchtec_dev stdev);
	389	u8 link_event_count[SWITCHTEC_MAX_PFF_CSR];
33dea5aa LG	390
33dea5aa LG	391	struct switchtec_ntb *sndev;
f7eb7b8a WS	392
	393	struct dma_mrpc_output *dma_mrpc;
	394	dma_addr_t dma_mrpc_dma_addr;
5a1c269f LG	395	};
	396
	397	static inline struct switchtec_dev to_stdev(struct device dev)
	398	{
	399	return container_of(dev, struct switchtec_dev, dev);
	400	}
	401
302e994d LG	402	extern struct class *switchtec_class;
302e994d LG	403
5a1c269f	404	#endif