[linux-block.git] / include / linux / stmmac.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*******************************************************************************

  Header file for stmmac platform data

  Copyright (C) 2009  STMicroelectronics Ltd


  Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
*******************************************************************************/

#ifndef __STMMAC_PLATFORM_DATA
#define __STMMAC_PLATFORM_DATA

#include <linux/platform_device.h>

#define MTL_MAX_RX_QUEUES	8
#define MTL_MAX_TX_QUEUES	8
#define STMMAC_CH_MAX		8

#define STMMAC_RX_COE_NONE	0
#define STMMAC_RX_COE_TYPE1	1
#define STMMAC_RX_COE_TYPE2	2

/* Define the macros for CSR clock range parameters to be passed by
 * platform code.
 * This could also be configured at run time using CPU freq framework. */

/* MDC Clock Selection define*/
#define	STMMAC_CSR_60_100M	0x0	/* MDC = clk_scr_i/42 */
#define	STMMAC_CSR_100_150M	0x1	/* MDC = clk_scr_i/62 */
#define	STMMAC_CSR_20_35M	0x2	/* MDC = clk_scr_i/16 */
#define	STMMAC_CSR_35_60M	0x3	/* MDC = clk_scr_i/26 */
#define	STMMAC_CSR_150_250M	0x4	/* MDC = clk_scr_i/102 */
#define	STMMAC_CSR_250_300M	0x5	/* MDC = clk_scr_i/122 */

/* MTL algorithms identifiers */
#define MTL_TX_ALGORITHM_WRR	0x0
#define MTL_TX_ALGORITHM_WFQ	0x1
#define MTL_TX_ALGORITHM_DWRR	0x2
#define MTL_TX_ALGORITHM_SP	0x3
#define MTL_RX_ALGORITHM_SP	0x4
#define MTL_RX_ALGORITHM_WSP	0x5

/* RX/TX Queue Mode */
#define MTL_QUEUE_AVB		0x0
#define MTL_QUEUE_DCB		0x1

/* The MDC clock could be set higher than the IEEE 802.3
 * specified frequency limit 0f 2.5 MHz, by programming a clock divider
 * of value different than the above defined values. The resultant MDIO
 * clock frequency of 12.5 MHz is applicable for the interfacing chips
 * supporting higher MDC clocks.
 * The MDC clock selection macros need to be defined for MDC clock rate
 * of 12.5 MHz, corresponding to the following selection.
 */
#define STMMAC_CSR_I_4		0x8	/* clk_csr_i/4 */
#define STMMAC_CSR_I_6		0x9	/* clk_csr_i/6 */
#define STMMAC_CSR_I_8		0xA	/* clk_csr_i/8 */
#define STMMAC_CSR_I_10		0xB	/* clk_csr_i/10 */
#define STMMAC_CSR_I_12		0xC	/* clk_csr_i/12 */
#define STMMAC_CSR_I_14		0xD	/* clk_csr_i/14 */
#define STMMAC_CSR_I_16		0xE	/* clk_csr_i/16 */
#define STMMAC_CSR_I_18		0xF	/* clk_csr_i/18 */

/* AXI DMA Burst length supported */
#define DMA_AXI_BLEN_4		(1 << 1)
#define DMA_AXI_BLEN_8		(1 << 2)
#define DMA_AXI_BLEN_16		(1 << 3)
#define DMA_AXI_BLEN_32		(1 << 4)
#define DMA_AXI_BLEN_64		(1 << 5)
#define DMA_AXI_BLEN_128	(1 << 6)
#define DMA_AXI_BLEN_256	(1 << 7)
#define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \
			| DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \
			| DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256)

/* Platfrom data for platform device structure's platform_data field */

struct stmmac_mdio_bus_data {
	unsigned int phy_mask;
	int *irqs;
	int probed_phy_irq;
	bool needs_reset;
};

struct stmmac_dma_cfg {
	int pbl;
	int txpbl;
	int rxpbl;
	bool pblx8;
	int fixed_burst;
	int mixed_burst;
	bool aal;
};

#define AXI_BLEN	7
struct stmmac_axi {
	bool axi_lpi_en;
	bool axi_xit_frm;
	u32 axi_wr_osr_lmt;
	u32 axi_rd_osr_lmt;
	bool axi_kbbe;
	u32 axi_blen[AXI_BLEN];
	bool axi_fb;
	bool axi_mb;
	bool axi_rb;
};

struct stmmac_rxq_cfg {
	u8 mode_to_use;
	u32 chan;
	u8 pkt_route;
	bool use_prio;
	u32 prio;
};

struct stmmac_txq_cfg {
	u32 weight;
	u8 mode_to_use;
	/* Credit Base Shaper parameters */
	u32 send_slope;
	u32 idle_slope;
	u32 high_credit;
	u32 low_credit;
	bool use_prio;
	u32 prio;
};

struct plat_stmmacenet_data {
	int bus_id;
	int phy_addr;
	int interface;
	int phy_interface;
	struct stmmac_mdio_bus_data *mdio_bus_data;
	struct device_node *phy_node;
	struct device_node *phylink_node;
	struct device_node *mdio_node;
	struct stmmac_dma_cfg *dma_cfg;
	int clk_csr;
	int has_gmac;
	int enh_desc;
	int tx_coe;
	int rx_coe;
	int bugged_jumbo;
	int pmt;
	int force_sf_dma_mode;
	int force_thresh_dma_mode;
	int riwt_off;
	int max_speed;
	int maxmtu;
	int multicast_filter_bins;
	int unicast_filter_entries;
	int tx_fifo_size;
	int rx_fifo_size;
	u32 rx_queues_to_use;
	u32 tx_queues_to_use;
	u8 rx_sched_algorithm;
	u8 tx_sched_algorithm;
	struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES];
	struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES];
	void (*fix_mac_speed)(void *priv, unsigned int speed);
	int (*init)(struct platform_device *pdev, void *priv);
	void (*exit)(struct platform_device *pdev, void *priv);
	struct mac_device_info *(*setup)(void *priv);
	void *bsp_priv;
	struct clk *stmmac_clk;
	struct clk *pclk;
	struct clk *clk_ptp_ref;
	unsigned int clk_ptp_rate;
	unsigned int clk_ref_rate;
	s32 ptp_max_adj;
	struct reset_control *stmmac_rst;
	struct stmmac_axi *axi;
	int has_gmac4;
	bool has_sun8i;
	bool tso_en;
	int rss_en;
	int mac_port_sel_speed;
	bool en_tx_lpi_clockgating;
	int has_xgmac;
};
#endif
Commit	Line	Data
1237a75a	1	/* SPDX-License-Identifier: GPL-2.0-only */
3c9732c0 GC	2	/*******************************************************************************
	3
	4	Header file for stmmac platform data
	5
	6	Copyright (C) 2009 STMicroelectronics Ltd
	7
3c9732c0 GC	8
	9	Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
	10	*******************************************************************************/
	11
	12	#ifndef __STMMAC_PLATFORM_DATA
	13	#define __STMMAC_PLATFORM_DATA
	14
57a503c6 VK	15	#include <linux/platform_device.h>
57a503c6 VK	16
d976a525 JP	17	#define MTL_MAX_RX_QUEUES 8
d976a525 JP	18	#define MTL_MAX_TX_QUEUES 8
8fce3331	19	#define STMMAC_CH_MAX 8
d976a525	20
55f9a4d6 DS	21	#define STMMAC_RX_COE_NONE 0
	22	#define STMMAC_RX_COE_TYPE1 1
	23	#define STMMAC_RX_COE_TYPE2 2
	24
faeae3fa DS	25	/* Define the macros for CSR clock range parameters to be passed by
	26	* platform code.
	27	* This could also be configured at run time using CPU freq framework. */
	28
	29	/* MDC Clock Selection define*/
18f05d64 GC	30	#define STMMAC_CSR_60_100M 0x0 /* MDC = clk_scr_i/42 */
	31	#define STMMAC_CSR_100_150M 0x1 /* MDC = clk_scr_i/62 */
	32	#define STMMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */
	33	#define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */
	34	#define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */
	35	#define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */
faeae3fa	36
d976a525 JP	37	/* MTL algorithms identifiers */
	38	#define MTL_TX_ALGORITHM_WRR 0x0
	39	#define MTL_TX_ALGORITHM_WFQ 0x1
	40	#define MTL_TX_ALGORITHM_DWRR 0x2
	41	#define MTL_TX_ALGORITHM_SP 0x3
	42	#define MTL_RX_ALGORITHM_SP 0x4
	43	#define MTL_RX_ALGORITHM_WSP 0x5
	44
19d91873	45	/* RX/TX Queue Mode */
2d72d501 TR	46	#define MTL_QUEUE_AVB 0x0
2d72d501 TR	47	#define MTL_QUEUE_DCB 0x1
d976a525	48
18f05d64	49	/* The MDC clock could be set higher than the IEEE 802.3
faeae3fa DS	50	* specified frequency limit 0f 2.5 MHz, by programming a clock divider
	51	* of value different than the above defined values. The resultant MDIO
	52	* clock frequency of 12.5 MHz is applicable for the interfacing chips
	53	* supporting higher MDC clocks.
	54	* The MDC clock selection macros need to be defined for MDC clock rate
	55	* of 12.5 MHz, corresponding to the following selection.
18f05d64 GC	56	*/
	57	#define STMMAC_CSR_I_4 0x8 /* clk_csr_i/4 */
	58	#define STMMAC_CSR_I_6 0x9 /* clk_csr_i/6 */
	59	#define STMMAC_CSR_I_8 0xA /* clk_csr_i/8 */
	60	#define STMMAC_CSR_I_10 0xB /* clk_csr_i/10 */
	61	#define STMMAC_CSR_I_12 0xC /* clk_csr_i/12 */
	62	#define STMMAC_CSR_I_14 0xD /* clk_csr_i/14 */
	63	#define STMMAC_CSR_I_16 0xE /* clk_csr_i/16 */
	64	#define STMMAC_CSR_I_18 0xF /* clk_csr_i/18 */
faeae3fa	65
02582e9b	66	/* AXI DMA Burst length supported */
8327eb65 DS	67	#define DMA_AXI_BLEN_4 (1 << 1)
	68	#define DMA_AXI_BLEN_8 (1 << 2)
	69	#define DMA_AXI_BLEN_16 (1 << 3)
	70	#define DMA_AXI_BLEN_32 (1 << 4)
	71	#define DMA_AXI_BLEN_64 (1 << 5)
	72	#define DMA_AXI_BLEN_128 (1 << 6)
	73	#define DMA_AXI_BLEN_256 (1 << 7)
	74	#define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 \| DMA_AXI_BLEN_8 \| DMA_AXI_BLEN_16 \
	75	\| DMA_AXI_BLEN_32 \| DMA_AXI_BLEN_64 \
	76	\| DMA_AXI_BLEN_128 \| DMA_AXI_BLEN_256)
	77
36bcfe7d GC	78	/* Platfrom data for platform device structure's platform_data field */
	79
	80	struct stmmac_mdio_bus_data {
36bcfe7d GC	81	unsigned int phy_mask;
	82	int *irqs;
	83	int probed_phy_irq;
1a981c05	84	bool needs_reset;
36bcfe7d	85	};
3c9732c0	86
8327eb65 DS	87	struct stmmac_dma_cfg {
8327eb65 DS	88	int pbl;
89caaa2d NC	89	int txpbl;
89caaa2d NC	90	int rxpbl;
4022d039	91	bool pblx8;
8327eb65	92	int fixed_burst;
b9cde0a8	93	int mixed_burst;
afea0365 GC	94	bool aal;
	95	};
	96
	97	#define AXI_BLEN 7
	98	struct stmmac_axi {
	99	bool axi_lpi_en;
	100	bool axi_xit_frm;
	101	u32 axi_wr_osr_lmt;
	102	u32 axi_rd_osr_lmt;
	103	bool axi_kbbe;
afea0365 GC	104	u32 axi_blen[AXI_BLEN];
	105	bool axi_fb;
	106	bool axi_mb;
	107	bool axi_rb;
8327eb65 DS	108	};
8327eb65 DS	109
d976a525 JP	110	struct stmmac_rxq_cfg {
d976a525 JP	111	u8 mode_to_use;
e73b49eb	112	u32 chan;
abe80fdc	113	u8 pkt_route;
a8f5102a JP	114	bool use_prio;
a8f5102a JP	115	u32 prio;
d976a525 JP	116	};
	117
	118	struct stmmac_txq_cfg {
e73b49eb	119	u32 weight;
19d91873 JP	120	u8 mode_to_use;
	121	/* Credit Base Shaper parameters */
	122	u32 send_slope;
	123	u32 idle_slope;
	124	u32 high_credit;
	125	u32 low_credit;
a8f5102a JP	126	bool use_prio;
a8f5102a JP	127	u32 prio;
d976a525 JP	128	};
d976a525 JP	129
3c9732c0 GC	130	struct plat_stmmacenet_data {
3c9732c0 GC	131	int bus_id;
36bcfe7d GC	132	int phy_addr;
36bcfe7d GC	133	int interface;
0060c878	134	int phy_interface;
36bcfe7d	135	struct stmmac_mdio_bus_data *mdio_bus_data;
5790cf3c	136	struct device_node *phy_node;
4838a540	137	struct device_node *phylink_node;
a7657f12	138	struct device_node *mdio_node;
8327eb65	139	struct stmmac_dma_cfg *dma_cfg;
dfb8fb96	140	int clk_csr;
3c9732c0	141	int has_gmac;
e326e850	142	int enh_desc;
ebbb293f	143	int tx_coe;
55f9a4d6	144	int rx_coe;
ebbb293f	145	int bugged_jumbo;
543876c9	146	int pmt;
61b8013a	147	int force_sf_dma_mode;
e2a240c7	148	int force_thresh_dma_mode;
62a2ab93	149	int riwt_off;
9cbadf09	150	int max_speed;
2618abb7	151	int maxmtu;
3b57de95 VB	152	int multicast_filter_bins;
3b57de95 VB	153	int unicast_filter_entries;
e7877f52 VB	154	int tx_fifo_size;
e7877f52 VB	155	int rx_fifo_size;
e73b49eb BV	156	u32 rx_queues_to_use;
e73b49eb BV	157	u32 tx_queues_to_use;
d976a525 JP	158	u8 rx_sched_algorithm;
	159	u8 tx_sched_algorithm;
	160	struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES];
	161	struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES];
3c9732c0	162	void (fix_mac_speed)(void priv, unsigned int speed);
938dfdaa CYT	163	int (init)(struct platform_device pdev, void *priv);
938dfdaa CYT	164	void (exit)(struct platform_device pdev, void *priv);
ec33d71d	165	struct mac_device_info (setup)(void *priv);
3c9732c0	166	void *bsp_priv;
f573c0b9	167	struct clk *stmmac_clk;
	168	struct clk *pclk;
	169	struct clk *clk_ptp_ref;
	170	unsigned int clk_ptp_rate;
4ec5302f	171	unsigned int clk_ref_rate;
190f73ab	172	s32 ptp_max_adj;
f573c0b9	173	struct reset_control *stmmac_rst;
afea0365	174	struct stmmac_axi *axi;
ee2ae1ed	175	int has_gmac4;
9f93ac8d	176	bool has_sun8i;
ee2ae1ed	177	bool tso_en;
76067459	178	int rss_en;
02e57b9d	179	int mac_port_sel_speed;
b4b7b772	180	bool en_tx_lpi_clockgating;
48ae5554	181	int has_xgmac;
3c9732c0	182	};
3c9732c0	183	#endif