[linux-2.6-block.git] / include / linux / stmmac.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*******************************************************************************

  Header file for stmmac platform data

  Copyright (C) 2009  STMicroelectronics Ltd


  Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
*******************************************************************************/

#ifndef __STMMAC_PLATFORM_DATA
#define __STMMAC_PLATFORM_DATA

#include <linux/platform_device.h>
#include <linux/phylink.h>

#define MTL_MAX_RX_QUEUES	8
#define MTL_MAX_TX_QUEUES	8
#define STMMAC_CH_MAX		8

#define STMMAC_RX_COE_NONE	0
#define STMMAC_RX_COE_TYPE1	1
#define STMMAC_RX_COE_TYPE2	2

/* Define the macros for CSR clock range parameters to be passed by
 * platform code.
 * This could also be configured at run time using CPU freq framework. */

/* MDC Clock Selection define*/
#define	STMMAC_CSR_60_100M	0x0	/* MDC = clk_scr_i/42 */
#define	STMMAC_CSR_100_150M	0x1	/* MDC = clk_scr_i/62 */
#define	STMMAC_CSR_20_35M	0x2	/* MDC = clk_scr_i/16 */
#define	STMMAC_CSR_35_60M	0x3	/* MDC = clk_scr_i/26 */
#define	STMMAC_CSR_150_250M	0x4	/* MDC = clk_scr_i/102 */
#define	STMMAC_CSR_250_300M	0x5	/* MDC = clk_scr_i/122 */

/* MTL algorithms identifiers */
#define MTL_TX_ALGORITHM_WRR	0x0
#define MTL_TX_ALGORITHM_WFQ	0x1
#define MTL_TX_ALGORITHM_DWRR	0x2
#define MTL_TX_ALGORITHM_SP	0x3
#define MTL_RX_ALGORITHM_SP	0x4
#define MTL_RX_ALGORITHM_WSP	0x5

/* RX/TX Queue Mode */
#define MTL_QUEUE_AVB		0x0
#define MTL_QUEUE_DCB		0x1

/* The MDC clock could be set higher than the IEEE 802.3
 * specified frequency limit 0f 2.5 MHz, by programming a clock divider
 * of value different than the above defined values. The resultant MDIO
 * clock frequency of 12.5 MHz is applicable for the interfacing chips
 * supporting higher MDC clocks.
 * The MDC clock selection macros need to be defined for MDC clock rate
 * of 12.5 MHz, corresponding to the following selection.
 */
#define STMMAC_CSR_I_4		0x8	/* clk_csr_i/4 */
#define STMMAC_CSR_I_6		0x9	/* clk_csr_i/6 */
#define STMMAC_CSR_I_8		0xA	/* clk_csr_i/8 */
#define STMMAC_CSR_I_10		0xB	/* clk_csr_i/10 */
#define STMMAC_CSR_I_12		0xC	/* clk_csr_i/12 */
#define STMMAC_CSR_I_14		0xD	/* clk_csr_i/14 */
#define STMMAC_CSR_I_16		0xE	/* clk_csr_i/16 */
#define STMMAC_CSR_I_18		0xF	/* clk_csr_i/18 */

/* AXI DMA Burst length supported */
#define DMA_AXI_BLEN_4		(1 << 1)
#define DMA_AXI_BLEN_8		(1 << 2)
#define DMA_AXI_BLEN_16		(1 << 3)
#define DMA_AXI_BLEN_32		(1 << 4)
#define DMA_AXI_BLEN_64		(1 << 5)
#define DMA_AXI_BLEN_128	(1 << 6)
#define DMA_AXI_BLEN_256	(1 << 7)
#define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \
			| DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \
			| DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256)

struct stmmac_priv;

/* Platfrom data for platform device structure's platform_data field */

struct stmmac_mdio_bus_data {
	unsigned int phy_mask;
	unsigned int pcs_mask;
	unsigned int default_an_inband;
	int *irqs;
	int probed_phy_irq;
	bool needs_reset;
};

struct stmmac_dma_cfg {
	int pbl;
	int txpbl;
	int rxpbl;
	bool pblx8;
	int fixed_burst;
	int mixed_burst;
	bool aal;
	bool eame;
	bool multi_msi_en;
	bool dche;
	bool atds;
};

#define AXI_BLEN	7
struct stmmac_axi {
	bool axi_lpi_en;
	bool axi_xit_frm;
	u32 axi_wr_osr_lmt;
	u32 axi_rd_osr_lmt;
	bool axi_kbbe;
	u32 axi_blen[AXI_BLEN];
	bool axi_fb;
	bool axi_mb;
	bool axi_rb;
};

struct stmmac_rxq_cfg {
	u8 mode_to_use;
	u32 chan;
	u8 pkt_route;
	bool use_prio;
	u32 prio;
};

struct stmmac_txq_cfg {
	u32 weight;
	bool coe_unsupported;
	u8 mode_to_use;
	/* Credit Base Shaper parameters */
	u32 send_slope;
	u32 idle_slope;
	u32 high_credit;
	u32 low_credit;
	bool use_prio;
	u32 prio;
	int tbs_en;
};

struct stmmac_safety_feature_cfg {
	u32 tsoee;
	u32 mrxpee;
	u32 mestee;
	u32 mrxee;
	u32 mtxee;
	u32 epsi;
	u32 edpp;
	u32 prtyen;
	u32 tmouten;
};

/* Addresses that may be customized by a platform */
struct dwmac4_addrs {
	u32 dma_chan;
	u32 dma_chan_offset;
	u32 mtl_chan;
	u32 mtl_chan_offset;
	u32 mtl_ets_ctrl;
	u32 mtl_ets_ctrl_offset;
	u32 mtl_txq_weight;
	u32 mtl_txq_weight_offset;
	u32 mtl_send_slp_cred;
	u32 mtl_send_slp_cred_offset;
	u32 mtl_high_cred;
	u32 mtl_high_cred_offset;
	u32 mtl_low_cred;
	u32 mtl_low_cred_offset;
};

#define STMMAC_FLAG_HAS_INTEGRATED_PCS		BIT(0)
#define STMMAC_FLAG_SPH_DISABLE			BIT(1)
#define STMMAC_FLAG_USE_PHY_WOL			BIT(2)
#define STMMAC_FLAG_HAS_SUN8I			BIT(3)
#define STMMAC_FLAG_TSO_EN			BIT(4)
#define STMMAC_FLAG_SERDES_UP_AFTER_PHY_LINKUP	BIT(5)
#define STMMAC_FLAG_VLAN_FAIL_Q_EN		BIT(6)
#define STMMAC_FLAG_MULTI_MSI_EN		BIT(7)
#define STMMAC_FLAG_EXT_SNAPSHOT_EN		BIT(8)
#define STMMAC_FLAG_INT_SNAPSHOT_EN		BIT(9)
#define STMMAC_FLAG_RX_CLK_RUNS_IN_LPI		BIT(10)
#define STMMAC_FLAG_EN_TX_LPI_CLOCKGATING	BIT(11)
#define STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY	BIT(12)

struct plat_stmmacenet_data {
	int bus_id;
	int phy_addr;
	/* MAC ----- optional PCS ----- SerDes ----- optional PHY ----- Media
	 *       ^                               ^
	 * mac_interface                   phy_interface
	 *
	 * mac_interface is the MAC-side interface, which may be the same
	 * as phy_interface if there is no intervening PCS. If there is a
	 * PCS, then mac_interface describes the interface mode between the
	 * MAC and PCS, and phy_interface describes the interface mode
	 * between the PCS and PHY.
	 */
	phy_interface_t mac_interface;
	/* phy_interface is the PHY-side interface - the interface used by
	 * an attached PHY.
	 */
	phy_interface_t phy_interface;
	struct stmmac_mdio_bus_data *mdio_bus_data;
	struct device_node *phy_node;
	struct fwnode_handle *port_node;
	struct device_node *mdio_node;
	struct stmmac_dma_cfg *dma_cfg;
	struct stmmac_safety_feature_cfg *safety_feat_cfg;
	int clk_csr;
	int has_gmac;
	int enh_desc;
	int tx_coe;
	int rx_coe;
	int bugged_jumbo;
	int pmt;
	int force_sf_dma_mode;
	int force_thresh_dma_mode;
	int riwt_off;
	int max_speed;
	int maxmtu;
	int multicast_filter_bins;
	int unicast_filter_entries;
	int tx_fifo_size;
	int rx_fifo_size;
	u32 host_dma_width;
	u32 rx_queues_to_use;
	u32 tx_queues_to_use;
	u8 rx_sched_algorithm;
	u8 tx_sched_algorithm;
	struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES];
	struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES];
	void (*fix_mac_speed)(void *priv, unsigned int speed, unsigned int mode);
	int (*fix_soc_reset)(void *priv, void __iomem *ioaddr);
	int (*serdes_powerup)(struct net_device *ndev, void *priv);
	void (*serdes_powerdown)(struct net_device *ndev, void *priv);
	void (*speed_mode_2500)(struct net_device *ndev, void *priv);
	void (*ptp_clk_freq_config)(struct stmmac_priv *priv);
	int (*init)(struct platform_device *pdev, void *priv);
	void (*exit)(struct platform_device *pdev, void *priv);
	struct mac_device_info *(*setup)(void *priv);
	int (*clks_config)(void *priv, bool enabled);
	int (*crosststamp)(ktime_t *device, struct system_counterval_t *system,
			   void *ctx);
	void (*dump_debug_regs)(void *priv);
	int (*pcs_init)(struct stmmac_priv *priv);
	void (*pcs_exit)(struct stmmac_priv *priv);
	struct phylink_pcs *(*select_pcs)(struct stmmac_priv *priv,
					  phy_interface_t interface);
	void *bsp_priv;
	struct clk *stmmac_clk;
	struct clk *pclk;
	struct clk *clk_ptp_ref;
	unsigned int clk_ptp_rate;
	unsigned int clk_ref_rate;
	unsigned int mult_fact_100ns;
	s32 ptp_max_adj;
	u32 cdc_error_adj;
	struct reset_control *stmmac_rst;
	struct reset_control *stmmac_ahb_rst;
	struct stmmac_axi *axi;
	int has_gmac4;
	int rss_en;
	int mac_port_sel_speed;
	int has_xgmac;
	u8 vlan_fail_q;
	unsigned int eee_usecs_rate;
	struct pci_dev *pdev;
	int int_snapshot_num;
	int msi_mac_vec;
	int msi_wol_vec;
	int msi_lpi_vec;
	int msi_sfty_ce_vec;
	int msi_sfty_ue_vec;
	int msi_rx_base_vec;
	int msi_tx_base_vec;
	const struct dwmac4_addrs *dwmac4_addrs;
	unsigned int flags;
};
#endif
Commit	Line	Data
1237a75a	1	/* SPDX-License-Identifier: GPL-2.0-only */
3c9732c0 GC	2	/*******************************************************************************
	3
	4	Header file for stmmac platform data
	5
	6	Copyright (C) 2009 STMicroelectronics Ltd
	7
3c9732c0 GC	8
	9	Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
	10	*******************************************************************************/
	11
	12	#ifndef __STMMAC_PLATFORM_DATA
	13	#define __STMMAC_PLATFORM_DATA
	14
57a503c6	15	#include <linux/platform_device.h>
6c3282a6	16	#include <linux/phylink.h>
57a503c6	17
d976a525 JP	18	#define MTL_MAX_RX_QUEUES 8
d976a525 JP	19	#define MTL_MAX_TX_QUEUES 8
8fce3331	20	#define STMMAC_CH_MAX 8
d976a525	21
55f9a4d6 DS	22	#define STMMAC_RX_COE_NONE 0
	23	#define STMMAC_RX_COE_TYPE1 1
	24	#define STMMAC_RX_COE_TYPE2 2
	25
faeae3fa DS	26	/* Define the macros for CSR clock range parameters to be passed by
	27	* platform code.
	28	* This could also be configured at run time using CPU freq framework. */
	29
	30	/* MDC Clock Selection define*/
18f05d64 GC	31	#define STMMAC_CSR_60_100M 0x0 /* MDC = clk_scr_i/42 */
	32	#define STMMAC_CSR_100_150M 0x1 /* MDC = clk_scr_i/62 */
	33	#define STMMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */
	34	#define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */
	35	#define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */
	36	#define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */
faeae3fa	37
d976a525 JP	38	/* MTL algorithms identifiers */
	39	#define MTL_TX_ALGORITHM_WRR 0x0
	40	#define MTL_TX_ALGORITHM_WFQ 0x1
	41	#define MTL_TX_ALGORITHM_DWRR 0x2
	42	#define MTL_TX_ALGORITHM_SP 0x3
	43	#define MTL_RX_ALGORITHM_SP 0x4
	44	#define MTL_RX_ALGORITHM_WSP 0x5
	45
19d91873	46	/* RX/TX Queue Mode */
2d72d501 TR	47	#define MTL_QUEUE_AVB 0x0
2d72d501 TR	48	#define MTL_QUEUE_DCB 0x1
d976a525	49
18f05d64	50	/* The MDC clock could be set higher than the IEEE 802.3
faeae3fa DS	51	* specified frequency limit 0f 2.5 MHz, by programming a clock divider
	52	* of value different than the above defined values. The resultant MDIO
	53	* clock frequency of 12.5 MHz is applicable for the interfacing chips
	54	* supporting higher MDC clocks.
	55	* The MDC clock selection macros need to be defined for MDC clock rate
	56	* of 12.5 MHz, corresponding to the following selection.
18f05d64 GC	57	*/
	58	#define STMMAC_CSR_I_4 0x8 /* clk_csr_i/4 */
	59	#define STMMAC_CSR_I_6 0x9 /* clk_csr_i/6 */
	60	#define STMMAC_CSR_I_8 0xA /* clk_csr_i/8 */
	61	#define STMMAC_CSR_I_10 0xB /* clk_csr_i/10 */
	62	#define STMMAC_CSR_I_12 0xC /* clk_csr_i/12 */
	63	#define STMMAC_CSR_I_14 0xD /* clk_csr_i/14 */
	64	#define STMMAC_CSR_I_16 0xE /* clk_csr_i/16 */
	65	#define STMMAC_CSR_I_18 0xF /* clk_csr_i/18 */
faeae3fa	66
02582e9b	67	/* AXI DMA Burst length supported */
8327eb65 DS	68	#define DMA_AXI_BLEN_4 (1 << 1)
	69	#define DMA_AXI_BLEN_8 (1 << 2)
	70	#define DMA_AXI_BLEN_16 (1 << 3)
	71	#define DMA_AXI_BLEN_32 (1 << 4)
	72	#define DMA_AXI_BLEN_64 (1 << 5)
	73	#define DMA_AXI_BLEN_128 (1 << 6)
	74	#define DMA_AXI_BLEN_256 (1 << 7)
	75	#define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 \| DMA_AXI_BLEN_8 \| DMA_AXI_BLEN_16 \
	76	\| DMA_AXI_BLEN_32 \| DMA_AXI_BLEN_64 \
	77	\| DMA_AXI_BLEN_128 \| DMA_AXI_BLEN_256)
	78
d928d14b AH	79	struct stmmac_priv;
d928d14b AH	80
36bcfe7d GC	81	/* Platfrom data for platform device structure's platform_data field */
	82
	83	struct stmmac_mdio_bus_data {
36bcfe7d	84	unsigned int phy_mask;
351066ba	85	unsigned int pcs_mask;
83f55b01	86	unsigned int default_an_inband;
36bcfe7d GC	87	int *irqs;
36bcfe7d GC	88	int probed_phy_irq;
1a981c05	89	bool needs_reset;
36bcfe7d	90	};
3c9732c0	91
8327eb65 DS	92	struct stmmac_dma_cfg {
8327eb65 DS	93	int pbl;
89caaa2d NC	94	int txpbl;
89caaa2d NC	95	int rxpbl;
4022d039	96	bool pblx8;
8327eb65	97	int fixed_burst;
b9cde0a8	98	int mixed_burst;
afea0365	99	bool aal;
968a2978	100	bool eame;
6ccf12ae	101	bool multi_msi_en;
96874c61	102	bool dche;
12dbc67c	103	bool atds;
afea0365 GC	104	};
	105
	106	#define AXI_BLEN 7
	107	struct stmmac_axi {
	108	bool axi_lpi_en;
	109	bool axi_xit_frm;
	110	u32 axi_wr_osr_lmt;
	111	u32 axi_rd_osr_lmt;
	112	bool axi_kbbe;
afea0365 GC	113	u32 axi_blen[AXI_BLEN];
	114	bool axi_fb;
	115	bool axi_mb;
	116	bool axi_rb;
8327eb65 DS	117	};
8327eb65 DS	118
d976a525 JP	119	struct stmmac_rxq_cfg {
d976a525 JP	120	u8 mode_to_use;
e73b49eb	121	u32 chan;
abe80fdc	122	u8 pkt_route;
a8f5102a JP	123	bool use_prio;
a8f5102a JP	124	u32 prio;
d976a525 JP	125	};
	126
	127	struct stmmac_txq_cfg {
e73b49eb	128	u32 weight;
8452a05b	129	bool coe_unsupported;
19d91873 JP	130	u8 mode_to_use;
	131	/* Credit Base Shaper parameters */
	132	u32 send_slope;
	133	u32 idle_slope;
	134	u32 high_credit;
	135	u32 low_credit;
a8f5102a JP	136	bool use_prio;
a8f5102a JP	137	u32 prio;
579a25a8	138	int tbs_en;
d976a525 JP	139	};
d976a525 JP	140
5ac712dc WVK	141	struct stmmac_safety_feature_cfg {
	142	u32 tsoee;
	143	u32 mrxpee;
	144	u32 mestee;
	145	u32 mrxee;
	146	u32 mtxee;
	147	u32 epsi;
	148	u32 edpp;
	149	u32 prtyen;
	150	u32 tmouten;
	151	};
	152
33719b57 AH	153	/* Addresses that may be customized by a platform */
	154	struct dwmac4_addrs {
	155	u32 dma_chan;
	156	u32 dma_chan_offset;
	157	u32 mtl_chan;
	158	u32 mtl_chan_offset;
	159	u32 mtl_ets_ctrl;
	160	u32 mtl_ets_ctrl_offset;
	161	u32 mtl_txq_weight;
	162	u32 mtl_txq_weight_offset;
	163	u32 mtl_send_slp_cred;
	164	u32 mtl_send_slp_cred_offset;
	165	u32 mtl_high_cred;
	166	u32 mtl_high_cred_offset;
	167	u32 mtl_low_cred;
	168	u32 mtl_low_cred_offset;
	169	};
	170
d26979f1	171	#define STMMAC_FLAG_HAS_INTEGRATED_PCS BIT(0)
309efe6e	172	#define STMMAC_FLAG_SPH_DISABLE BIT(1)
fd1d62d8	173	#define STMMAC_FLAG_USE_PHY_WOL BIT(2)
d8daff28	174	#define STMMAC_FLAG_HAS_SUN8I BIT(3)
68861a3b	175	#define STMMAC_FLAG_TSO_EN BIT(4)
efe92571	176	#define STMMAC_FLAG_SERDES_UP_AFTER_PHY_LINKUP BIT(5)
fc02152b	177	#define STMMAC_FLAG_VLAN_FAIL_Q_EN BIT(6)
956c3f09	178	#define STMMAC_FLAG_MULTI_MSI_EN BIT(7)
aa5513f5	179	#define STMMAC_FLAG_EXT_SNAPSHOT_EN BIT(8)
621ba7ad	180	#define STMMAC_FLAG_INT_SNAPSHOT_EN BIT(9)
743dd1db	181	#define STMMAC_FLAG_RX_CLK_RUNS_IN_LPI BIT(10)
9d0c0d5e	182	#define STMMAC_FLAG_EN_TX_LPI_CLOCKGATING BIT(11)
26cfb838	183	#define STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY BIT(12)
d26979f1	184
3c9732c0 GC	185	struct plat_stmmacenet_data {
3c9732c0 GC	186	int bus_id;
36bcfe7d	187	int phy_addr;
a014c355 RKO	188	/* MAC ----- optional PCS ----- SerDes ----- optional PHY ----- Media
	189	* ^ ^
	190	* mac_interface phy_interface
	191	*
	192	* mac_interface is the MAC-side interface, which may be the same
	193	* as phy_interface if there is no intervening PCS. If there is a
	194	* PCS, then mac_interface describes the interface mode between the
	195	* MAC and PCS, and phy_interface describes the interface mode
	196	* between the PCS and PHY.
	197	*/
	198	phy_interface_t mac_interface;
	199	/* phy_interface is the PHY-side interface - the interface used by
	200	* an attached PHY.
	201	*/
0c65b2b9	202	phy_interface_t phy_interface;
36bcfe7d	203	struct stmmac_mdio_bus_data *mdio_bus_data;
5790cf3c	204	struct device_node *phy_node;
e80af2ac	205	struct fwnode_handle *port_node;
a7657f12	206	struct device_node *mdio_node;
8327eb65	207	struct stmmac_dma_cfg *dma_cfg;
5ac712dc	208	struct stmmac_safety_feature_cfg *safety_feat_cfg;
dfb8fb96	209	int clk_csr;
3c9732c0	210	int has_gmac;
e326e850	211	int enh_desc;
ebbb293f	212	int tx_coe;
55f9a4d6	213	int rx_coe;
ebbb293f	214	int bugged_jumbo;
543876c9	215	int pmt;
61b8013a	216	int force_sf_dma_mode;
e2a240c7	217	int force_thresh_dma_mode;
62a2ab93	218	int riwt_off;
9cbadf09	219	int max_speed;
2618abb7	220	int maxmtu;
3b57de95 VB	221	int multicast_filter_bins;
3b57de95 VB	222	int unicast_filter_entries;
e7877f52 VB	223	int tx_fifo_size;
e7877f52 VB	224	int rx_fifo_size;
070246e4	225	u32 host_dma_width;
e73b49eb BV	226	u32 rx_queues_to_use;
e73b49eb BV	227	u32 tx_queues_to_use;
d976a525 JP	228	u8 rx_sched_algorithm;
	229	u8 tx_sched_algorithm;
	230	struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES];
	231	struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES];
1fc04a0b	232	void (fix_mac_speed)(void priv, unsigned int speed, unsigned int mode);
10739ea3	233	int (fix_soc_reset)(void priv, void __iomem *ioaddr);
b9663b7c VW	234	int (serdes_powerup)(struct net_device ndev, void *priv);
b9663b7c VW	235	void (serdes_powerdown)(struct net_device ndev, void *priv);
46682cb8	236	void (speed_mode_2500)(struct net_device ndev, void *priv);
d928d14b	237	void (ptp_clk_freq_config)(struct stmmac_priv priv);
938dfdaa CYT	238	int (init)(struct platform_device pdev, void *priv);
938dfdaa CYT	239	void (exit)(struct platform_device pdev, void *priv);
ec33d71d	240	struct mac_device_info (setup)(void *priv);
b4d45aee	241	int (clks_config)(void priv, bool enabled);
341f67e4 TTM	242	int (crosststamp)(ktime_t device, struct system_counterval_t *system,
341f67e4 TTM	243	void *ctx);
4047b9db	244	void (dump_debug_regs)(void priv);
f0ef433f RKO	245	int (pcs_init)(struct stmmac_priv priv);
f0ef433f RKO	246	void (pcs_exit)(struct stmmac_priv priv);
6c3282a6 RKO	247	struct phylink_pcs (select_pcs)(struct stmmac_priv *priv,
6c3282a6 RKO	248	phy_interface_t interface);
3c9732c0	249	void *bsp_priv;
f573c0b9	250	struct clk *stmmac_clk;
	251	struct clk *pclk;
	252	struct clk *clk_ptp_ref;
	253	unsigned int clk_ptp_rate;
4ec5302f	254	unsigned int clk_ref_rate;
e80fe71b	255	unsigned int mult_fact_100ns;
190f73ab	256	s32 ptp_max_adj;
c6d5f193	257	u32 cdc_error_adj;
f573c0b9	258	struct reset_control *stmmac_rst;
e67f325e	259	struct reset_control *stmmac_ahb_rst;
afea0365	260	struct stmmac_axi *axi;
ee2ae1ed	261	int has_gmac4;
76067459	262	int rss_en;
02e57b9d	263	int mac_port_sel_speed;
48ae5554	264	int has_xgmac;
e0f9956a	265	u8 vlan_fail_q;
b4c5f83a	266	unsigned int eee_usecs_rate;
20e07e2c	267	struct pci_dev *pdev;
341f67e4	268	int int_snapshot_num;
8532f613 OBL	269	int msi_mac_vec;
	270	int msi_wol_vec;
	271	int msi_lpi_vec;
	272	int msi_sfty_ce_vec;
	273	int msi_sfty_ue_vec;
	274	int msi_rx_base_vec;
	275	int msi_tx_base_vec;
33719b57	276	const struct dwmac4_addrs *dwmac4_addrs;
d26979f1	277	unsigned int flags;
3c9732c0	278	};
3c9732c0	279	#endif