Commit | Line | Data |
---|---|---|
1237a75a | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
3c9732c0 GC |
2 | /******************************************************************************* |
3 | ||
4 | Header file for stmmac platform data | |
5 | ||
6 | Copyright (C) 2009 STMicroelectronics Ltd | |
7 | ||
3c9732c0 GC |
8 | |
9 | Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> | |
10 | *******************************************************************************/ | |
11 | ||
12 | #ifndef __STMMAC_PLATFORM_DATA | |
13 | #define __STMMAC_PLATFORM_DATA | |
14 | ||
57a503c6 | 15 | #include <linux/platform_device.h> |
0c65b2b9 | 16 | #include <linux/phy.h> |
57a503c6 | 17 | |
d976a525 JP |
18 | #define MTL_MAX_RX_QUEUES 8 |
19 | #define MTL_MAX_TX_QUEUES 8 | |
8fce3331 | 20 | #define STMMAC_CH_MAX 8 |
d976a525 | 21 | |
55f9a4d6 DS |
22 | #define STMMAC_RX_COE_NONE 0 |
23 | #define STMMAC_RX_COE_TYPE1 1 | |
24 | #define STMMAC_RX_COE_TYPE2 2 | |
25 | ||
faeae3fa DS |
26 | /* Define the macros for CSR clock range parameters to be passed by |
27 | * platform code. | |
28 | * This could also be configured at run time using CPU freq framework. */ | |
29 | ||
30 | /* MDC Clock Selection define*/ | |
18f05d64 GC |
31 | #define STMMAC_CSR_60_100M 0x0 /* MDC = clk_scr_i/42 */ |
32 | #define STMMAC_CSR_100_150M 0x1 /* MDC = clk_scr_i/62 */ | |
33 | #define STMMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */ | |
34 | #define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */ | |
35 | #define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */ | |
36 | #define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */ | |
faeae3fa | 37 | |
d976a525 JP |
38 | /* MTL algorithms identifiers */ |
39 | #define MTL_TX_ALGORITHM_WRR 0x0 | |
40 | #define MTL_TX_ALGORITHM_WFQ 0x1 | |
41 | #define MTL_TX_ALGORITHM_DWRR 0x2 | |
42 | #define MTL_TX_ALGORITHM_SP 0x3 | |
43 | #define MTL_RX_ALGORITHM_SP 0x4 | |
44 | #define MTL_RX_ALGORITHM_WSP 0x5 | |
45 | ||
19d91873 | 46 | /* RX/TX Queue Mode */ |
2d72d501 TR |
47 | #define MTL_QUEUE_AVB 0x0 |
48 | #define MTL_QUEUE_DCB 0x1 | |
d976a525 | 49 | |
18f05d64 | 50 | /* The MDC clock could be set higher than the IEEE 802.3 |
faeae3fa DS |
51 | * specified frequency limit 0f 2.5 MHz, by programming a clock divider |
52 | * of value different than the above defined values. The resultant MDIO | |
53 | * clock frequency of 12.5 MHz is applicable for the interfacing chips | |
54 | * supporting higher MDC clocks. | |
55 | * The MDC clock selection macros need to be defined for MDC clock rate | |
56 | * of 12.5 MHz, corresponding to the following selection. | |
18f05d64 GC |
57 | */ |
58 | #define STMMAC_CSR_I_4 0x8 /* clk_csr_i/4 */ | |
59 | #define STMMAC_CSR_I_6 0x9 /* clk_csr_i/6 */ | |
60 | #define STMMAC_CSR_I_8 0xA /* clk_csr_i/8 */ | |
61 | #define STMMAC_CSR_I_10 0xB /* clk_csr_i/10 */ | |
62 | #define STMMAC_CSR_I_12 0xC /* clk_csr_i/12 */ | |
63 | #define STMMAC_CSR_I_14 0xD /* clk_csr_i/14 */ | |
64 | #define STMMAC_CSR_I_16 0xE /* clk_csr_i/16 */ | |
65 | #define STMMAC_CSR_I_18 0xF /* clk_csr_i/18 */ | |
faeae3fa | 66 | |
02582e9b | 67 | /* AXI DMA Burst length supported */ |
8327eb65 DS |
68 | #define DMA_AXI_BLEN_4 (1 << 1) |
69 | #define DMA_AXI_BLEN_8 (1 << 2) | |
70 | #define DMA_AXI_BLEN_16 (1 << 3) | |
71 | #define DMA_AXI_BLEN_32 (1 << 4) | |
72 | #define DMA_AXI_BLEN_64 (1 << 5) | |
73 | #define DMA_AXI_BLEN_128 (1 << 6) | |
74 | #define DMA_AXI_BLEN_256 (1 << 7) | |
75 | #define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \ | |
76 | | DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \ | |
77 | | DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256) | |
78 | ||
36bcfe7d GC |
79 | /* Platfrom data for platform device structure's platform_data field */ |
80 | ||
81 | struct stmmac_mdio_bus_data { | |
36bcfe7d | 82 | unsigned int phy_mask; |
f213bbe8 | 83 | unsigned int has_xpcs; |
e5e5b771 | 84 | unsigned int xpcs_an_inband; |
36bcfe7d GC |
85 | int *irqs; |
86 | int probed_phy_irq; | |
1a981c05 | 87 | bool needs_reset; |
36bcfe7d | 88 | }; |
3c9732c0 | 89 | |
8327eb65 DS |
90 | struct stmmac_dma_cfg { |
91 | int pbl; | |
89caaa2d NC |
92 | int txpbl; |
93 | int rxpbl; | |
4022d039 | 94 | bool pblx8; |
8327eb65 | 95 | int fixed_burst; |
b9cde0a8 | 96 | int mixed_burst; |
afea0365 | 97 | bool aal; |
968a2978 | 98 | bool eame; |
6ccf12ae | 99 | bool multi_msi_en; |
96874c61 | 100 | bool dche; |
afea0365 GC |
101 | }; |
102 | ||
103 | #define AXI_BLEN 7 | |
104 | struct stmmac_axi { | |
105 | bool axi_lpi_en; | |
106 | bool axi_xit_frm; | |
107 | u32 axi_wr_osr_lmt; | |
108 | u32 axi_rd_osr_lmt; | |
109 | bool axi_kbbe; | |
afea0365 GC |
110 | u32 axi_blen[AXI_BLEN]; |
111 | bool axi_fb; | |
112 | bool axi_mb; | |
113 | bool axi_rb; | |
8327eb65 DS |
114 | }; |
115 | ||
504723af JA |
116 | #define EST_GCL 1024 |
117 | struct stmmac_est { | |
b2aae654 | 118 | struct mutex lock; |
504723af | 119 | int enable; |
e9e37200 | 120 | u32 btr_reserve[2]; |
504723af JA |
121 | u32 btr_offset[2]; |
122 | u32 btr[2]; | |
123 | u32 ctr[2]; | |
124 | u32 ter; | |
125 | u32 gcl_unaligned[EST_GCL]; | |
126 | u32 gcl[EST_GCL]; | |
127 | u32 gcl_size; | |
128 | }; | |
129 | ||
d976a525 JP |
130 | struct stmmac_rxq_cfg { |
131 | u8 mode_to_use; | |
e73b49eb | 132 | u32 chan; |
abe80fdc | 133 | u8 pkt_route; |
a8f5102a JP |
134 | bool use_prio; |
135 | u32 prio; | |
d976a525 JP |
136 | }; |
137 | ||
138 | struct stmmac_txq_cfg { | |
e73b49eb | 139 | u32 weight; |
19d91873 JP |
140 | u8 mode_to_use; |
141 | /* Credit Base Shaper parameters */ | |
142 | u32 send_slope; | |
143 | u32 idle_slope; | |
144 | u32 high_credit; | |
145 | u32 low_credit; | |
a8f5102a JP |
146 | bool use_prio; |
147 | u32 prio; | |
579a25a8 | 148 | int tbs_en; |
d976a525 JP |
149 | }; |
150 | ||
5a558611 OBL |
151 | /* FPE link state */ |
152 | enum stmmac_fpe_state { | |
153 | FPE_STATE_OFF = 0, | |
154 | FPE_STATE_CAPABLE = 1, | |
155 | FPE_STATE_ENTERING_ON = 2, | |
156 | FPE_STATE_ON = 3, | |
157 | }; | |
158 | ||
159 | /* FPE link-partner hand-shaking mPacket type */ | |
160 | enum stmmac_mpacket_type { | |
161 | MPACKET_VERIFY = 0, | |
162 | MPACKET_RESPONSE = 1, | |
163 | }; | |
164 | ||
165 | enum stmmac_fpe_task_state_t { | |
166 | __FPE_REMOVING, | |
167 | __FPE_TASK_SCHED, | |
168 | }; | |
169 | ||
170 | struct stmmac_fpe_cfg { | |
171 | bool enable; /* FPE enable */ | |
172 | bool hs_enable; /* FPE handshake enable */ | |
173 | enum stmmac_fpe_state lp_fpe_state; /* Link Partner FPE state */ | |
174 | enum stmmac_fpe_state lo_fpe_state; /* Local station FPE state */ | |
175 | }; | |
176 | ||
5ac712dc WVK |
177 | struct stmmac_safety_feature_cfg { |
178 | u32 tsoee; | |
179 | u32 mrxpee; | |
180 | u32 mestee; | |
181 | u32 mrxee; | |
182 | u32 mtxee; | |
183 | u32 epsi; | |
184 | u32 edpp; | |
185 | u32 prtyen; | |
186 | u32 tmouten; | |
187 | }; | |
188 | ||
33719b57 AH |
189 | /* Addresses that may be customized by a platform */ |
190 | struct dwmac4_addrs { | |
191 | u32 dma_chan; | |
192 | u32 dma_chan_offset; | |
193 | u32 mtl_chan; | |
194 | u32 mtl_chan_offset; | |
195 | u32 mtl_ets_ctrl; | |
196 | u32 mtl_ets_ctrl_offset; | |
197 | u32 mtl_txq_weight; | |
198 | u32 mtl_txq_weight_offset; | |
199 | u32 mtl_send_slp_cred; | |
200 | u32 mtl_send_slp_cred_offset; | |
201 | u32 mtl_high_cred; | |
202 | u32 mtl_high_cred_offset; | |
203 | u32 mtl_low_cred; | |
204 | u32 mtl_low_cred_offset; | |
205 | }; | |
206 | ||
3c9732c0 GC |
207 | struct plat_stmmacenet_data { |
208 | int bus_id; | |
36bcfe7d GC |
209 | int phy_addr; |
210 | int interface; | |
0c65b2b9 | 211 | phy_interface_t phy_interface; |
36bcfe7d | 212 | struct stmmac_mdio_bus_data *mdio_bus_data; |
5790cf3c | 213 | struct device_node *phy_node; |
4838a540 | 214 | struct device_node *phylink_node; |
a7657f12 | 215 | struct device_node *mdio_node; |
8327eb65 | 216 | struct stmmac_dma_cfg *dma_cfg; |
504723af | 217 | struct stmmac_est *est; |
5a558611 | 218 | struct stmmac_fpe_cfg *fpe_cfg; |
5ac712dc | 219 | struct stmmac_safety_feature_cfg *safety_feat_cfg; |
dfb8fb96 | 220 | int clk_csr; |
3c9732c0 | 221 | int has_gmac; |
e326e850 | 222 | int enh_desc; |
ebbb293f | 223 | int tx_coe; |
55f9a4d6 | 224 | int rx_coe; |
ebbb293f | 225 | int bugged_jumbo; |
543876c9 | 226 | int pmt; |
61b8013a | 227 | int force_sf_dma_mode; |
e2a240c7 | 228 | int force_thresh_dma_mode; |
62a2ab93 | 229 | int riwt_off; |
9cbadf09 | 230 | int max_speed; |
2618abb7 | 231 | int maxmtu; |
3b57de95 VB |
232 | int multicast_filter_bins; |
233 | int unicast_filter_entries; | |
e7877f52 VB |
234 | int tx_fifo_size; |
235 | int rx_fifo_size; | |
070246e4 | 236 | u32 host_dma_width; |
e73b49eb BV |
237 | u32 rx_queues_to_use; |
238 | u32 tx_queues_to_use; | |
d976a525 JP |
239 | u8 rx_sched_algorithm; |
240 | u8 tx_sched_algorithm; | |
241 | struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES]; | |
242 | struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES]; | |
3c9732c0 | 243 | void (*fix_mac_speed)(void *priv, unsigned int speed); |
10739ea3 | 244 | int (*fix_soc_reset)(void *priv, void __iomem *ioaddr); |
b9663b7c VW |
245 | int (*serdes_powerup)(struct net_device *ndev, void *priv); |
246 | void (*serdes_powerdown)(struct net_device *ndev, void *priv); | |
46682cb8 | 247 | void (*speed_mode_2500)(struct net_device *ndev, void *priv); |
76da35dc | 248 | void (*ptp_clk_freq_config)(void *priv); |
938dfdaa CYT |
249 | int (*init)(struct platform_device *pdev, void *priv); |
250 | void (*exit)(struct platform_device *pdev, void *priv); | |
ec33d71d | 251 | struct mac_device_info *(*setup)(void *priv); |
b4d45aee | 252 | int (*clks_config)(void *priv, bool enabled); |
341f67e4 TTM |
253 | int (*crosststamp)(ktime_t *device, struct system_counterval_t *system, |
254 | void *ctx); | |
4047b9db | 255 | void (*dump_debug_regs)(void *priv); |
3c9732c0 | 256 | void *bsp_priv; |
f573c0b9 | 257 | struct clk *stmmac_clk; |
258 | struct clk *pclk; | |
259 | struct clk *clk_ptp_ref; | |
260 | unsigned int clk_ptp_rate; | |
4ec5302f | 261 | unsigned int clk_ref_rate; |
e80fe71b | 262 | unsigned int mult_fact_100ns; |
190f73ab | 263 | s32 ptp_max_adj; |
c6d5f193 | 264 | u32 cdc_error_adj; |
f573c0b9 | 265 | struct reset_control *stmmac_rst; |
e67f325e | 266 | struct reset_control *stmmac_ahb_rst; |
afea0365 | 267 | struct stmmac_axi *axi; |
ee2ae1ed | 268 | int has_gmac4; |
9f93ac8d | 269 | bool has_sun8i; |
ee2ae1ed | 270 | bool tso_en; |
76067459 | 271 | int rss_en; |
02e57b9d | 272 | int mac_port_sel_speed; |
b4b7b772 | 273 | bool en_tx_lpi_clockgating; |
54aa39a5 | 274 | bool rx_clk_runs_in_lpi; |
48ae5554 | 275 | int has_xgmac; |
e0f9956a CKT |
276 | bool vlan_fail_q_en; |
277 | u8 vlan_fail_q; | |
b4c5f83a | 278 | unsigned int eee_usecs_rate; |
20e07e2c | 279 | struct pci_dev *pdev; |
341f67e4 | 280 | int int_snapshot_num; |
f4da5652 | 281 | int ext_snapshot_num; |
76c16d3e | 282 | bool int_snapshot_en; |
f4da5652 | 283 | bool ext_snapshot_en; |
8532f613 OBL |
284 | bool multi_msi_en; |
285 | int msi_mac_vec; | |
286 | int msi_wol_vec; | |
287 | int msi_lpi_vec; | |
288 | int msi_sfty_ce_vec; | |
289 | int msi_sfty_ue_vec; | |
290 | int msi_rx_base_vec; | |
291 | int msi_tx_base_vec; | |
5a9b876e | 292 | bool use_phy_wol; |
47f753c1 | 293 | bool sph_disable; |
a46e9010 | 294 | bool serdes_up_after_phy_linkup; |
33719b57 | 295 | const struct dwmac4_addrs *dwmac4_addrs; |
aa571b62 | 296 | bool has_integrated_pcs; |
3c9732c0 | 297 | }; |
3c9732c0 | 298 | #endif |