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ssb: add GPIO driver
[linux-2.6-block.git] / include / linux / ssb / ssb.h
CommitLineData
61e115a5
MB		 1#ifndef LINUX_SSB_H_
2#define LINUX_SSB_H_
3
4#include <linux/device.h>
5#include <linux/list.h>
6#include <linux/types.h>
7#include <linux/spinlock.h>
8#include <linux/pci.h>
ec43b08b 9#include <linux/gpio.h>
61e115a5 10#include <linux/mod_devicetable.h>
9c0c7a42 11#include <linux/dma-mapping.h>
61e115a5
MB		 12
13#include <linux/ssb/ssb_regs.h>
14
15
16struct pcmcia_device;
17struct ssb_bus;
18struct ssb_driver;
19
b0f70292
RM		 20struct ssb_sprom_core_pwr_info {
21 u8 itssi_2g, itssi_5g;
22 u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
3b64e6f9 23 u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4];
b0f70292
RM		 24};
25
61e115a5
MB		 26struct ssb_sprom {
27 u8 revision;
ac82fab4
LF		 28 u8 il0mac[6]; /* MAC address for 802.11b/g */
29 u8 et0mac[6]; /* MAC address for Ethernet */
30 u8 et1mac[6]; /* MAC address for 802.11a */
31 u8 et0phyaddr; /* MII address for enet0 */
32 u8 et1phyaddr; /* MII address for enet1 */
e861b98d
MB		 33 u8 et0mdcport; /* MDIO for enet0 */
34 u8 et1mdcport; /* MDIO for enet1 */
e2d646ce 35 u16 board_rev; /* Board revision number from SPROM. */
52aa63f5
HM		 36 u16 board_num; /* Board number from SPROM. */
37 u16 board_type; /* Board type from SPROM. */
ac82fab4 38 u8 country_code; /* Country Code */
03a5642b 39 char alpha2[2]; /* Country Code as two chars like EU or US */
edd8d90b
HM		 40 u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */
41 u8 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
f679056b
GS		 42 u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
43 u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
ac82fab4
LF		 44 u16 pa0b0;
45 u16 pa0b1;
46 u16 pa0b2;
47 u16 pa1b0;
48 u16 pa1b1;
49 u16 pa1b2;
f679056b
GS		 50 u16 pa1lob0;
51 u16 pa1lob1;
52 u16 pa1lob2;
53 u16 pa1hib0;
54 u16 pa1hib1;
55 u16 pa1hib2;
ac82fab4
LF		 56 u8 gpio0; /* GPIO pin 0 */
57 u8 gpio1; /* GPIO pin 1 */
58 u8 gpio2; /* GPIO pin 2 */
59 u8 gpio3; /* GPIO pin 3 */
edd8d90b
HM		 60 u8 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
61 u8 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
62 u8 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
63 u8 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
ac82fab4
LF		 64 u8 itssi_a; /* Idle TSSI Target for A-PHY */
65 u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
f679056b
GS		 66 u8 tri2g; /* 2.4GHz TX isolation */
67 u8 tri5gl; /* 5.2GHz TX isolation */
68 u8 tri5g; /* 5.3GHz TX isolation */
69 u8 tri5gh; /* 5.8GHz TX isolation */
172c69a4
RM		 70 u8 txpid2g[4]; /* 2GHz TX power index */
71 u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
72 u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
73 u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
edd8d90b
HM		 74 s8 rxpo2g; /* 2GHz RX power offset */
75 s8 rxpo5g; /* 5GHz RX power offset */
f679056b
GS		 76 u8 rssisav2g; /* 2GHz RSSI params */
77 u8 rssismc2g;
78 u8 rssismf2g;
79 u8 bxa2g; /* 2GHz BX arch */
80 u8 rssisav5g; /* 5GHz RSSI params */
81 u8 rssismc5g;
82 u8 rssismf5g;
83 u8 bxa5g; /* 5GHz BX arch */
84 u16 cck2gpo; /* CCK power offset */
85 u32 ofdm2gpo; /* 2.4GHz OFDM power offset */
86 u32 ofdm5glpo; /* 5.2GHz OFDM power offset */
87 u32 ofdm5gpo; /* 5.3GHz OFDM power offset */
88 u32 ofdm5ghpo; /* 5.8GHz OFDM power offset */
89 u16 boardflags_lo; /* Board flags (bits 0-15) */
90 u16 boardflags_hi; /* Board flags (bits 16-31) */
91 u16 boardflags2_lo; /* Board flags (bits 32-47) */
92 u16 boardflags2_hi; /* Board flags (bits 48-63) */
93 /* TODO store board flags in a single u64 */
e861b98d 94
b0f70292
RM		 95 struct ssb_sprom_core_pwr_info core_pwr_info[4];
96
e861b98d
MB		 97 /* Antenna gain values for up to 4 antennas
98 * on each band. Values in dBm/4 (Q5.2). Negative gain means the
99 * loss in the connectors is bigger than the gain. */
100 struct {
f8f8a660 101 s8 a0, a1, a2, a3;
e861b98d 102 } antenna_gain;
ac82fab4 103
8a5ac6ec
RM		 104 struct {
105 struct {
106 u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
107 } ghz2;
108 struct {
109 u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
110 } ghz5;
111 } fem;
112
52aa63f5
HM		 113 u16 mcs2gpo[8];
114 u16 mcs5gpo[8];
115 u16 mcs5glpo[8];
116 u16 mcs5ghpo[8];
117 u8 opo;
118
119 u8 rxgainerr2ga[3];
120 u8 rxgainerr5gla[3];
121 u8 rxgainerr5gma[3];
122 u8 rxgainerr5gha[3];
123 u8 rxgainerr5gua[3];
124
125 u8 noiselvl2ga[3];
126 u8 noiselvl5gla[3];
127 u8 noiselvl5gma[3];
128 u8 noiselvl5gha[3];
129 u8 noiselvl5gua[3];
130
131 u8 regrev;
132 u8 txchain;
133 u8 rxchain;
134 u8 antswitch;
135 u16 cddpo;
136 u16 stbcpo;
137 u16 bw40po;
138 u16 bwduppo;
139
140 u8 tempthresh;
141 u8 tempoffset;
142 u16 rawtempsense;
143 u8 measpower;
144 u8 tempsense_slope;
145 u8 tempcorrx;
146 u8 tempsense_option;
147 u8 freqoffset_corr;
148 u8 iqcal_swp_dis;
149 u8 hw_iqcal_en;
150 u8 elna2g;
151 u8 elna5g;
152 u8 phycal_tempdelta;
153 u8 temps_period;
154 u8 temps_hysteresis;
155 u8 measpower1;
156 u8 measpower2;
157 u8 pcieingress_war;
158
159 /* power per rate from sromrev 9 */
160 u16 cckbw202gpo;
161 u16 cckbw20ul2gpo;
162 u32 legofdmbw202gpo;
163 u32 legofdmbw20ul2gpo;
164 u32 legofdmbw205glpo;
165 u32 legofdmbw20ul5glpo;
166 u32 legofdmbw205gmpo;
167 u32 legofdmbw20ul5gmpo;
168 u32 legofdmbw205ghpo;
169 u32 legofdmbw20ul5ghpo;
170 u32 mcsbw202gpo;
171 u32 mcsbw20ul2gpo;
172 u32 mcsbw402gpo;
173 u32 mcsbw205glpo;
174 u32 mcsbw20ul5glpo;
175 u32 mcsbw405glpo;
176 u32 mcsbw205gmpo;
177 u32 mcsbw20ul5gmpo;
178 u32 mcsbw405gmpo;
179 u32 mcsbw205ghpo;
180 u32 mcsbw20ul5ghpo;
181 u32 mcsbw405ghpo;
182 u16 mcs32po;
183 u16 legofdm40duppo;
184 u8 sar2g;
185 u8 sar5g;
61e115a5
MB		 186};
187
188/* Information about the PCB the circuitry is soldered on. */
189struct ssb_boardinfo {
190 u16 vendor;
191 u16 type;
61e115a5
MB		 192};
193
194
195struct ssb_device;
196/* Lowlevel read/write operations on the device MMIO.
197 * Internal, don't use that outside of ssb. */
198struct ssb_bus_ops {
ffc7689d 199 u8 (*read8)(struct ssb_device *dev, u16 offset);
61e115a5
MB		 200 u16 (*read16)(struct ssb_device *dev, u16 offset);
201 u32 (*read32)(struct ssb_device *dev, u16 offset);
ffc7689d 202 void (*write8)(struct ssb_device *dev, u16 offset, u8 value);
61e115a5
MB		 203 void (*write16)(struct ssb_device *dev, u16 offset, u16 value);
204 void (*write32)(struct ssb_device *dev, u16 offset, u32 value);
d625a29b
MB		 205#ifdef CONFIG_SSB_BLOCKIO
206 void (*block_read)(struct ssb_device *dev, void *buffer,
207 size_t count, u16 offset, u8 reg_width);
208 void (*block_write)(struct ssb_device *dev, const void *buffer,
209 size_t count, u16 offset, u8 reg_width);
210#endif
61e115a5
MB		 211};
212
213
214/* Core-ID values. */
215#define SSB_DEV_CHIPCOMMON 0x800
216#define SSB_DEV_ILINE20 0x801
217#define SSB_DEV_SDRAM 0x803
218#define SSB_DEV_PCI 0x804
219#define SSB_DEV_MIPS 0x805
220#define SSB_DEV_ETHERNET 0x806
221#define SSB_DEV_V90 0x807
222#define SSB_DEV_USB11_HOSTDEV 0x808
223#define SSB_DEV_ADSL 0x809
224#define SSB_DEV_ILINE100 0x80A
225#define SSB_DEV_IPSEC 0x80B
226#define SSB_DEV_PCMCIA 0x80D
227#define SSB_DEV_INTERNAL_MEM 0x80E
228#define SSB_DEV_MEMC_SDRAM 0x80F
229#define SSB_DEV_EXTIF 0x811
230#define SSB_DEV_80211 0x812
231#define SSB_DEV_MIPS_3302 0x816
232#define SSB_DEV_USB11_HOST 0x817
233#define SSB_DEV_USB11_DEV 0x818
234#define SSB_DEV_USB20_HOST 0x819
235#define SSB_DEV_USB20_DEV 0x81A
236#define SSB_DEV_SDIO_HOST 0x81B
237#define SSB_DEV_ROBOSWITCH 0x81C
238#define SSB_DEV_PARA_ATA 0x81D
239#define SSB_DEV_SATA_XORDMA 0x81E
240#define SSB_DEV_ETHERNET_GBIT 0x81F
241#define SSB_DEV_PCIE 0x820
242#define SSB_DEV_MIMO_PHY 0x821
243#define SSB_DEV_SRAM_CTRLR 0x822
244#define SSB_DEV_MINI_MACPHY 0x823
245#define SSB_DEV_ARM_1176 0x824
246#define SSB_DEV_ARM_7TDMI 0x825
ccaf8c32 247#define SSB_DEV_ARM_CM3 0x82A
61e115a5
MB		 248
249/* Vendor-ID values */
250#define SSB_VENDOR_BROADCOM 0x4243
251
252/* Some kernel subsystems poke with dev->drvdata, so we must use the
253 * following ugly workaround to get from struct device to struct ssb_device */
254struct __ssb_dev_wrapper {
255 struct device dev;
256 struct ssb_device *sdev;
257};
258
259struct ssb_device {
260 /* Having a copy of the ops pointer in each dev struct
261 * is an optimization. */
262 const struct ssb_bus_ops *ops;
263
14f92952 264 struct device *dev, *dma_dev;
4ac58469 265
61e115a5
MB		 266 struct ssb_bus *bus;
267 struct ssb_device_id id;
268
269 u8 core_index;
270 unsigned int irq;
271
272 /* Internal-only stuff follows. */
273 void *drvdata; /* Per-device data */
274 void *devtypedata; /* Per-devicetype (eg 802.11) data */
275};
276
277/* Go from struct device to struct ssb_device. */
278static inline
279struct ssb_device * dev_to_ssb_dev(struct device *dev)
280{
281 struct __ssb_dev_wrapper *wrap;
282 wrap = container_of(dev, struct __ssb_dev_wrapper, dev);
283 return wrap->sdev;
284}
285
286/* Device specific user data */
287static inline
288void ssb_set_drvdata(struct ssb_device *dev, void *data)
289{
290 dev->drvdata = data;
291}
292static inline
293void * ssb_get_drvdata(struct ssb_device *dev)
294{
295 return dev->drvdata;
296}
297
298/* Devicetype specific user data. This is per device-type (not per device) */
299void ssb_set_devtypedata(struct ssb_device *dev, void *data);
300static inline
301void * ssb_get_devtypedata(struct ssb_device *dev)
302{
303 return dev->devtypedata;
304}
305
306
307struct ssb_driver {
308 const char *name;
309 const struct ssb_device_id *id_table;
310
311 int (*probe)(struct ssb_device *dev, const struct ssb_device_id *id);
312 void (*remove)(struct ssb_device *dev);
313 int (*suspend)(struct ssb_device *dev, pm_message_t state);
314 int (*resume)(struct ssb_device *dev);
315 void (*shutdown)(struct ssb_device *dev);
316
317 struct device_driver drv;
318};
319#define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
320
321extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
eb5589a8
PG		 322#define ssb_driver_register(drv) \
323 __ssb_driver_register(drv, THIS_MODULE)
324
61e115a5
MB		 325extern void ssb_driver_unregister(struct ssb_driver *drv);
326
327
328
329
330enum ssb_bustype {
331 SSB_BUSTYPE_SSB, /* This SSB bus is the system bus */
332 SSB_BUSTYPE_PCI, /* SSB is connected to PCI bus */
333 SSB_BUSTYPE_PCMCIA, /* SSB is connected to PCMCIA bus */
24ea602e 334 SSB_BUSTYPE_SDIO, /* SSB is connected to SDIO bus */
61e115a5
MB		 335};
336
337/* board_vendor */
338#define SSB_BOARDVENDOR_BCM 0x14E4 /* Broadcom */
339#define SSB_BOARDVENDOR_DELL 0x1028 /* Dell */
340#define SSB_BOARDVENDOR_HP 0x0E11 /* HP */
341/* board_type */
342#define SSB_BOARD_BCM94306MP 0x0418
343#define SSB_BOARD_BCM4309G 0x0421
344#define SSB_BOARD_BCM4306CB 0x0417
345#define SSB_BOARD_BCM4309MP 0x040C
346#define SSB_BOARD_MP4318 0x044A
347#define SSB_BOARD_BU4306 0x0416
348#define SSB_BOARD_BU4309 0x040A
349/* chip_package */
350#define SSB_CHIPPACK_BCM4712S 1 /* Small 200pin 4712 */
351#define SSB_CHIPPACK_BCM4712M 2 /* Medium 225pin 4712 */
352#define SSB_CHIPPACK_BCM4712L 0 /* Large 340pin 4712 */
353
354#include <linux/ssb/ssb_driver_chipcommon.h>
355#include <linux/ssb/ssb_driver_mips.h>
356#include <linux/ssb/ssb_driver_extif.h>
357#include <linux/ssb/ssb_driver_pci.h>
358
359struct ssb_bus {
360 /* The MMIO area. */
361 void __iomem *mmio;
362
363 const struct ssb_bus_ops *ops;
364
8b45499c
MB		 365 /* The core currently mapped into the MMIO window.
366 * Not valid on all host-buses. So don't use outside of SSB. */
61e115a5 367 struct ssb_device *mapped_device;
24ea602e
AH		 368 union {
369 /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
370 u8 mapped_pcmcia_seg;
371 /* Current SSB base address window for SDIO. */
372 u32 sdio_sbaddr;
373 };
993e1c78
MB		 374 /* Lock for core and segment switching.
375 * On PCMCIA-host busses this is used to protect the whole MMIO access. */
61e115a5
MB		 376 spinlock_t bar_lock;
377
8b45499c 378 /* The host-bus this backplane is running on. */
61e115a5 379 enum ssb_bustype bustype;
8b45499c
MB		 380 /* Pointers to the host-bus. Check bustype before using any of these pointers. */
381 union {
382 /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
383 struct pci_dev *host_pci;
384 /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
385 struct pcmcia_device *host_pcmcia;
386 /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
387 struct sdio_func *host_sdio;
388 };
24ea602e
AH		 389
390 /* See enum ssb_quirks */
391 unsigned int quirks;
61e115a5 392
e7ec2e32 393#ifdef CONFIG_SSB_SPROM
61e115a5 394 /* Mutex to protect the SPROM writing. */
e7ec2e32 395 struct mutex sprom_mutex;
61e115a5
MB		 396#endif
397
398 /* ID information about the Chip. */
399 u16 chip_id;
ce57d9e6 400 u8 chip_rev;
ea2db495 401 u16 sprom_offset;
c272ef44 402 u16 sprom_size; /* number of words in sprom */
61e115a5
MB		 403 u8 chip_package;
404
405 /* List of devices (cores) on the backplane. */
406 struct ssb_device devices[SSB_MAX_NR_CORES];
407 u8 nr_devices;
408
61e115a5
MB		 409 /* Software ID number for this bus. */
410 unsigned int busnumber;
411
412 /* The ChipCommon device (if available). */
413 struct ssb_chipcommon chipco;
414 /* The PCI-core device (if available). */
415 struct ssb_pcicore pcicore;
416 /* The MIPS-core device (if available). */
417 struct ssb_mipscore mipscore;
418 /* The EXTif-core device (if available). */
419 struct ssb_extif extif;
420
421 /* The following structure elements are not available in early
422 * SSB initialization. Though, they are available for regular
423 * registered drivers at any stage. So be careful when
424 * using them in the ssb core code. */
425
426 /* ID information about the PCB. */
427 struct ssb_boardinfo boardinfo;
428 /* Contents of the SPROM. */
429 struct ssb_sprom sprom;
7cb44615
MB		 430 /* If the board has a cardbus slot, this is set to true. */
431 bool has_cardbus_slot;
61e115a5 432
53521d8c
MB		 433#ifdef CONFIG_SSB_EMBEDDED
434 /* Lock for GPIO register access. */
435 spinlock_t gpio_lock;
436#endif /* EMBEDDED */
ec43b08b
HM		 437#ifdef CONFIG_SSB_DRIVER_GPIO
438 struct gpio_chip gpio;
439#endif /* DRIVER_GPIO */
53521d8c 440
61e115a5
MB		 441 /* Internal-only stuff follows. Do not touch. */
442 struct list_head list;
443#ifdef CONFIG_SSB_DEBUG
444 /* Is the bus already powered up? */
445 bool powered_up;
446 int power_warn_count;
447#endif /* DEBUG */
448};
449
24ea602e
AH		 450enum ssb_quirks {
451 /* SDIO connected card requires performing a read after writing a 32-bit value */
452 SSB_QUIRK_SDIO_READ_AFTER_WRITE32 = (1 << 0),
453};
454
61e115a5
MB		 455/* The initialization-invariants. */
456struct ssb_init_invariants {
7cb44615 457 /* Versioning information about the PCB. */
61e115a5 458 struct ssb_boardinfo boardinfo;
7cb44615
MB		 459 /* The SPROM information. That's either stored in an
460 * EEPROM or NVRAM on the board. */
61e115a5 461 struct ssb_sprom sprom;
7cb44615
MB		 462 /* If the board has a cardbus slot, this is set to true. */
463 bool has_cardbus_slot;
61e115a5
MB		 464};
465/* Type of function to fetch the invariants. */
466typedef int (*ssb_invariants_func_t)(struct ssb_bus *bus,
467 struct ssb_init_invariants *iv);
468
469/* Register a SSB system bus. get_invariants() is called after the
470 * basic system devices are initialized.
471 * The invariants are usually fetched from some NVRAM.
472 * Put the invariants into the struct pointed to by iv. */
473extern int ssb_bus_ssbbus_register(struct ssb_bus *bus,
474 unsigned long baseaddr,
475 ssb_invariants_func_t get_invariants);
476#ifdef CONFIG_SSB_PCIHOST
477extern int ssb_bus_pcibus_register(struct ssb_bus *bus,
478 struct pci_dev *host_pci);
479#endif /* CONFIG_SSB_PCIHOST */
480#ifdef CONFIG_SSB_PCMCIAHOST
481extern int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
482 struct pcmcia_device *pcmcia_dev,
483 unsigned long baseaddr);
484#endif /* CONFIG_SSB_PCMCIAHOST */
24ea602e
AH		 485#ifdef CONFIG_SSB_SDIOHOST
486extern int ssb_bus_sdiobus_register(struct ssb_bus *bus,
487 struct sdio_func *sdio_func,
488 unsigned int quirks);
489#endif /* CONFIG_SSB_SDIOHOST */
490
61e115a5
MB		 491
492extern void ssb_bus_unregister(struct ssb_bus *bus);
493
d53cdbb9
JL		 494/* Does the device have an SPROM? */
495extern bool ssb_is_sprom_available(struct ssb_bus *bus);
496
e79c1ba8
MB		 497/* Set a fallback SPROM.
498 * See kdoc at the function definition for complete documentation. */
b3ae52b6
HM		 499extern int ssb_arch_register_fallback_sprom(
500 int (*sprom_callback)(struct ssb_bus *bus,
501 struct ssb_sprom *out));
e79c1ba8 502
8fe2b65a
MB		 503/* Suspend a SSB bus.
504 * Call this from the parent bus suspend routine. */
505extern int ssb_bus_suspend(struct ssb_bus *bus);
506/* Resume a SSB bus.
507 * Call this from the parent bus resume routine. */
508extern int ssb_bus_resume(struct ssb_bus *bus);
509
61e115a5
MB		 510extern u32 ssb_clockspeed(struct ssb_bus *bus);
511
512/* Is the device enabled in hardware? */
513int ssb_device_is_enabled(struct ssb_device *dev);
514/* Enable a device and pass device-specific SSB_TMSLOW flags.
515 * If no device-specific flags are available, use 0. */
516void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags);
517/* Disable a device in hardware and pass SSB_TMSLOW flags (if any). */
518void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags);
519
520
521/* Device MMIO register read/write functions. */
ffc7689d
MB		 522static inline u8 ssb_read8(struct ssb_device *dev, u16 offset)
523{
524 return dev->ops->read8(dev, offset);
525}
61e115a5
MB		 526static inline u16 ssb_read16(struct ssb_device *dev, u16 offset)
527{
528 return dev->ops->read16(dev, offset);
529}
530static inline u32 ssb_read32(struct ssb_device *dev, u16 offset)
531{
532 return dev->ops->read32(dev, offset);
533}
ffc7689d
MB		 534static inline void ssb_write8(struct ssb_device *dev, u16 offset, u8 value)
535{
536 dev->ops->write8(dev, offset, value);
537}
61e115a5
MB		 538static inline void ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
539{
540 dev->ops->write16(dev, offset, value);
541}
542static inline void ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
543{
544 dev->ops->write32(dev, offset, value);
545}
d625a29b
MB		 546#ifdef CONFIG_SSB_BLOCKIO
547static inline void ssb_block_read(struct ssb_device *dev, void *buffer,
548 size_t count, u16 offset, u8 reg_width)
549{
550 dev->ops->block_read(dev, buffer, count, offset, reg_width);
551}
552
553static inline void ssb_block_write(struct ssb_device *dev, const void *buffer,
554 size_t count, u16 offset, u8 reg_width)
555{
556 dev->ops->block_write(dev, buffer, count, offset, reg_width);
557}
558#endif /* CONFIG_SSB_BLOCKIO */
61e115a5
MB		 559
560
f225763a
MB		 561/* The SSB DMA API. Use this API for any DMA operation on the device.
562 * This API basically is a wrapper that calls the correct DMA API for
563 * the host device type the SSB device is attached to. */
564
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MB		 565/* Translation (routing) bits that need to be ORed to DMA
566 * addresses before they are given to a device. */
567extern u32 ssb_dma_translation(struct ssb_device *dev);
568#define SSB_DMA_TRANSLATION_MASK 0xC0000000
569#define SSB_DMA_TRANSLATION_SHIFT 30
570
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MB		 571static inline void __cold __ssb_dma_not_implemented(struct ssb_device *dev)
572{
573#ifdef CONFIG_SSB_DEBUG
574 printk(KERN_ERR "SSB: BUG! Calling DMA API for "
575 "unsupported bustype %d\n", dev->bus->bustype);
576#endif /* DEBUG */
577}
578
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MB		 579#ifdef CONFIG_SSB_PCIHOST
580/* PCI-host wrapper driver */
581extern int ssb_pcihost_register(struct pci_driver *driver);
582static inline void ssb_pcihost_unregister(struct pci_driver *driver)
583{
584 pci_unregister_driver(driver);
585}
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MB		 586
587static inline
588void ssb_pcihost_set_power_state(struct ssb_device *sdev, pci_power_t state)
589{
590 if (sdev->bus->bustype == SSB_BUSTYPE_PCI)
591 pci_set_power_state(sdev->bus->host_pci, state);
592}
532031d7
AM		 593#else
594static inline void ssb_pcihost_unregister(struct pci_driver *driver)
595{
596}
597
598static inline
599void ssb_pcihost_set_power_state(struct ssb_device *sdev, pci_power_t state)
600{
601}
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MB		 602#endif /* CONFIG_SSB_PCIHOST */
603
604
605/* If a driver is shutdown or suspended, call this to signal
606 * that the bus may be completely powered down. SSB will decide,
607 * if it's really time to power down the bus, based on if there
608 * are other devices that want to run. */
609extern int ssb_bus_may_powerdown(struct ssb_bus *bus);
610/* Before initializing and enabling a device, call this to power-up the bus.
611 * If you want to allow use of dynamic-power-control, pass the flag.
612 * Otherwise static always-on powercontrol will be used. */
613extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
614
8576f815 615extern void ssb_commit_settings(struct ssb_bus *bus);
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MB		 616
617/* Various helper functions */
618extern u32 ssb_admatch_base(u32 adm);
619extern u32 ssb_admatch_size(u32 adm);
620
aab547ce
MB		 621/* PCI device mapping and fixup routines.
622 * Called from the architecture pcibios init code.
623 * These are only available on SSB_EMBEDDED configurations. */
624#ifdef CONFIG_SSB_EMBEDDED
625int ssb_pcibios_plat_dev_init(struct pci_dev *dev);
626int ssb_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
627#endif /* CONFIG_SSB_EMBEDDED */
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MB		 628
629#endif /* LINUX_SSB_H_ */
Linux 6.x block layer and io_uring tree(s)