[linux-block.git] / include / linux / soundwire / sdw_intel.h

/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/* Copyright(c) 2015-17 Intel Corporation. */

#ifndef __SDW_INTEL_H
#define __SDW_INTEL_H

#include <linux/irqreturn.h>
#include <linux/soundwire/sdw.h>

#define SDW_SHIM_BASE			0x2C000
#define SDW_ALH_BASE			0x2C800
#define SDW_SHIM_BASE_ACE		0x38000
#define SDW_ALH_BASE_ACE		0x24000
#define SDW_LINK_BASE			0x30000
#define SDW_LINK_SIZE			0x10000

/* Intel SHIM Registers Definition */
/* LCAP */
#define SDW_SHIM_LCAP			0x0
#define SDW_SHIM_LCAP_LCOUNT_MASK	GENMASK(2, 0)

/* LCTL */
#define SDW_SHIM_LCTL			0x4

#define SDW_SHIM_LCTL_SPA		BIT(0)
#define SDW_SHIM_LCTL_SPA_MASK		GENMASK(3, 0)
#define SDW_SHIM_LCTL_CPA		BIT(8)
#define SDW_SHIM_LCTL_CPA_MASK		GENMASK(11, 8)

/* SYNC */
#define SDW_SHIM_SYNC			0xC

#define SDW_SHIM_SYNC_SYNCPRD_VAL_24	(24000 / SDW_CADENCE_GSYNC_KHZ - 1)
#define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4	(38400 / SDW_CADENCE_GSYNC_KHZ - 1)
#define SDW_SHIM_SYNC_SYNCPRD		GENMASK(14, 0)
#define SDW_SHIM_SYNC_SYNCCPU		BIT(15)
#define SDW_SHIM_SYNC_CMDSYNC_MASK	GENMASK(19, 16)
#define SDW_SHIM_SYNC_CMDSYNC		BIT(16)
#define SDW_SHIM_SYNC_SYNCGO		BIT(24)

/* Control stream capabililities and channel mask */
#define SDW_SHIM_CTLSCAP(x)		(0x010 + 0x60 * (x))
#define SDW_SHIM_CTLS0CM(x)		(0x012 + 0x60 * (x))
#define SDW_SHIM_CTLS1CM(x)		(0x014 + 0x60 * (x))
#define SDW_SHIM_CTLS2CM(x)		(0x016 + 0x60 * (x))
#define SDW_SHIM_CTLS3CM(x)		(0x018 + 0x60 * (x))

/* PCM Stream capabilities */
#define SDW_SHIM_PCMSCAP(x)		(0x020 + 0x60 * (x))

#define SDW_SHIM_PCMSCAP_ISS		GENMASK(3, 0)
#define SDW_SHIM_PCMSCAP_OSS		GENMASK(7, 4)
#define SDW_SHIM_PCMSCAP_BSS		GENMASK(12, 8)

/* PCM Stream Channel Map */
#define SDW_SHIM_PCMSYCHM(x, y)		(0x022 + (0x60 * (x)) + (0x2 * (y)))

/* PCM Stream Channel Count */
#define SDW_SHIM_PCMSYCHC(x, y)		(0x042 + (0x60 * (x)) + (0x2 * (y)))

#define SDW_SHIM_PCMSYCM_LCHN		GENMASK(3, 0)
#define SDW_SHIM_PCMSYCM_HCHN		GENMASK(7, 4)
#define SDW_SHIM_PCMSYCM_STREAM		GENMASK(13, 8)
#define SDW_SHIM_PCMSYCM_DIR		BIT(15)

/* IO control */
#define SDW_SHIM_IOCTL(x)		(0x06C + 0x60 * (x))

#define SDW_SHIM_IOCTL_MIF		BIT(0)
#define SDW_SHIM_IOCTL_CO		BIT(1)
#define SDW_SHIM_IOCTL_COE		BIT(2)
#define SDW_SHIM_IOCTL_DO		BIT(3)
#define SDW_SHIM_IOCTL_DOE		BIT(4)
#define SDW_SHIM_IOCTL_BKE		BIT(5)
#define SDW_SHIM_IOCTL_WPDD		BIT(6)
#define SDW_SHIM_IOCTL_CIBD		BIT(8)
#define SDW_SHIM_IOCTL_DIBD		BIT(9)

/* Wake Enable*/
#define SDW_SHIM_WAKEEN			0x190

#define SDW_SHIM_WAKEEN_ENABLE		BIT(0)

/* Wake Status */
#define SDW_SHIM_WAKESTS		0x192

#define SDW_SHIM_WAKESTS_STATUS		BIT(0)

/* AC Timing control */
#define SDW_SHIM_CTMCTL(x)		(0x06E + 0x60 * (x))

#define SDW_SHIM_CTMCTL_DACTQE		BIT(0)
#define SDW_SHIM_CTMCTL_DODS		BIT(1)
#define SDW_SHIM_CTMCTL_DOAIS		GENMASK(4, 3)

/* Intel ALH Register definitions */
#define SDW_ALH_STRMZCFG(x)		(0x000 + (0x4 * (x)))
#define SDW_ALH_NUM_STREAMS		64

#define SDW_ALH_STRMZCFG_DMAT_VAL	0x3
#define SDW_ALH_STRMZCFG_DMAT		GENMASK(7, 0)
#define SDW_ALH_STRMZCFG_CHN		GENMASK(19, 16)

/**
 * struct sdw_intel_stream_params_data: configuration passed during
 * the @params_stream callback, e.g. for interaction with DSP
 * firmware.
 */
struct sdw_intel_stream_params_data {
	int stream;
	struct snd_soc_dai *dai;
	struct snd_pcm_hw_params *hw_params;
	int link_id;
	int alh_stream_id;
};

/**
 * struct sdw_intel_stream_free_data: configuration passed during
 * the @free_stream callback, e.g. for interaction with DSP
 * firmware.
 */
struct sdw_intel_stream_free_data {
	int stream;
	struct snd_soc_dai *dai;
	int link_id;
};

/**
 * struct sdw_intel_ops: Intel audio driver callback ops
 *
 */
struct sdw_intel_ops {
	int (*params_stream)(struct device *dev,
			     struct sdw_intel_stream_params_data *params_data);
	int (*free_stream)(struct device *dev,
			   struct sdw_intel_stream_free_data *free_data);
	int (*trigger)(struct snd_soc_dai *dai, int cmd, int stream);
};

/**
 * struct sdw_intel_acpi_info - Soundwire Intel information found in ACPI tables
 * @handle: ACPI controller handle
 * @count: link count found with "sdw-master-count" property
 * @link_mask: bit-wise mask listing links enabled by BIOS menu
 *
 * this structure could be expanded to e.g. provide all the _ADR
 * information in case the link_mask is not sufficient to identify
 * platform capabilities.
 */
struct sdw_intel_acpi_info {
	acpi_handle handle;
	int count;
	u32 link_mask;
};

struct sdw_intel_link_dev;

/* Intel clock-stop/pm_runtime quirk definitions */

/*
 * Force the clock to remain on during pm_runtime suspend. This might
 * be needed if Slave devices do not have an alternate clock source or
 * if the latency requirements are very strict.
 */
#define SDW_INTEL_CLK_STOP_NOT_ALLOWED		BIT(0)

/*
 * Stop the bus during pm_runtime suspend. If set, a complete bus
 * reset and re-enumeration will be performed when the bus
 * restarts. This mode shall not be used if Slave devices can generate
 * in-band wakes.
 */
#define SDW_INTEL_CLK_STOP_TEARDOWN		BIT(1)

/*
 * Stop the bus during pm_suspend if Slaves are not wake capable
 * (e.g. speaker amplifiers). The clock-stop mode is typically
 * slightly higher power than when the IP is completely powered-off.
 */
#define SDW_INTEL_CLK_STOP_WAKE_CAPABLE_ONLY	BIT(2)

/*
 * Require a bus reset (and complete re-enumeration) when exiting
 * clock stop modes. This may be needed if the controller power was
 * turned off and all context lost. This quirk shall not be used if a
 * Slave device needs to remain enumerated and keep its context,
 * e.g. to provide the reasons for the wake, report acoustic events or
 * pass a history buffer.
 */
#define SDW_INTEL_CLK_STOP_BUS_RESET		BIT(3)

struct sdw_intel_slave_id {
	int link_id;
	struct sdw_slave_id id;
};

/**
 * struct sdw_intel_ctx - context allocated by the controller
 * driver probe
 * @count: link count
 * @mmio_base: mmio base of SoundWire registers, only used to check
 * hardware capabilities after all power dependencies are settled.
 * @link_mask: bit-wise mask listing SoundWire links reported by the
 * Controller
 * @num_slaves: total number of devices exposed across all enabled links
 * @handle: ACPI parent handle
 * @ldev: information for each link (controller-specific and kept
 * opaque here)
 * @ids: array of slave_id, representing Slaves exposed across all enabled
 * links
 * @link_list: list to handle interrupts across all links
 * @shim_lock: mutex to handle concurrent rmw access to shared SHIM registers.
 * @shim_mask: flags to track initialization of SHIM shared registers
 * @shim_base: sdw shim base.
 * @alh_base: sdw alh base.
 */
struct sdw_intel_ctx {
	int count;
	void __iomem *mmio_base;
	u32 link_mask;
	int num_slaves;
	acpi_handle handle;
	struct sdw_intel_link_dev **ldev;
	struct sdw_intel_slave_id *ids;
	struct list_head link_list;
	struct mutex shim_lock; /* lock for access to shared SHIM registers */
	u32 shim_mask;
	u32 shim_base;
	u32 alh_base;
};

/**
 * struct sdw_intel_res - Soundwire Intel global resource structure,
 * typically populated by the DSP driver
 *
 * @count: link count
 * @mmio_base: mmio base of SoundWire registers
 * @irq: interrupt number
 * @handle: ACPI parent handle
 * @parent: parent device
 * @ops: callback ops
 * @dev: device implementing hwparams and free callbacks
 * @link_mask: bit-wise mask listing links selected by the DSP driver
 * This mask may be a subset of the one reported by the controller since
 * machine-specific quirks are handled in the DSP driver.
 * @clock_stop_quirks: mask array of possible behaviors requested by the
 * DSP driver. The quirks are common for all links for now.
 * @shim_base: sdw shim base.
 * @alh_base: sdw alh base.
 */
struct sdw_intel_res {
	int count;
	void __iomem *mmio_base;
	int irq;
	acpi_handle handle;
	struct device *parent;
	const struct sdw_intel_ops *ops;
	struct device *dev;
	u32 link_mask;
	u32 clock_stop_quirks;
	u32 shim_base;
	u32 alh_base;
};

/*
 * On Intel platforms, the SoundWire IP has dependencies on power
 * rails shared with the DSP, and the initialization steps are split
 * in three. First an ACPI scan to check what the firmware describes
 * in DSDT tables, then an allocation step (with no hardware
 * configuration but with all the relevant devices created) and last
 * the actual hardware configuration. The final stage is a global
 * interrupt enable which is controlled by the DSP driver. Splitting
 * these phases helps simplify the boot flow and make early decisions
 * on e.g. which machine driver to select (I2S mode, HDaudio or
 * SoundWire).
 */
int sdw_intel_acpi_scan(acpi_handle *parent_handle,
			struct sdw_intel_acpi_info *info);

void sdw_intel_process_wakeen_event(struct sdw_intel_ctx *ctx);

struct sdw_intel_ctx *
sdw_intel_probe(struct sdw_intel_res *res);

int sdw_intel_startup(struct sdw_intel_ctx *ctx);

void sdw_intel_exit(struct sdw_intel_ctx *ctx);

void sdw_intel_enable_irq(void __iomem *mmio_base, bool enable);

irqreturn_t sdw_intel_thread(int irq, void *dev_id);

#define SDW_INTEL_QUIRK_MASK_BUS_DISABLE      BIT(1)

#endif
Commit	Line	Data
392f1045 VK	1	/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
392f1045 VK	2	/* Copyright(c) 2015-17 Intel Corporation. */
71bb8a1b VK	3
	4	#ifndef __SDW_INTEL_H
	5	#define __SDW_INTEL_H
	6
6cd1d670	7	#include <linux/irqreturn.h>
92f622bc	8	#include <linux/soundwire/sdw.h>
6cd1d670	9
f0163958 BL	10	#define SDW_SHIM_BASE 0x2C000
f0163958 BL	11	#define SDW_ALH_BASE 0x2C800
064520e8 BL	12	#define SDW_SHIM_BASE_ACE 0x38000
064520e8 BL	13	#define SDW_ALH_BASE_ACE 0x24000
f0163958 BL	14	#define SDW_LINK_BASE 0x30000
	15	#define SDW_LINK_SIZE 0x10000
	16
	17	/* Intel SHIM Registers Definition */
7f817068	18	/* LCAP */
f0163958	19	#define SDW_SHIM_LCAP 0x0
7f817068 PLB	20	#define SDW_SHIM_LCAP_LCOUNT_MASK GENMASK(2, 0)
7f817068 PLB	21
feaa24aa	22	/* LCTL */
f0163958	23	#define SDW_SHIM_LCTL 0x4
feaa24aa PLB	24
	25	#define SDW_SHIM_LCTL_SPA BIT(0)
	26	#define SDW_SHIM_LCTL_SPA_MASK GENMASK(3, 0)
	27	#define SDW_SHIM_LCTL_CPA BIT(8)
	28	#define SDW_SHIM_LCTL_CPA_MASK GENMASK(11, 8)
	29
ca33a58d	30	/* SYNC */
f0163958 BL	31	#define SDW_SHIM_SYNC 0xC
f0163958 BL	32
ca33a58d PLB	33	#define SDW_SHIM_SYNC_SYNCPRD_VAL_24 (24000 / SDW_CADENCE_GSYNC_KHZ - 1)
	34	#define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4 (38400 / SDW_CADENCE_GSYNC_KHZ - 1)
	35	#define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0)
	36	#define SDW_SHIM_SYNC_SYNCCPU BIT(15)
	37	#define SDW_SHIM_SYNC_CMDSYNC_MASK GENMASK(19, 16)
	38	#define SDW_SHIM_SYNC_CMDSYNC BIT(16)
	39	#define SDW_SHIM_SYNC_SYNCGO BIT(24)
	40
bd45a65d	41	/* Control stream capabililities and channel mask */
f0163958 BL	42	#define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * (x))
	43	#define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * (x))
	44	#define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * (x))
	45	#define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * (x))
	46	#define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * (x))
bd45a65d	47
40f7a3dd	48	/* PCM Stream capabilities */
f0163958 BL	49	#define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * (x))
f0163958 BL	50
40f7a3dd PLB	51	#define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0)
	52	#define SDW_SHIM_PCMSCAP_OSS GENMASK(7, 4)
	53	#define SDW_SHIM_PCMSCAP_BSS GENMASK(12, 8)
	54
5c0d2562	55	/* PCM Stream Channel Map */
f0163958	56	#define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * (x)) + (0x2 * (y)))
f0163958	57
5c0d2562 PLB	58	/* PCM Stream Channel Count */
5c0d2562 PLB	59	#define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * (x)) + (0x2 * (y)))
f0163958	60
f0163958 BL	61	#define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0)
	62	#define SDW_SHIM_PCMSYCM_HCHN GENMASK(7, 4)
	63	#define SDW_SHIM_PCMSYCM_STREAM GENMASK(13, 8)
	64	#define SDW_SHIM_PCMSYCM_DIR BIT(15)
	65
3ea29d33	66	/* IO control */
5c0d2562	67	#define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * (x))
5c0d2562	68
f0163958 BL	69	#define SDW_SHIM_IOCTL_MIF BIT(0)
	70	#define SDW_SHIM_IOCTL_CO BIT(1)
	71	#define SDW_SHIM_IOCTL_COE BIT(2)
	72	#define SDW_SHIM_IOCTL_DO BIT(3)
	73	#define SDW_SHIM_IOCTL_DOE BIT(4)
	74	#define SDW_SHIM_IOCTL_BKE BIT(5)
	75	#define SDW_SHIM_IOCTL_WPDD BIT(6)
	76	#define SDW_SHIM_IOCTL_CIBD BIT(8)
	77	#define SDW_SHIM_IOCTL_DIBD BIT(9)
	78
279e46bc	79	/* Wake Enable*/
3ea29d33	80	#define SDW_SHIM_WAKEEN 0x190
279e46bc PLB	81
	82	#define SDW_SHIM_WAKEEN_ENABLE BIT(0)
	83
	84	/* Wake Status */
3ea29d33 PLB	85	#define SDW_SHIM_WAKESTS 0x192
3ea29d33 PLB	86
279e46bc PLB	87	#define SDW_SHIM_WAKESTS_STATUS BIT(0)
279e46bc PLB	88
bc7b9595 PLB	89	/* AC Timing control */
	90	#define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x))
	91
f0163958 BL	92	#define SDW_SHIM_CTMCTL_DACTQE BIT(0)
	93	#define SDW_SHIM_CTMCTL_DODS BIT(1)
	94	#define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3)
	95
f0163958 BL	96	/* Intel ALH Register definitions */
	97	#define SDW_ALH_STRMZCFG(x) (0x000 + (0x4 * (x)))
	98	#define SDW_ALH_NUM_STREAMS 64
	99
	100	#define SDW_ALH_STRMZCFG_DMAT_VAL 0x3
	101	#define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0)
	102	#define SDW_ALH_STRMZCFG_CHN GENMASK(19, 16)
	103
4b206d34 RW	104	/**
	105	* struct sdw_intel_stream_params_data: configuration passed during
	106	* the @params_stream callback, e.g. for interaction with DSP
	107	* firmware.
	108	*/
	109	struct sdw_intel_stream_params_data {
b86947b5	110	int stream;
4b206d34 RW	111	struct snd_soc_dai *dai;
	112	struct snd_pcm_hw_params *hw_params;
	113	int link_id;
	114	int alh_stream_id;
	115	};
	116
	117	/**
	118	* struct sdw_intel_stream_free_data: configuration passed during
	119	* the @free_stream callback, e.g. for interaction with DSP
	120	* firmware.
	121	*/
	122	struct sdw_intel_stream_free_data {
b86947b5	123	int stream;
4b206d34 RW	124	struct snd_soc_dai *dai;
	125	int link_id;
	126	};
	127
c46302ec VK	128	/**
	129	* struct sdw_intel_ops: Intel audio driver callback ops
	130	*
c46302ec VK	131	*/
c46302ec VK	132	struct sdw_intel_ops {
4b206d34 RW	133	int (params_stream)(struct device dev,
	134	struct sdw_intel_stream_params_data *params_data);
	135	int (free_stream)(struct device dev,
	136	struct sdw_intel_stream_free_data *free_data);
6d1c1a73	137	int (trigger)(struct snd_soc_dai dai, int cmd, int stream);
c46302ec VK	138	};
c46302ec VK	139
71bb8a1b	140	/**
f98f690f PLB	141	* struct sdw_intel_acpi_info - Soundwire Intel information found in ACPI tables
	142	* @handle: ACPI controller handle
	143	* @count: link count found with "sdw-master-count" property
	144	* @link_mask: bit-wise mask listing links enabled by BIOS menu
	145	*
	146	* this structure could be expanded to e.g. provide all the _ADR
	147	* information in case the link_mask is not sufficient to identify
	148	* platform capabilities.
	149	*/
	150	struct sdw_intel_acpi_info {
	151	acpi_handle handle;
	152	int count;
	153	u32 link_mask;
	154	};
	155
29a269c6	156	struct sdw_intel_link_dev;
f98f690f	157
09f6a72d PLB	158	/* Intel clock-stop/pm_runtime quirk definitions */
	159
	160	/*
	161	* Force the clock to remain on during pm_runtime suspend. This might
	162	* be needed if Slave devices do not have an alternate clock source or
	163	* if the latency requirements are very strict.
	164	*/
	165	#define SDW_INTEL_CLK_STOP_NOT_ALLOWED BIT(0)
	166
	167	/*
	168	* Stop the bus during pm_runtime suspend. If set, a complete bus
	169	* reset and re-enumeration will be performed when the bus
	170	* restarts. This mode shall not be used if Slave devices can generate
	171	* in-band wakes.
	172	*/
	173	#define SDW_INTEL_CLK_STOP_TEARDOWN BIT(1)
	174
	175	/*
	176	* Stop the bus during pm_suspend if Slaves are not wake capable
	177	* (e.g. speaker amplifiers). The clock-stop mode is typically
	178	* slightly higher power than when the IP is completely powered-off.
	179	*/
	180	#define SDW_INTEL_CLK_STOP_WAKE_CAPABLE_ONLY BIT(2)
	181
	182	/*
	183	* Require a bus reset (and complete re-enumeration) when exiting
	184	* clock stop modes. This may be needed if the controller power was
	185	* turned off and all context lost. This quirk shall not be used if a
	186	* Slave device needs to remain enumerated and keep its context,
	187	* e.g. to provide the reasons for the wake, report acoustic events or
	188	* pass a history buffer.
	189	*/
	190	#define SDW_INTEL_CLK_STOP_BUS_RESET BIT(3)
	191
92f622bc BL	192	struct sdw_intel_slave_id {
	193	int link_id;
	194	struct sdw_slave_id id;
	195	};
	196
f98f690f PLB	197	/**
	198	* struct sdw_intel_ctx - context allocated by the controller
	199	* driver probe
	200	* @count: link count
	201	* @mmio_base: mmio base of SoundWire registers, only used to check
	202	* hardware capabilities after all power dependencies are settled.
	203	* @link_mask: bit-wise mask listing SoundWire links reported by the
	204	* Controller
92f622bc	205	* @num_slaves: total number of devices exposed across all enabled links
f98f690f	206	* @handle: ACPI parent handle
29a269c6	207	* @ldev: information for each link (controller-specific and kept
f98f690f	208	* opaque here)
92f622bc BL	209	* @ids: array of slave_id, representing Slaves exposed across all enabled
92f622bc BL	210	* links
eae0b60d	211	* @link_list: list to handle interrupts across all links
4da0680f	212	* @shim_lock: mutex to handle concurrent rmw access to shared SHIM registers.
4a17c441	213	* @shim_mask: flags to track initialization of SHIM shared registers
60e9feb7 BL	214	* @shim_base: sdw shim base.
60e9feb7 BL	215	* @alh_base: sdw alh base.
f98f690f PLB	216	*/
	217	struct sdw_intel_ctx {
	218	int count;
	219	void __iomem *mmio_base;
	220	u32 link_mask;
92f622bc	221	int num_slaves;
f98f690f	222	acpi_handle handle;
29a269c6	223	struct sdw_intel_link_dev **ldev;
92f622bc	224	struct sdw_intel_slave_id *ids;
eae0b60d	225	struct list_head link_list;
4da0680f	226	struct mutex shim_lock; /* lock for access to shared SHIM registers */
4a17c441	227	u32 shim_mask;
60e9feb7 BL	228	u32 shim_base;
60e9feb7 BL	229	u32 alh_base;
f98f690f PLB	230	};
	231
	232	/**
	233	* struct sdw_intel_res - Soundwire Intel global resource structure,
	234	* typically populated by the DSP driver
	235	*
	236	* @count: link count
71bb8a1b VK	237	* @mmio_base: mmio base of SoundWire registers
	238	* @irq: interrupt number
	239	* @handle: ACPI parent handle
	240	* @parent: parent device
c46302ec	241	* @ops: callback ops
f98f690f PLB	242	* @dev: device implementing hwparams and free callbacks
	243	* @link_mask: bit-wise mask listing links selected by the DSP driver
	244	* This mask may be a subset of the one reported by the controller since
	245	* machine-specific quirks are handled in the DSP driver.
09f6a72d PLB	246	* @clock_stop_quirks: mask array of possible behaviors requested by the
09f6a72d PLB	247	* DSP driver. The quirks are common for all links for now.
60e9feb7 BL	248	* @shim_base: sdw shim base.
60e9feb7 BL	249	* @alh_base: sdw alh base.
71bb8a1b VK	250	*/
71bb8a1b VK	251	struct sdw_intel_res {
f98f690f	252	int count;
71bb8a1b VK	253	void __iomem *mmio_base;
	254	int irq;
	255	acpi_handle handle;
	256	struct device *parent;
c46302ec	257	const struct sdw_intel_ops *ops;
f98f690f PLB	258	struct device *dev;
f98f690f PLB	259	u32 link_mask;
09f6a72d	260	u32 clock_stop_quirks;
60e9feb7 BL	261	u32 shim_base;
60e9feb7 BL	262	u32 alh_base;
71bb8a1b VK	263	};
71bb8a1b VK	264
f98f690f PLB	265	/*
	266	* On Intel platforms, the SoundWire IP has dependencies on power
	267	* rails shared with the DSP, and the initialization steps are split
	268	* in three. First an ACPI scan to check what the firmware describes
	269	* in DSDT tables, then an allocation step (with no hardware
	270	* configuration but with all the relevant devices created) and last
	271	* the actual hardware configuration. The final stage is a global
	272	* interrupt enable which is controlled by the DSP driver. Splitting
	273	* these phases helps simplify the boot flow and make early decisions
	274	* on e.g. which machine driver to select (I2S mode, HDaudio or
	275	* SoundWire).
	276	*/
	277	int sdw_intel_acpi_scan(acpi_handle *parent_handle,
	278	struct sdw_intel_acpi_info *info);
	279
905b5a81 RW	280	void sdw_intel_process_wakeen_event(struct sdw_intel_ctx *ctx);
905b5a81 RW	281
f98f690f PLB	282	struct sdw_intel_ctx *
	283	sdw_intel_probe(struct sdw_intel_res *res);
	284
	285	int sdw_intel_startup(struct sdw_intel_ctx *ctx);
	286
	287	void sdw_intel_exit(struct sdw_intel_ctx *ctx);
	288
	289	void sdw_intel_enable_irq(void __iomem *mmio_base, bool enable);
d62a7d41	290
6cd1d670 BL	291	irqreturn_t sdw_intel_thread(int irq, void *dev_id);
6cd1d670 BL	292
08c2a4bc PLB	293	#define SDW_INTEL_QUIRK_MASK_BUS_DISABLE BIT(1)
08c2a4bc PLB	294
71bb8a1b	295	#endif