[linux-block.git] / include / linux / sh_dma.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Header for the new SH dmaengine driver
 *
 * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
 */
#ifndef SH_DMA_H
#define SH_DMA_H

#include <linux/dmaengine.h>
#include <linux/list.h>
#include <linux/shdma-base.h>
#include <linux/types.h>

struct device;

/* Used by slave DMA clients to request DMA to/from a specific peripheral */
struct sh_dmae_slave {
	struct shdma_slave		shdma_slave;	/* Set by the platform */
};

/*
 * Supplied by platforms to specify, how a DMA channel has to be configured for
 * a certain peripheral
 */
struct sh_dmae_slave_config {
	int		slave_id;
	dma_addr_t	addr;
	u32		chcr;
	char		mid_rid;
};

/**
 * struct sh_dmae_channel - DMAC channel platform data
 * @offset:		register offset within the main IOMEM resource
 * @dmars:		channel DMARS register offset
 * @chclr_offset:	channel CHCLR register offset
 * @dmars_bit:		channel DMARS field offset within the register
 * @chclr_bit:		bit position, to be set to reset the channel
 */
struct sh_dmae_channel {
	unsigned int	offset;
	unsigned int	dmars;
	unsigned int	chclr_offset;
	unsigned char	dmars_bit;
	unsigned char	chclr_bit;
};

/**
 * struct sh_dmae_pdata - DMAC platform data
 * @slave:		array of slaves
 * @slave_num:		number of slaves in the above array
 * @channel:		array of DMA channels
 * @channel_num:	number of channels in the above array
 * @ts_low_shift:	shift of the low part of the TS field
 * @ts_low_mask:	low TS field mask
 * @ts_high_shift:	additional shift of the high part of the TS field
 * @ts_high_mask:	high TS field mask
 * @ts_shift:		array of Transfer Size shifts, indexed by TS value
 * @ts_shift_num:	number of shifts in the above array
 * @dmaor_init:		DMAOR initialisation value
 * @chcr_offset:	CHCR address offset
 * @chcr_ie_bit:	CHCR Interrupt Enable bit
 * @dmaor_is_32bit:	DMAOR is a 32-bit register
 * @needs_tend_set:	the TEND register has to be set
 * @no_dmars:		DMAC has no DMARS registers
 * @chclr_present:	DMAC has one or several CHCLR registers
 * @chclr_bitwise:	channel CHCLR registers are bitwise
 * @slave_only:		DMAC cannot be used for MEMCPY
 */
struct sh_dmae_pdata {
	const struct sh_dmae_slave_config *slave;
	int slave_num;
	const struct sh_dmae_channel *channel;
	int channel_num;
	unsigned int ts_low_shift;
	unsigned int ts_low_mask;
	unsigned int ts_high_shift;
	unsigned int ts_high_mask;
	const unsigned int *ts_shift;
	int ts_shift_num;
	u16 dmaor_init;
	unsigned int chcr_offset;
	u32 chcr_ie_bit;

	unsigned int dmaor_is_32bit:1;
	unsigned int needs_tend_set:1;
	unsigned int no_dmars:1;
	unsigned int chclr_present:1;
	unsigned int chclr_bitwise:1;
	unsigned int slave_only:1;
};

/* DMAOR definitions */
#define DMAOR_AE	0x00000004	/* Address Error Flag */
#define DMAOR_NMIF	0x00000002
#define DMAOR_DME	0x00000001	/* DMA Master Enable */

/* Definitions for the SuperH DMAC */
#define DM_INC	0x00004000	/* Destination addresses are incremented */
#define DM_DEC	0x00008000	/* Destination addresses are decremented */
#define DM_FIX	0x0000c000	/* Destination address is fixed */
#define SM_INC	0x00001000	/* Source addresses are incremented */
#define SM_DEC	0x00002000	/* Source addresses are decremented */
#define SM_FIX	0x00003000	/* Source address is fixed */
#define RS_AUTO	0x00000400	/* Auto Request */
#define RS_ERS	0x00000800	/* DMA extended resource selector */
#define CHCR_DE	0x00000001	/* DMA Enable */
#define CHCR_TE	0x00000002	/* Transfer End Flag */
#define CHCR_IE	0x00000004	/* Interrupt Enable */

#endif
Commit	Line	Data
d2912cb1	1	/* SPDX-License-Identifier: GPL-2.0-only */
b2623a61 MD	2	/*
	3	* Header for the new SH dmaengine driver
	4	*
	5	* Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
b2623a61 MD	6	*/
	7	#ifndef SH_DMA_H
	8	#define SH_DMA_H
	9
b2623a61	10	#include <linux/dmaengine.h>
5902c9a7 GL	11	#include <linux/list.h>
5902c9a7 GL	12	#include <linux/shdma-base.h>
ce3a1ab7 GL	13	#include <linux/types.h>
	14
	15	struct device;
b2623a61 MD	16
	17	/* Used by slave DMA clients to request DMA to/from a specific peripheral */
	18	struct sh_dmae_slave {
ce3a1ab7	19	struct shdma_slave shdma_slave; /* Set by the platform */
b2623a61	20	};
5bac942d	21
ce3a1ab7 GL	22	/*
	23	* Supplied by platforms to specify, how a DMA channel has to be configured for
	24	* a certain peripheral
	25	*/
b2623a61	26	struct sh_dmae_slave_config {
c2cdb7e4 GL	27	int slave_id;
	28	dma_addr_t addr;
	29	u32 chcr;
	30	char mid_rid;
b2623a61 MD	31	};
b2623a61 MD	32
ca8b3878 GL	33	/**
	34	* struct sh_dmae_channel - DMAC channel platform data
	35	* @offset: register offset within the main IOMEM resource
	36	* @dmars: channel DMARS register offset
	37	* @chclr_offset: channel CHCLR register offset
	38	* @dmars_bit: channel DMARS field offset within the register
	39	* @chclr_bit: bit position, to be set to reset the channel
	40	*/
b2623a61 MD	41	struct sh_dmae_channel {
	42	unsigned int offset;
	43	unsigned int dmars;
c11b46c3	44	unsigned int chclr_offset;
ca8b3878 GL	45	unsigned char dmars_bit;
ca8b3878 GL	46	unsigned char chclr_bit;
b2623a61 MD	47	};
b2623a61 MD	48
ca8b3878 GL	49	/**
	50	* struct sh_dmae_pdata - DMAC platform data
	51	* @slave: array of slaves
	52	* @slave_num: number of slaves in the above array
	53	* @channel: array of DMA channels
	54	* @channel_num: number of channels in the above array
	55	* @ts_low_shift: shift of the low part of the TS field
	56	* @ts_low_mask: low TS field mask
	57	* @ts_high_shift: additional shift of the high part of the TS field
	58	* @ts_high_mask: high TS field mask
	59	* @ts_shift: array of Transfer Size shifts, indexed by TS value
	60	* @ts_shift_num: number of shifts in the above array
	61	* @dmaor_init: DMAOR initialisation value
	62	* @chcr_offset: CHCR address offset
	63	* @chcr_ie_bit: CHCR Interrupt Enable bit
	64	* @dmaor_is_32bit: DMAOR is a 32-bit register
	65	* @needs_tend_set: the TEND register has to be set
	66	* @no_dmars: DMAC has no DMARS registers
	67	* @chclr_present: DMAC has one or several CHCLR registers
	68	* @chclr_bitwise: channel CHCLR registers are bitwise
	69	* @slave_only: DMAC cannot be used for MEMCPY
	70	*/
b2623a61	71	struct sh_dmae_pdata {
5bac942d	72	const struct sh_dmae_slave_config *slave;
b2623a61	73	int slave_num;
5bac942d	74	const struct sh_dmae_channel *channel;
b2623a61 MD	75	int channel_num;
	76	unsigned int ts_low_shift;
	77	unsigned int ts_low_mask;
	78	unsigned int ts_high_shift;
	79	unsigned int ts_high_mask;
5bac942d	80	const unsigned int *ts_shift;
b2623a61 MD	81	int ts_shift_num;
b2623a61 MD	82	u16 dmaor_init;
5899a723	83	unsigned int chcr_offset;
67c6269e	84	u32 chcr_ie_bit;
e76c3af8 KM	85
e76c3af8 KM	86	unsigned int dmaor_is_32bit:1;
260bf2c5 KM	87	unsigned int needs_tend_set:1;
260bf2c5 KM	88	unsigned int no_dmars:1;
c11b46c3	89	unsigned int chclr_present:1;
ca8b3878	90	unsigned int chclr_bitwise:1;
e9c8d7a0	91	unsigned int slave_only:1;
b2623a61 MD	92	};
b2623a61 MD	93
b2623a61	94	/* DMAOR definitions */
6b32fafe	95	#define DMAOR_AE 0x00000004 /* Address Error Flag */
b2623a61	96	#define DMAOR_NMIF 0x00000002
6b32fafe	97	#define DMAOR_DME 0x00000001 /* DMA Master Enable */
b2623a61 MD	98
b2623a61 MD	99	/* Definitions for the SuperH DMAC */
6b32fafe GU	100	#define DM_INC 0x00004000 /* Destination addresses are incremented */
	101	#define DM_DEC 0x00008000 /* Destination addresses are decremented */
	102	#define DM_FIX 0x0000c000 /* Destination address is fixed */
	103	#define SM_INC 0x00001000 /* Source addresses are incremented */
	104	#define SM_DEC 0x00002000 /* Source addresses are decremented */
	105	#define SM_FIX 0x00003000 /* Source address is fixed */
	106	#define RS_AUTO 0x00000400 /* Auto Request */
	107	#define RS_ERS 0x00000800 /* DMA extended resource selector */
	108	#define CHCR_DE 0x00000001 /* DMA Enable */
	109	#define CHCR_TE 0x00000002 /* Transfer End Flag */
	110	#define CHCR_IE 0x00000004 /* Interrupt Enable */
b2623a61 MD	111
b2623a61 MD	112	#endif