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d28bdf05 MD |
1 | #ifndef __SH_CLOCK_H |
2 | #define __SH_CLOCK_H | |
3 | ||
4 | #include <linux/list.h> | |
5 | #include <linux/seq_file.h> | |
6 | #include <linux/cpufreq.h> | |
28085bc5 PM |
7 | #include <linux/types.h> |
8 | #include <linux/kref.h> | |
d28bdf05 MD |
9 | #include <linux/clk.h> |
10 | #include <linux/err.h> | |
11 | ||
12 | struct clk; | |
13 | ||
28085bc5 PM |
14 | struct clk_mapping { |
15 | phys_addr_t phys; | |
16 | void __iomem *base; | |
17 | unsigned long len; | |
18 | struct kref ref; | |
19 | }; | |
20 | ||
84c36ffd | 21 | struct sh_clk_ops { |
549015c3 | 22 | #ifdef CONFIG_SH_CLK_CPG_LEGACY |
d28bdf05 | 23 | void (*init)(struct clk *clk); |
549015c3 | 24 | #endif |
d28bdf05 MD |
25 | int (*enable)(struct clk *clk); |
26 | void (*disable)(struct clk *clk); | |
27 | unsigned long (*recalc)(struct clk *clk); | |
35a96c73 | 28 | int (*set_rate)(struct clk *clk, unsigned long rate); |
d28bdf05 MD |
29 | int (*set_parent)(struct clk *clk, struct clk *parent); |
30 | long (*round_rate)(struct clk *clk, unsigned long rate); | |
31 | }; | |
32 | ||
1111cc1e PM |
33 | #define SH_CLK_DIV_MSK(div) ((1 << (div)) - 1) |
34 | #define SH_CLK_DIV4_MSK SH_CLK_DIV_MSK(4) | |
35 | #define SH_CLK_DIV6_MSK SH_CLK_DIV_MSK(6) | |
36 | ||
d28bdf05 MD |
37 | struct clk { |
38 | struct list_head node; | |
d28bdf05 | 39 | struct clk *parent; |
b5272b50 GL |
40 | struct clk **parent_table; /* list of parents to */ |
41 | unsigned short parent_num; /* choose between */ | |
42 | unsigned char src_shift; /* source clock field in the */ | |
43 | unsigned char src_width; /* configuration register */ | |
84c36ffd | 44 | struct sh_clk_ops *ops; |
d28bdf05 MD |
45 | |
46 | struct list_head children; | |
47 | struct list_head sibling; /* node for children */ | |
48 | ||
49 | int usecount; | |
50 | ||
51 | unsigned long rate; | |
52 | unsigned long flags; | |
53 | ||
54 | void __iomem *enable_reg; | |
55 | unsigned int enable_bit; | |
eda2030a | 56 | void __iomem *mapped_reg; |
d28bdf05 | 57 | |
1111cc1e | 58 | unsigned int div_mask; |
d28bdf05 MD |
59 | unsigned long arch_flags; |
60 | void *priv; | |
28085bc5 | 61 | struct clk_mapping *mapping; |
d28bdf05 | 62 | struct cpufreq_frequency_table *freq_table; |
f586903d | 63 | unsigned int nr_freqs; |
d28bdf05 MD |
64 | }; |
65 | ||
4d6ddb08 PM |
66 | #define CLK_ENABLE_ON_INIT BIT(0) |
67 | ||
68 | #define CLK_ENABLE_REG_32BIT BIT(1) /* default access size */ | |
69 | #define CLK_ENABLE_REG_16BIT BIT(2) | |
70 | #define CLK_ENABLE_REG_8BIT BIT(3) | |
71 | ||
72 | #define CLK_ENABLE_REG_MASK (CLK_ENABLE_REG_32BIT | \ | |
73 | CLK_ENABLE_REG_16BIT | \ | |
74 | CLK_ENABLE_REG_8BIT) | |
d28bdf05 | 75 | |
a71ba096 | 76 | /* drivers/sh/clk.c */ |
d28bdf05 MD |
77 | unsigned long followparent_recalc(struct clk *); |
78 | void recalculate_root_clocks(void); | |
79 | void propagate_rate(struct clk *); | |
80 | int clk_reparent(struct clk *child, struct clk *parent); | |
81 | int clk_register(struct clk *); | |
82 | void clk_unregister(struct clk *); | |
8b5ee113 | 83 | void clk_enable_init_clocks(void); |
d28bdf05 | 84 | |
d28bdf05 MD |
85 | struct clk_div_mult_table { |
86 | unsigned int *divisors; | |
87 | unsigned int nr_divisors; | |
88 | unsigned int *multipliers; | |
89 | unsigned int nr_multipliers; | |
90 | }; | |
91 | ||
92 | struct cpufreq_frequency_table; | |
93 | void clk_rate_table_build(struct clk *clk, | |
94 | struct cpufreq_frequency_table *freq_table, | |
95 | int nr_freqs, | |
96 | struct clk_div_mult_table *src_table, | |
97 | unsigned long *bitmap); | |
98 | ||
99 | long clk_rate_table_round(struct clk *clk, | |
100 | struct cpufreq_frequency_table *freq_table, | |
101 | unsigned long rate); | |
102 | ||
103 | int clk_rate_table_find(struct clk *clk, | |
104 | struct cpufreq_frequency_table *freq_table, | |
105 | unsigned long rate); | |
106 | ||
8e122db6 PM |
107 | long clk_rate_div_range_round(struct clk *clk, unsigned int div_min, |
108 | unsigned int div_max, unsigned long rate); | |
109 | ||
dd2c0ca1 KM |
110 | long clk_rate_mult_range_round(struct clk *clk, unsigned int mult_min, |
111 | unsigned int mult_max, unsigned long rate); | |
112 | ||
6af26c6c GL |
113 | long clk_round_parent(struct clk *clk, unsigned long target, |
114 | unsigned long *best_freq, unsigned long *parent_freq, | |
115 | unsigned int div_min, unsigned int div_max); | |
116 | ||
4d6ddb08 | 117 | #define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _flags) \ |
d28bdf05 MD |
118 | { \ |
119 | .parent = _parent, \ | |
120 | .enable_reg = (void __iomem *)_enable_reg, \ | |
121 | .enable_bit = _enable_bit, \ | |
122 | .flags = _flags, \ | |
123 | } | |
124 | ||
4d6ddb08 PM |
125 | #define SH_CLK_MSTP32(_p, _r, _b, _f) \ |
126 | SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_32BIT) | |
127 | ||
128 | #define SH_CLK_MSTP16(_p, _r, _b, _f) \ | |
129 | SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_16BIT) | |
130 | ||
131 | #define SH_CLK_MSTP8(_p, _r, _b, _f) \ | |
132 | SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_8BIT) | |
133 | ||
134 | int sh_clk_mstp_register(struct clk *clks, int nr); | |
135 | ||
136 | /* | |
137 | * MSTP registration never really cared about access size, despite the | |
138 | * original enable/disable pairs assuming a 32-bit access. Clocks are | |
139 | * responsible for defining their access sizes either directly or via the | |
140 | * clock definition wrappers. | |
141 | */ | |
142 | static inline int __deprecated sh_clk_mstp32_register(struct clk *clks, int nr) | |
143 | { | |
144 | return sh_clk_mstp_register(clks, nr); | |
145 | } | |
d28bdf05 MD |
146 | |
147 | #define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \ | |
148 | { \ | |
149 | .parent = _parent, \ | |
150 | .enable_reg = (void __iomem *)_reg, \ | |
151 | .enable_bit = _shift, \ | |
152 | .arch_flags = _div_bitmap, \ | |
1111cc1e | 153 | .div_mask = SH_CLK_DIV4_MSK, \ |
d28bdf05 MD |
154 | .flags = _flags, \ |
155 | } | |
156 | ||
a60977a5 | 157 | struct clk_div_table { |
d28bdf05 MD |
158 | struct clk_div_mult_table *div_mult_table; |
159 | void (*kick)(struct clk *clk); | |
160 | }; | |
161 | ||
a60977a5 PM |
162 | #define clk_div4_table clk_div_table |
163 | ||
d28bdf05 MD |
164 | int sh_clk_div4_register(struct clk *clks, int nr, |
165 | struct clk_div4_table *table); | |
166 | int sh_clk_div4_enable_register(struct clk *clks, int nr, | |
167 | struct clk_div4_table *table); | |
168 | int sh_clk_div4_reparent_register(struct clk *clks, int nr, | |
169 | struct clk_div4_table *table); | |
170 | ||
56242a1f | 171 | #define SH_CLK_DIV6_EXT(_reg, _flags, _parents, \ |
b3dd51a8 GL |
172 | _num_parents, _src_shift, _src_width) \ |
173 | { \ | |
b3dd51a8 | 174 | .enable_reg = (void __iomem *)_reg, \ |
75f5f8a5 | 175 | .enable_bit = 0, /* unused */ \ |
b3dd51a8 | 176 | .flags = _flags, \ |
1111cc1e | 177 | .div_mask = SH_CLK_DIV6_MSK, \ |
b3dd51a8 GL |
178 | .parent_table = _parents, \ |
179 | .parent_num = _num_parents, \ | |
180 | .src_shift = _src_shift, \ | |
181 | .src_width = _src_width, \ | |
d28bdf05 MD |
182 | } |
183 | ||
b3dd51a8 | 184 | #define SH_CLK_DIV6(_parent, _reg, _flags) \ |
56242a1f KM |
185 | { \ |
186 | .parent = _parent, \ | |
187 | .enable_reg = (void __iomem *)_reg, \ | |
75f5f8a5 | 188 | .enable_bit = 0, /* unused */ \ |
1111cc1e | 189 | .div_mask = SH_CLK_DIV6_MSK, \ |
56242a1f KM |
190 | .flags = _flags, \ |
191 | } | |
b3dd51a8 | 192 | |
d28bdf05 | 193 | int sh_clk_div6_register(struct clk *clks, int nr); |
b3dd51a8 | 194 | int sh_clk_div6_reparent_register(struct clk *clks, int nr); |
d28bdf05 | 195 | |
1522043b KM |
196 | #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } |
197 | #define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk } | |
198 | #define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk } | |
199 | ||
d28bdf05 | 200 | #endif /* __SH_CLOCK_H */ |