Commit | Line | Data |
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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
d28bdf05 MD |
2 | #ifndef __SH_CLOCK_H |
3 | #define __SH_CLOCK_H | |
4 | ||
5 | #include <linux/list.h> | |
6 | #include <linux/seq_file.h> | |
7 | #include <linux/cpufreq.h> | |
28085bc5 PM |
8 | #include <linux/types.h> |
9 | #include <linux/kref.h> | |
d28bdf05 MD |
10 | #include <linux/clk.h> |
11 | #include <linux/err.h> | |
12 | ||
13 | struct clk; | |
14 | ||
28085bc5 PM |
15 | struct clk_mapping { |
16 | phys_addr_t phys; | |
17 | void __iomem *base; | |
18 | unsigned long len; | |
19 | struct kref ref; | |
20 | }; | |
21 | ||
84c36ffd | 22 | struct sh_clk_ops { |
549015c3 | 23 | #ifdef CONFIG_SH_CLK_CPG_LEGACY |
d28bdf05 | 24 | void (*init)(struct clk *clk); |
549015c3 | 25 | #endif |
d28bdf05 MD |
26 | int (*enable)(struct clk *clk); |
27 | void (*disable)(struct clk *clk); | |
28 | unsigned long (*recalc)(struct clk *clk); | |
35a96c73 | 29 | int (*set_rate)(struct clk *clk, unsigned long rate); |
d28bdf05 MD |
30 | int (*set_parent)(struct clk *clk, struct clk *parent); |
31 | long (*round_rate)(struct clk *clk, unsigned long rate); | |
32 | }; | |
33 | ||
1111cc1e PM |
34 | #define SH_CLK_DIV_MSK(div) ((1 << (div)) - 1) |
35 | #define SH_CLK_DIV4_MSK SH_CLK_DIV_MSK(4) | |
36 | #define SH_CLK_DIV6_MSK SH_CLK_DIV_MSK(6) | |
37 | ||
d28bdf05 MD |
38 | struct clk { |
39 | struct list_head node; | |
d28bdf05 | 40 | struct clk *parent; |
b5272b50 GL |
41 | struct clk **parent_table; /* list of parents to */ |
42 | unsigned short parent_num; /* choose between */ | |
43 | unsigned char src_shift; /* source clock field in the */ | |
44 | unsigned char src_width; /* configuration register */ | |
84c36ffd | 45 | struct sh_clk_ops *ops; |
d28bdf05 MD |
46 | |
47 | struct list_head children; | |
48 | struct list_head sibling; /* node for children */ | |
49 | ||
50 | int usecount; | |
51 | ||
52 | unsigned long rate; | |
53 | unsigned long flags; | |
54 | ||
55 | void __iomem *enable_reg; | |
a028c6da | 56 | void __iomem *status_reg; |
d28bdf05 | 57 | unsigned int enable_bit; |
eda2030a | 58 | void __iomem *mapped_reg; |
d28bdf05 | 59 | |
1111cc1e | 60 | unsigned int div_mask; |
d28bdf05 MD |
61 | unsigned long arch_flags; |
62 | void *priv; | |
28085bc5 | 63 | struct clk_mapping *mapping; |
d28bdf05 | 64 | struct cpufreq_frequency_table *freq_table; |
f586903d | 65 | unsigned int nr_freqs; |
d28bdf05 MD |
66 | }; |
67 | ||
4d6ddb08 PM |
68 | #define CLK_ENABLE_ON_INIT BIT(0) |
69 | ||
70 | #define CLK_ENABLE_REG_32BIT BIT(1) /* default access size */ | |
71 | #define CLK_ENABLE_REG_16BIT BIT(2) | |
72 | #define CLK_ENABLE_REG_8BIT BIT(3) | |
73 | ||
764f4e4e PM |
74 | #define CLK_MASK_DIV_ON_DISABLE BIT(4) |
75 | ||
4d6ddb08 PM |
76 | #define CLK_ENABLE_REG_MASK (CLK_ENABLE_REG_32BIT | \ |
77 | CLK_ENABLE_REG_16BIT | \ | |
78 | CLK_ENABLE_REG_8BIT) | |
d28bdf05 | 79 | |
a71ba096 | 80 | /* drivers/sh/clk.c */ |
d28bdf05 MD |
81 | unsigned long followparent_recalc(struct clk *); |
82 | void recalculate_root_clocks(void); | |
83 | void propagate_rate(struct clk *); | |
84 | int clk_reparent(struct clk *child, struct clk *parent); | |
85 | int clk_register(struct clk *); | |
86 | void clk_unregister(struct clk *); | |
8b5ee113 | 87 | void clk_enable_init_clocks(void); |
d28bdf05 | 88 | |
d28bdf05 MD |
89 | struct clk_div_mult_table { |
90 | unsigned int *divisors; | |
91 | unsigned int nr_divisors; | |
92 | unsigned int *multipliers; | |
93 | unsigned int nr_multipliers; | |
94 | }; | |
95 | ||
96 | struct cpufreq_frequency_table; | |
97 | void clk_rate_table_build(struct clk *clk, | |
98 | struct cpufreq_frequency_table *freq_table, | |
99 | int nr_freqs, | |
100 | struct clk_div_mult_table *src_table, | |
101 | unsigned long *bitmap); | |
102 | ||
103 | long clk_rate_table_round(struct clk *clk, | |
104 | struct cpufreq_frequency_table *freq_table, | |
105 | unsigned long rate); | |
106 | ||
107 | int clk_rate_table_find(struct clk *clk, | |
108 | struct cpufreq_frequency_table *freq_table, | |
109 | unsigned long rate); | |
110 | ||
8e122db6 PM |
111 | long clk_rate_div_range_round(struct clk *clk, unsigned int div_min, |
112 | unsigned int div_max, unsigned long rate); | |
113 | ||
dd2c0ca1 KM |
114 | long clk_rate_mult_range_round(struct clk *clk, unsigned int mult_min, |
115 | unsigned int mult_max, unsigned long rate); | |
116 | ||
a028c6da | 117 | #define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _status_reg, _flags) \ |
d28bdf05 MD |
118 | { \ |
119 | .parent = _parent, \ | |
120 | .enable_reg = (void __iomem *)_enable_reg, \ | |
121 | .enable_bit = _enable_bit, \ | |
a028c6da | 122 | .status_reg = _status_reg, \ |
d28bdf05 MD |
123 | .flags = _flags, \ |
124 | } | |
125 | ||
a028c6da GL |
126 | #define SH_CLK_MSTP32(_p, _r, _b, _f) \ |
127 | SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_32BIT) | |
4d6ddb08 | 128 | |
a028c6da GL |
129 | #define SH_CLK_MSTP32_STS(_p, _r, _b, _s, _f) \ |
130 | SH_CLK_MSTP(_p, _r, _b, _s, _f | CLK_ENABLE_REG_32BIT) | |
4d6ddb08 | 131 | |
a028c6da GL |
132 | #define SH_CLK_MSTP16(_p, _r, _b, _f) \ |
133 | SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_16BIT) | |
134 | ||
135 | #define SH_CLK_MSTP8(_p, _r, _b, _f) \ | |
136 | SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_8BIT) | |
4d6ddb08 PM |
137 | |
138 | int sh_clk_mstp_register(struct clk *clks, int nr); | |
139 | ||
140 | /* | |
141 | * MSTP registration never really cared about access size, despite the | |
142 | * original enable/disable pairs assuming a 32-bit access. Clocks are | |
143 | * responsible for defining their access sizes either directly or via the | |
144 | * clock definition wrappers. | |
145 | */ | |
146 | static inline int __deprecated sh_clk_mstp32_register(struct clk *clks, int nr) | |
147 | { | |
148 | return sh_clk_mstp_register(clks, nr); | |
149 | } | |
d28bdf05 MD |
150 | |
151 | #define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \ | |
152 | { \ | |
153 | .parent = _parent, \ | |
154 | .enable_reg = (void __iomem *)_reg, \ | |
155 | .enable_bit = _shift, \ | |
156 | .arch_flags = _div_bitmap, \ | |
1111cc1e | 157 | .div_mask = SH_CLK_DIV4_MSK, \ |
d28bdf05 MD |
158 | .flags = _flags, \ |
159 | } | |
160 | ||
a60977a5 | 161 | struct clk_div_table { |
d28bdf05 MD |
162 | struct clk_div_mult_table *div_mult_table; |
163 | void (*kick)(struct clk *clk); | |
164 | }; | |
165 | ||
a60977a5 PM |
166 | #define clk_div4_table clk_div_table |
167 | ||
d28bdf05 MD |
168 | int sh_clk_div4_register(struct clk *clks, int nr, |
169 | struct clk_div4_table *table); | |
170 | int sh_clk_div4_enable_register(struct clk *clks, int nr, | |
171 | struct clk_div4_table *table); | |
172 | int sh_clk_div4_reparent_register(struct clk *clks, int nr, | |
173 | struct clk_div4_table *table); | |
174 | ||
56242a1f | 175 | #define SH_CLK_DIV6_EXT(_reg, _flags, _parents, \ |
b3dd51a8 GL |
176 | _num_parents, _src_shift, _src_width) \ |
177 | { \ | |
b3dd51a8 | 178 | .enable_reg = (void __iomem *)_reg, \ |
75f5f8a5 | 179 | .enable_bit = 0, /* unused */ \ |
764f4e4e | 180 | .flags = _flags | CLK_MASK_DIV_ON_DISABLE, \ |
1111cc1e | 181 | .div_mask = SH_CLK_DIV6_MSK, \ |
b3dd51a8 GL |
182 | .parent_table = _parents, \ |
183 | .parent_num = _num_parents, \ | |
184 | .src_shift = _src_shift, \ | |
185 | .src_width = _src_width, \ | |
d28bdf05 MD |
186 | } |
187 | ||
b3dd51a8 | 188 | #define SH_CLK_DIV6(_parent, _reg, _flags) \ |
56242a1f KM |
189 | { \ |
190 | .parent = _parent, \ | |
191 | .enable_reg = (void __iomem *)_reg, \ | |
75f5f8a5 | 192 | .enable_bit = 0, /* unused */ \ |
1111cc1e | 193 | .div_mask = SH_CLK_DIV6_MSK, \ |
764f4e4e | 194 | .flags = _flags | CLK_MASK_DIV_ON_DISABLE, \ |
56242a1f | 195 | } |
b3dd51a8 | 196 | |
d28bdf05 | 197 | int sh_clk_div6_register(struct clk *clks, int nr); |
b3dd51a8 | 198 | int sh_clk_div6_reparent_register(struct clk *clks, int nr); |
d28bdf05 | 199 | |
1522043b KM |
200 | #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } |
201 | #define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk } | |
202 | #define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk } | |
203 | ||
9d626ecc KM |
204 | /* .enable_reg will be updated to .mapping on sh_clk_fsidiv_register() */ |
205 | #define SH_CLK_FSIDIV(_reg, _parent) \ | |
206 | { \ | |
207 | .enable_reg = (void __iomem *)_reg, \ | |
208 | .parent = _parent, \ | |
209 | } | |
210 | ||
211 | int sh_clk_fsidiv_register(struct clk *clks, int nr); | |
212 | ||
d28bdf05 | 213 | #endif /* __SH_CLOCK_H */ |