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1da177e4 LT |
1 | /* |
2 | * linux/drivers/char/serial_core.h | |
3 | * | |
4 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
20 | #ifndef LINUX_SERIAL_CORE_H | |
21 | #define LINUX_SERIAL_CORE_H | |
22 | ||
23 | /* | |
24 | * The type definitions. These are from Ted Ts'o's serial.h | |
25 | */ | |
26 | #define PORT_UNKNOWN 0 | |
27 | #define PORT_8250 1 | |
28 | #define PORT_16450 2 | |
29 | #define PORT_16550 3 | |
30 | #define PORT_16550A 4 | |
31 | #define PORT_CIRRUS 5 | |
32 | #define PORT_16650 6 | |
33 | #define PORT_16650V2 7 | |
34 | #define PORT_16750 8 | |
35 | #define PORT_STARTECH 9 | |
36 | #define PORT_16C950 10 | |
37 | #define PORT_16654 11 | |
38 | #define PORT_16850 12 | |
39 | #define PORT_RSA 13 | |
40 | #define PORT_NS16550A 14 | |
41 | #define PORT_XSCALE 15 | |
bd71c182 TK |
42 | #define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */ |
43 | #define PORT_MAX_8250 16 /* max port ID */ | |
1da177e4 LT |
44 | |
45 | /* | |
46 | * ARM specific type numbers. These are not currently guaranteed | |
47 | * to be implemented, and will change in the future. These are | |
48 | * separate so any additions to the old serial.c that occur before | |
49 | * we are merged can be easily merged here. | |
50 | */ | |
51 | #define PORT_PXA 31 | |
52 | #define PORT_AMBA 32 | |
53 | #define PORT_CLPS711X 33 | |
54 | #define PORT_SA1100 34 | |
55 | #define PORT_UART00 35 | |
56 | #define PORT_21285 37 | |
57 | ||
58 | /* Sparc type numbers. */ | |
59 | #define PORT_SUNZILOG 38 | |
60 | #define PORT_SUNSAB 39 | |
61 | ||
8b4a4080 MR |
62 | /* DEC */ |
63 | #define PORT_DZ 46 | |
64 | #define PORT_ZS 47 | |
1da177e4 LT |
65 | |
66 | /* Parisc type numbers. */ | |
67 | #define PORT_MUX 48 | |
68 | ||
9ab4f88b HS |
69 | /* Atmel AT91 / AT32 SoC */ |
70 | #define PORT_ATMEL 49 | |
1e6c9c28 | 71 | |
1da177e4 LT |
72 | /* Macintosh Zilog type numbers */ |
73 | #define PORT_MAC_ZILOG 50 /* m68k : not yet implemented */ | |
74 | #define PORT_PMAC_ZILOG 51 | |
75 | ||
76 | /* SH-SCI */ | |
77 | #define PORT_SCI 52 | |
78 | #define PORT_SCIF 53 | |
79 | #define PORT_IRDA 54 | |
80 | ||
81 | /* Samsung S3C2410 SoC and derivatives thereof */ | |
82 | #define PORT_S3C2410 55 | |
83 | ||
84 | /* SGI IP22 aka Indy / Challenge S / Indigo 2 */ | |
85 | #define PORT_IP22ZILOG 56 | |
86 | ||
87 | /* Sharp LH7a40x -- an ARM9 SoC series */ | |
88 | #define PORT_LH7A40X 57 | |
89 | ||
90 | /* PPC CPM type number */ | |
91 | #define PORT_CPM 58 | |
92 | ||
93 | /* MPC52xx type numbers */ | |
94 | #define PORT_MPC52xx 59 | |
95 | ||
96 | /* IBM icom */ | |
97 | #define PORT_ICOM 60 | |
98 | ||
99 | /* Samsung S3C2440 SoC */ | |
100 | #define PORT_S3C2440 61 | |
101 | ||
102 | /* Motorola i.MX SoC */ | |
103 | #define PORT_IMX 62 | |
104 | ||
105 | /* Marvell MPSC */ | |
106 | #define PORT_MPSC 63 | |
107 | ||
108 | /* TXX9 type number */ | |
e5c2d749 | 109 | #define PORT_TXX9 64 |
1da177e4 LT |
110 | |
111 | /* NEC VR4100 series SIU/DSIU */ | |
112 | #define PORT_VR41XX_SIU 65 | |
113 | #define PORT_VR41XX_DSIU 66 | |
114 | ||
115 | /* Samsung S3C2400 SoC */ | |
116 | #define PORT_S3C2400 67 | |
117 | ||
118 | /* M32R SIO */ | |
119 | #define PORT_M32R_SIO 68 | |
120 | ||
121 | /*Digi jsm */ | |
913ade51 RK |
122 | #define PORT_JSM 69 |
123 | ||
e6fa0ba3 | 124 | #define PORT_PNX8XXX 70 |
1da177e4 | 125 | |
f5417612 SH |
126 | /* Hilscher netx */ |
127 | #define PORT_NETX 71 | |
128 | ||
02fd473b DM |
129 | /* SUN4V Hypervisor Console */ |
130 | #define PORT_SUNHV 72 | |
131 | ||
73e55cb3 BD |
132 | #define PORT_S3C2412 73 |
133 | ||
238b8721 PK |
134 | /* Xilinx uartlite */ |
135 | #define PORT_UARTLITE 74 | |
73e55cb3 | 136 | |
194de561 BW |
137 | /* Blackfin bf5xx */ |
138 | #define PORT_BFIN 75 | |
139 | ||
2c7ee6ab AV |
140 | /* Micrel KS8695 */ |
141 | #define PORT_KS8695 76 | |
142 | ||
b45d5279 MR |
143 | /* Broadcom SB1250, etc. SOC */ |
144 | #define PORT_SB1250_DUART 77 | |
145 | ||
f0c15f48 GU |
146 | /* Freescale ColdFire */ |
147 | #define PORT_MCF 78 | |
148 | ||
2f351741 BW |
149 | /* Blackfin SPORT */ |
150 | #define PORT_BFIN_SPORT 79 | |
2c7ee6ab | 151 | |
ef3d5347 DH |
152 | /* MN10300 on-chip UART numbers */ |
153 | #define PORT_MN10300 80 | |
154 | #define PORT_MN10300_CTS 81 | |
155 | ||
2f351741 BW |
156 | #define PORT_SC26XX 82 |
157 | ||
1a22f08d YS |
158 | /* SH-SCI */ |
159 | #define PORT_SCIFA 83 | |
160 | ||
b690ace5 BD |
161 | #define PORT_S3C6400 84 |
162 | ||
1da177e4 LT |
163 | #ifdef __KERNEL__ |
164 | ||
661f83a6 | 165 | #include <linux/compiler.h> |
1da177e4 LT |
166 | #include <linux/interrupt.h> |
167 | #include <linux/circ_buf.h> | |
168 | #include <linux/spinlock.h> | |
169 | #include <linux/sched.h> | |
170 | #include <linux/tty.h> | |
e2862f6a | 171 | #include <linux/mutex.h> |
b11115c1 | 172 | #include <linux/sysrq.h> |
1da177e4 LT |
173 | |
174 | struct uart_port; | |
175 | struct uart_info; | |
176 | struct serial_struct; | |
177 | struct device; | |
178 | ||
179 | /* | |
180 | * This structure describes all the operations that can be | |
181 | * done on the physical hardware. | |
182 | */ | |
183 | struct uart_ops { | |
184 | unsigned int (*tx_empty)(struct uart_port *); | |
185 | void (*set_mctrl)(struct uart_port *, unsigned int mctrl); | |
186 | unsigned int (*get_mctrl)(struct uart_port *); | |
b129a8cc RK |
187 | void (*stop_tx)(struct uart_port *); |
188 | void (*start_tx)(struct uart_port *); | |
1da177e4 LT |
189 | void (*send_xchar)(struct uart_port *, char ch); |
190 | void (*stop_rx)(struct uart_port *); | |
191 | void (*enable_ms)(struct uart_port *); | |
192 | void (*break_ctl)(struct uart_port *, int ctl); | |
193 | int (*startup)(struct uart_port *); | |
194 | void (*shutdown)(struct uart_port *); | |
6bb0e3a5 | 195 | void (*flush_buffer)(struct uart_port *); |
606d099c AC |
196 | void (*set_termios)(struct uart_port *, struct ktermios *new, |
197 | struct ktermios *old); | |
64e9159f | 198 | void (*set_ldisc)(struct uart_port *); |
1da177e4 LT |
199 | void (*pm)(struct uart_port *, unsigned int state, |
200 | unsigned int oldstate); | |
201 | int (*set_wake)(struct uart_port *, unsigned int state); | |
202 | ||
203 | /* | |
204 | * Return a string describing the type of the port | |
205 | */ | |
206 | const char *(*type)(struct uart_port *); | |
207 | ||
208 | /* | |
209 | * Release IO and memory resources used by the port. | |
210 | * This includes iounmap if necessary. | |
211 | */ | |
212 | void (*release_port)(struct uart_port *); | |
213 | ||
214 | /* | |
215 | * Request IO and memory resources used by the port. | |
216 | * This includes iomapping the port if necessary. | |
217 | */ | |
218 | int (*request_port)(struct uart_port *); | |
219 | void (*config_port)(struct uart_port *, int); | |
220 | int (*verify_port)(struct uart_port *, struct serial_struct *); | |
221 | int (*ioctl)(struct uart_port *, unsigned int, unsigned long); | |
f2d937f3 JW |
222 | #ifdef CONFIG_CONSOLE_POLL |
223 | void (*poll_put_char)(struct uart_port *, unsigned char); | |
224 | int (*poll_get_char)(struct uart_port *); | |
225 | #endif | |
1da177e4 LT |
226 | }; |
227 | ||
228 | #define UART_CONFIG_TYPE (1 << 0) | |
229 | #define UART_CONFIG_IRQ (1 << 1) | |
230 | ||
231 | struct uart_icount { | |
232 | __u32 cts; | |
233 | __u32 dsr; | |
234 | __u32 rng; | |
235 | __u32 dcd; | |
236 | __u32 rx; | |
237 | __u32 tx; | |
238 | __u32 frame; | |
239 | __u32 overrun; | |
240 | __u32 parity; | |
241 | __u32 brk; | |
242 | __u32 buf_overrun; | |
243 | }; | |
244 | ||
0077d45e RK |
245 | typedef unsigned int __bitwise__ upf_t; |
246 | ||
1da177e4 LT |
247 | struct uart_port { |
248 | spinlock_t lock; /* port lock */ | |
0c8946d9 | 249 | unsigned long iobase; /* in/out[bwl] */ |
1da177e4 | 250 | unsigned char __iomem *membase; /* read/write[bwl] */ |
7d6a07d1 DD |
251 | unsigned int (*serial_in)(struct uart_port *, int); |
252 | void (*serial_out)(struct uart_port *, int, int); | |
1da177e4 LT |
253 | unsigned int irq; /* irq number */ |
254 | unsigned int uartclk; /* base uart clock */ | |
947deee8 | 255 | unsigned int fifosize; /* tx fifo size */ |
1da177e4 LT |
256 | unsigned char x_char; /* xon/xoff char */ |
257 | unsigned char regshift; /* reg offset shift */ | |
258 | unsigned char iotype; /* io access style */ | |
947deee8 | 259 | unsigned char unused1; |
1da177e4 LT |
260 | |
261 | #define UPIO_PORT (0) | |
262 | #define UPIO_HUB6 (1) | |
263 | #define UPIO_MEM (2) | |
264 | #define UPIO_MEM32 (3) | |
21c614a7 | 265 | #define UPIO_AU (4) /* Au1x00 type IO */ |
3be91ec7 | 266 | #define UPIO_TSI (5) /* Tsi108/109 type IO */ |
beab697a | 267 | #define UPIO_DWAPB (6) /* DesignWare APB UART */ |
bd71c182 | 268 | #define UPIO_RM9000 (7) /* RM9000 type IO */ |
1da177e4 LT |
269 | |
270 | unsigned int read_status_mask; /* driver specific */ | |
271 | unsigned int ignore_status_mask; /* driver specific */ | |
272 | struct uart_info *info; /* pointer to parent info */ | |
273 | struct uart_icount icount; /* statistics */ | |
274 | ||
275 | struct console *cons; /* struct console, if any */ | |
276 | #ifdef CONFIG_SERIAL_CORE_CONSOLE | |
277 | unsigned long sysrq; /* sysrq timeout */ | |
278 | #endif | |
279 | ||
0077d45e RK |
280 | upf_t flags; |
281 | ||
282 | #define UPF_FOURPORT ((__force upf_t) (1 << 1)) | |
283 | #define UPF_SAK ((__force upf_t) (1 << 2)) | |
284 | #define UPF_SPD_MASK ((__force upf_t) (0x1030)) | |
285 | #define UPF_SPD_HI ((__force upf_t) (0x0010)) | |
286 | #define UPF_SPD_VHI ((__force upf_t) (0x0020)) | |
287 | #define UPF_SPD_CUST ((__force upf_t) (0x0030)) | |
288 | #define UPF_SPD_SHI ((__force upf_t) (0x1000)) | |
289 | #define UPF_SPD_WARP ((__force upf_t) (0x1010)) | |
290 | #define UPF_SKIP_TEST ((__force upf_t) (1 << 6)) | |
291 | #define UPF_AUTO_IRQ ((__force upf_t) (1 << 7)) | |
292 | #define UPF_HARDPPS_CD ((__force upf_t) (1 << 11)) | |
293 | #define UPF_LOW_LATENCY ((__force upf_t) (1 << 13)) | |
294 | #define UPF_BUGGY_UART ((__force upf_t) (1 << 14)) | |
295 | #define UPF_MAGIC_MULTIPLIER ((__force upf_t) (1 << 16)) | |
296 | #define UPF_CONS_FLOW ((__force upf_t) (1 << 23)) | |
297 | #define UPF_SHARE_IRQ ((__force upf_t) (1 << 24)) | |
298 | #define UPF_BOOT_AUTOCONF ((__force upf_t) (1 << 28)) | |
abb4a239 | 299 | #define UPF_FIXED_PORT ((__force upf_t) (1 << 29)) |
68ac64cd | 300 | #define UPF_DEAD ((__force upf_t) (1 << 30)) |
0077d45e RK |
301 | #define UPF_IOREMAP ((__force upf_t) (1 << 31)) |
302 | ||
303 | #define UPF_CHANGE_MASK ((__force upf_t) (0x17fff)) | |
304 | #define UPF_USR_MASK ((__force upf_t) (UPF_SPD_MASK|UPF_LOW_LATENCY)) | |
1da177e4 LT |
305 | |
306 | unsigned int mctrl; /* current modem ctrl settings */ | |
307 | unsigned int timeout; /* character-based timeout */ | |
308 | unsigned int type; /* port type */ | |
ba899dbc | 309 | const struct uart_ops *ops; |
1da177e4 LT |
310 | unsigned int custom_divisor; |
311 | unsigned int line; /* port index */ | |
4f640efb | 312 | resource_size_t mapbase; /* for ioremap */ |
1da177e4 LT |
313 | struct device *dev; /* parent device */ |
314 | unsigned char hub6; /* this should be in the 8250 driver */ | |
b3b708fa GL |
315 | unsigned char suspended; |
316 | unsigned char unused[2]; | |
beab697a | 317 | void *private_data; /* generic platform data pointer */ |
1da177e4 LT |
318 | }; |
319 | ||
1da177e4 LT |
320 | /* |
321 | * This is the state information which is only valid when the port | |
f751928e | 322 | * is open; it may be cleared the core driver once the device has |
1da177e4 LT |
323 | * been closed. Either the low level driver or the core can modify |
324 | * stuff here. | |
325 | */ | |
f751928e AC |
326 | typedef unsigned int __bitwise__ uif_t; |
327 | ||
1da177e4 | 328 | struct uart_info { |
df4f4dd4 | 329 | struct tty_port port; |
1da177e4 | 330 | struct circ_buf xmit; |
747c8a55 | 331 | uif_t flags; |
1da177e4 LT |
332 | |
333 | /* | |
747c8a55 RK |
334 | * Definitions for info->flags. These are _private_ to serial_core, and |
335 | * are specific to this structure. They may be queried by low level drivers. | |
df4f4dd4 AC |
336 | * |
337 | * FIXME: use the ASY_ definitions | |
1da177e4 | 338 | */ |
747c8a55 RK |
339 | #define UIF_CHECK_CD ((__force uif_t) (1 << 25)) |
340 | #define UIF_CTS_FLOW ((__force uif_t) (1 << 26)) | |
341 | #define UIF_NORMAL_ACTIVE ((__force uif_t) (1 << 29)) | |
342 | #define UIF_INITIALIZED ((__force uif_t) (1 << 31)) | |
a6b93a90 | 343 | #define UIF_SUSPENDED ((__force uif_t) (1 << 30)) |
1da177e4 | 344 | |
1da177e4 | 345 | struct tasklet_struct tlet; |
1da177e4 LT |
346 | wait_queue_head_t delta_msr_wait; |
347 | }; | |
348 | ||
f751928e AC |
349 | /* |
350 | * This is the state information which is persistent across opens. | |
351 | * The low level driver must not to touch any elements contained | |
352 | * within. | |
353 | */ | |
354 | struct uart_state { | |
355 | unsigned int close_delay; /* msec */ | |
356 | unsigned int closing_wait; /* msec */ | |
357 | ||
358 | #define USF_CLOSING_WAIT_INF (0) | |
359 | #define USF_CLOSING_WAIT_NONE (~0U) | |
360 | ||
361 | int count; | |
362 | int pm_state; | |
363 | struct uart_info info; | |
364 | struct uart_port *port; | |
365 | ||
366 | struct mutex mutex; | |
367 | }; | |
368 | ||
369 | #define UART_XMIT_SIZE PAGE_SIZE | |
370 | ||
371 | ||
1da177e4 LT |
372 | /* number of characters left in xmit buffer before we ask for more */ |
373 | #define WAKEUP_CHARS 256 | |
374 | ||
375 | struct module; | |
376 | struct tty_driver; | |
377 | ||
378 | struct uart_driver { | |
379 | struct module *owner; | |
380 | const char *driver_name; | |
381 | const char *dev_name; | |
1da177e4 LT |
382 | int major; |
383 | int minor; | |
384 | int nr; | |
385 | struct console *cons; | |
386 | ||
387 | /* | |
388 | * these are private; the low level driver should not | |
389 | * touch these; they should be initialised to NULL | |
390 | */ | |
391 | struct uart_state *state; | |
392 | struct tty_driver *tty_driver; | |
393 | }; | |
394 | ||
395 | void uart_write_wakeup(struct uart_port *port); | |
396 | ||
397 | /* | |
398 | * Baud rate helpers. | |
399 | */ | |
400 | void uart_update_timeout(struct uart_port *port, unsigned int cflag, | |
401 | unsigned int baud); | |
606d099c AC |
402 | unsigned int uart_get_baud_rate(struct uart_port *port, struct ktermios *termios, |
403 | struct ktermios *old, unsigned int min, | |
1da177e4 LT |
404 | unsigned int max); |
405 | unsigned int uart_get_divisor(struct uart_port *port, unsigned int baud); | |
406 | ||
407 | /* | |
408 | * Console helpers. | |
409 | */ | |
410 | struct uart_port *uart_get_console(struct uart_port *ports, int nr, | |
411 | struct console *c); | |
412 | void uart_parse_options(char *options, int *baud, int *parity, int *bits, | |
413 | int *flow); | |
414 | int uart_set_options(struct uart_port *port, struct console *co, int baud, | |
415 | int parity, int bits, int flow); | |
416 | struct tty_driver *uart_console_device(struct console *co, int *index); | |
d358788f RK |
417 | void uart_console_write(struct uart_port *port, const char *s, |
418 | unsigned int count, | |
419 | void (*putchar)(struct uart_port *, int)); | |
1da177e4 LT |
420 | |
421 | /* | |
422 | * Port/driver registration/removal | |
423 | */ | |
424 | int uart_register_driver(struct uart_driver *uart); | |
425 | void uart_unregister_driver(struct uart_driver *uart); | |
1da177e4 LT |
426 | int uart_add_one_port(struct uart_driver *reg, struct uart_port *port); |
427 | int uart_remove_one_port(struct uart_driver *reg, struct uart_port *port); | |
428 | int uart_match_port(struct uart_port *port1, struct uart_port *port2); | |
429 | ||
430 | /* | |
431 | * Power Management | |
432 | */ | |
433 | int uart_suspend_port(struct uart_driver *reg, struct uart_port *port); | |
434 | int uart_resume_port(struct uart_driver *reg, struct uart_port *port); | |
435 | ||
436 | #define uart_circ_empty(circ) ((circ)->head == (circ)->tail) | |
437 | #define uart_circ_clear(circ) ((circ)->head = (circ)->tail = 0) | |
438 | ||
439 | #define uart_circ_chars_pending(circ) \ | |
440 | (CIRC_CNT((circ)->head, (circ)->tail, UART_XMIT_SIZE)) | |
441 | ||
442 | #define uart_circ_chars_free(circ) \ | |
443 | (CIRC_SPACE((circ)->head, (circ)->tail, UART_XMIT_SIZE)) | |
444 | ||
f751928e AC |
445 | static inline int uart_tx_stopped(struct uart_port *port) |
446 | { | |
447 | struct tty_struct *tty = port->info->port.tty; | |
448 | if(tty->stopped || tty->hw_stopped) | |
449 | return 1; | |
450 | return 0; | |
451 | } | |
1da177e4 LT |
452 | |
453 | /* | |
454 | * The following are helper functions for the low level drivers. | |
455 | */ | |
1da177e4 | 456 | static inline int |
7d12e780 | 457 | uart_handle_sysrq_char(struct uart_port *port, unsigned int ch) |
1da177e4 | 458 | { |
93c37f29 | 459 | #ifdef SUPPORT_SYSRQ |
1da177e4 LT |
460 | if (port->sysrq) { |
461 | if (ch && time_before(jiffies, port->sysrq)) { | |
f751928e | 462 | handle_sysrq(ch, port->info->port.tty); |
1da177e4 LT |
463 | port->sysrq = 0; |
464 | return 1; | |
465 | } | |
466 | port->sysrq = 0; | |
467 | } | |
93c37f29 | 468 | #endif |
1da177e4 LT |
469 | return 0; |
470 | } | |
4e149184 | 471 | #ifndef SUPPORT_SYSRQ |
7d12e780 | 472 | #define uart_handle_sysrq_char(port,ch) uart_handle_sysrq_char(port, 0) |
4e149184 | 473 | #endif |
1da177e4 LT |
474 | |
475 | /* | |
476 | * We do the SysRQ and SAK checking like this... | |
477 | */ | |
478 | static inline int uart_handle_break(struct uart_port *port) | |
479 | { | |
480 | struct uart_info *info = port->info; | |
481 | #ifdef SUPPORT_SYSRQ | |
482 | if (port->cons && port->cons->index == port->line) { | |
483 | if (!port->sysrq) { | |
484 | port->sysrq = jiffies + HZ*5; | |
485 | return 1; | |
486 | } | |
487 | port->sysrq = 0; | |
488 | } | |
489 | #endif | |
27ae7a74 | 490 | if (port->flags & UPF_SAK) |
df4f4dd4 | 491 | do_SAK(info->port.tty); |
1da177e4 LT |
492 | return 0; |
493 | } | |
494 | ||
495 | /** | |
496 | * uart_handle_dcd_change - handle a change of carrier detect state | |
497 | * @port: uart_port structure for the open port | |
498 | * @status: new carrier detect status, nonzero if active | |
499 | */ | |
500 | static inline void | |
501 | uart_handle_dcd_change(struct uart_port *port, unsigned int status) | |
502 | { | |
503 | struct uart_info *info = port->info; | |
504 | ||
505 | port->icount.dcd++; | |
506 | ||
507 | #ifdef CONFIG_HARD_PPS | |
508 | if ((port->flags & UPF_HARDPPS_CD) && status) | |
509 | hardpps(); | |
510 | #endif | |
511 | ||
512 | if (info->flags & UIF_CHECK_CD) { | |
513 | if (status) | |
df4f4dd4 AC |
514 | wake_up_interruptible(&info->port.open_wait); |
515 | else if (info->port.tty) | |
516 | tty_hangup(info->port.tty); | |
1da177e4 LT |
517 | } |
518 | } | |
519 | ||
520 | /** | |
521 | * uart_handle_cts_change - handle a change of clear-to-send state | |
522 | * @port: uart_port structure for the open port | |
523 | * @status: new clear to send status, nonzero if active | |
524 | */ | |
525 | static inline void | |
526 | uart_handle_cts_change(struct uart_port *port, unsigned int status) | |
527 | { | |
528 | struct uart_info *info = port->info; | |
df4f4dd4 | 529 | struct tty_struct *tty = info->port.tty; |
1da177e4 LT |
530 | |
531 | port->icount.cts++; | |
532 | ||
533 | if (info->flags & UIF_CTS_FLOW) { | |
534 | if (tty->hw_stopped) { | |
535 | if (status) { | |
536 | tty->hw_stopped = 0; | |
b129a8cc | 537 | port->ops->start_tx(port); |
1da177e4 LT |
538 | uart_write_wakeup(port); |
539 | } | |
540 | } else { | |
541 | if (!status) { | |
542 | tty->hw_stopped = 1; | |
b129a8cc | 543 | port->ops->stop_tx(port); |
1da177e4 LT |
544 | } |
545 | } | |
546 | } | |
547 | } | |
548 | ||
05ab3014 RK |
549 | #include <linux/tty_flip.h> |
550 | ||
551 | static inline void | |
552 | uart_insert_char(struct uart_port *port, unsigned int status, | |
553 | unsigned int overrun, unsigned int ch, unsigned int flag) | |
554 | { | |
df4f4dd4 | 555 | struct tty_struct *tty = port->info->port.tty; |
05ab3014 RK |
556 | |
557 | if ((status & port->ignore_status_mask & ~overrun) == 0) | |
558 | tty_insert_flip_char(tty, ch, flag); | |
559 | ||
560 | /* | |
561 | * Overrun is special. Since it's reported immediately, | |
562 | * it doesn't affect the current character. | |
563 | */ | |
564 | if (status & ~port->ignore_status_mask & overrun) | |
565 | tty_insert_flip_char(tty, 0, TTY_OVERRUN); | |
566 | } | |
567 | ||
1da177e4 LT |
568 | /* |
569 | * UART_ENABLE_MS - determine if port should enable modem status irqs | |
570 | */ | |
571 | #define UART_ENABLE_MS(port,cflag) ((port)->flags & UPF_HARDPPS_CD || \ | |
572 | (cflag) & CRTSCTS || \ | |
573 | !((cflag) & CLOCAL)) | |
574 | ||
575 | #endif | |
576 | ||
577 | #endif /* LINUX_SERIAL_CORE_H */ |