[linux-2.6-block.git] / include / linux / serial_core.h

/*
 *  linux/drivers/char/serial_core.h
 *
 *  Copyright (C) 2000 Deep Blue Solutions Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#ifndef LINUX_SERIAL_CORE_H
#define LINUX_SERIAL_CORE_H

#include <linux/serial.h>

/*
 * The type definitions.  These are from Ted Ts'o's serial.h
 */
#define PORT_UNKNOWN	0
#define PORT_8250	1
#define PORT_16450	2
#define PORT_16550	3
#define PORT_16550A	4
#define PORT_CIRRUS	5
#define PORT_16650	6
#define PORT_16650V2	7
#define PORT_16750	8
#define PORT_STARTECH	9
#define PORT_16C950	10
#define PORT_16654	11
#define PORT_16850	12
#define PORT_RSA	13
#define PORT_NS16550A	14
#define PORT_XSCALE	15
#define PORT_RM9000	16	/* PMC-Sierra RM9xxx internal UART */
#define PORT_OCTEON	17	/* Cavium OCTEON internal UART */
#define PORT_AR7	18	/* Texas Instruments AR7 internal UART */
#define PORT_MAX_8250	18	/* max port ID */

/*
 * ARM specific type numbers.  These are not currently guaranteed
 * to be implemented, and will change in the future.  These are
 * separate so any additions to the old serial.c that occur before
 * we are merged can be easily merged here.
 */
#define PORT_PXA	31
#define PORT_AMBA	32
#define PORT_CLPS711X	33
#define PORT_SA1100	34
#define PORT_UART00	35
#define PORT_21285	37

/* Sparc type numbers.  */
#define PORT_SUNZILOG	38
#define PORT_SUNSAB	39

/* DEC */
#define PORT_DZ		46
#define PORT_ZS		47

/* Parisc type numbers. */
#define PORT_MUX	48

/* Atmel AT91 / AT32 SoC */
#define PORT_ATMEL	49

/* Macintosh Zilog type numbers */
#define PORT_MAC_ZILOG	50	/* m68k : not yet implemented */
#define PORT_PMAC_ZILOG	51

/* SH-SCI */
#define PORT_SCI	52
#define PORT_SCIF	53
#define PORT_IRDA	54

/* Samsung S3C2410 SoC and derivatives thereof */
#define PORT_S3C2410    55

/* SGI IP22 aka Indy / Challenge S / Indigo 2 */
#define PORT_IP22ZILOG	56

/* Sharp LH7a40x -- an ARM9 SoC series */
#define PORT_LH7A40X	57

/* PPC CPM type number */
#define PORT_CPM        58

/* MPC52xx type numbers */
#define PORT_MPC52xx	59

/* IBM icom */
#define PORT_ICOM	60

/* Samsung S3C2440 SoC */
#define PORT_S3C2440	61

/* Motorola i.MX SoC */
#define PORT_IMX	62

/* Marvell MPSC */
#define PORT_MPSC	63

/* TXX9 type number */
#define PORT_TXX9	64

/* NEC VR4100 series SIU/DSIU */
#define PORT_VR41XX_SIU		65
#define PORT_VR41XX_DSIU	66

/* Samsung S3C2400 SoC */
#define PORT_S3C2400	67

/* M32R SIO */
#define PORT_M32R_SIO	68

/*Digi jsm */
#define PORT_JSM        69

#define PORT_PNX8XXX	70

/* Hilscher netx */
#define PORT_NETX	71

/* SUN4V Hypervisor Console */
#define PORT_SUNHV	72

#define PORT_S3C2412	73

/* Xilinx uartlite */
#define PORT_UARTLITE	74

/* Blackfin bf5xx */
#define PORT_BFIN	75

/* Micrel KS8695 */
#define PORT_KS8695	76

/* Broadcom SB1250, etc. SOC */
#define PORT_SB1250_DUART	77

/* Freescale ColdFire */
#define PORT_MCF	78

/* Blackfin SPORT */
#define PORT_BFIN_SPORT		79

/* MN10300 on-chip UART numbers */
#define PORT_MN10300		80
#define PORT_MN10300_CTS	81

#define PORT_SC26XX	82

/* SH-SCI */
#define PORT_SCIFA	83

#define PORT_S3C6400	84

/* NWPSERIAL */
#define PORT_NWPSERIAL	85

/* MAX3100 */
#define PORT_MAX3100    86

/* Timberdale UART */
#define PORT_TIMBUART	87

/* Qualcomm MSM SoCs */
#define PORT_MSM	88

/* BCM63xx family SoCs */
#define PORT_BCM63XX	89

/* Aeroflex Gaisler GRLIB APBUART */
#define PORT_APBUART    90

/* Altera UARTs */
#define PORT_ALTERA_JTAGUART	91
#define PORT_ALTERA_UART	92

/* MAX3107 */
#define PORT_MAX3107	94


#ifdef __KERNEL__

#include <linux/compiler.h>
#include <linux/interrupt.h>
#include <linux/circ_buf.h>
#include <linux/spinlock.h>
#include <linux/sched.h>
#include <linux/tty.h>
#include <linux/mutex.h>
#include <linux/sysrq.h>

struct uart_port;
struct serial_struct;
struct device;

/*
 * This structure describes all the operations that can be
 * done on the physical hardware.
 */
struct uart_ops {
	unsigned int	(*tx_empty)(struct uart_port *);
	void		(*set_mctrl)(struct uart_port *, unsigned int mctrl);
	unsigned int	(*get_mctrl)(struct uart_port *);
	void		(*stop_tx)(struct uart_port *);
	void		(*start_tx)(struct uart_port *);
	void		(*send_xchar)(struct uart_port *, char ch);
	void		(*stop_rx)(struct uart_port *);
	void		(*enable_ms)(struct uart_port *);
	void		(*break_ctl)(struct uart_port *, int ctl);
	int		(*startup)(struct uart_port *);
	void		(*shutdown)(struct uart_port *);
	void		(*flush_buffer)(struct uart_port *);
	void		(*set_termios)(struct uart_port *, struct ktermios *new,
				       struct ktermios *old);
	void		(*set_ldisc)(struct uart_port *, int new);
	void		(*pm)(struct uart_port *, unsigned int state,
			      unsigned int oldstate);
	int		(*set_wake)(struct uart_port *, unsigned int state);

	/*
	 * Return a string describing the type of the port
	 */
	const char *(*type)(struct uart_port *);

	/*
	 * Release IO and memory resources used by the port.
	 * This includes iounmap if necessary.
	 */
	void		(*release_port)(struct uart_port *);

	/*
	 * Request IO and memory resources used by the port.
	 * This includes iomapping the port if necessary.
	 */
	int		(*request_port)(struct uart_port *);
	void		(*config_port)(struct uart_port *, int);
	int		(*verify_port)(struct uart_port *, struct serial_struct *);
	int		(*ioctl)(struct uart_port *, unsigned int, unsigned long);
#ifdef CONFIG_CONSOLE_POLL
	void	(*poll_put_char)(struct uart_port *, unsigned char);
	int		(*poll_get_char)(struct uart_port *);
#endif
};

#define NO_POLL_CHAR		0x00ff0000
#define UART_CONFIG_TYPE	(1 << 0)
#define UART_CONFIG_IRQ		(1 << 1)

struct uart_icount {
	__u32	cts;
	__u32	dsr;
	__u32	rng;
	__u32	dcd;
	__u32	rx;
	__u32	tx;
	__u32	frame;
	__u32	overrun;
	__u32	parity;
	__u32	brk;
	__u32	buf_overrun;
};

typedef unsigned int __bitwise__ upf_t;

struct uart_port {
	spinlock_t		lock;			/* port lock */
	unsigned long		iobase;			/* in/out[bwl] */
	unsigned char __iomem	*membase;		/* read/write[bwl] */
	unsigned int		(*serial_in)(struct uart_port *, int);
	void			(*serial_out)(struct uart_port *, int, int);
	unsigned int		irq;			/* irq number */
	unsigned long		irqflags;		/* irq flags  */
	unsigned int		uartclk;		/* base uart clock */
	unsigned int		fifosize;		/* tx fifo size */
	unsigned char		x_char;			/* xon/xoff char */
	unsigned char		regshift;		/* reg offset shift */
	unsigned char		iotype;			/* io access style */
	unsigned char		unused1;

#define UPIO_PORT		(0)
#define UPIO_HUB6		(1)
#define UPIO_MEM		(2)
#define UPIO_MEM32		(3)
#define UPIO_AU			(4)			/* Au1x00 type IO */
#define UPIO_TSI		(5)			/* Tsi108/109 type IO */
#define UPIO_DWAPB		(6)			/* DesignWare APB UART */
#define UPIO_RM9000		(7)			/* RM9000 type IO */

	unsigned int		read_status_mask;	/* driver specific */
	unsigned int		ignore_status_mask;	/* driver specific */
	struct uart_state	*state;			/* pointer to parent state */
	struct uart_icount	icount;			/* statistics */

	struct console		*cons;			/* struct console, if any */
#if defined(CONFIG_SERIAL_CORE_CONSOLE) || defined(SUPPORT_SYSRQ)
	unsigned long		sysrq;			/* sysrq timeout */
#endif

	upf_t			flags;

#define UPF_FOURPORT		((__force upf_t) (1 << 1))
#define UPF_SAK			((__force upf_t) (1 << 2))
#define UPF_SPD_MASK		((__force upf_t) (0x1030))
#define UPF_SPD_HI		((__force upf_t) (0x0010))
#define UPF_SPD_VHI		((__force upf_t) (0x0020))
#define UPF_SPD_CUST		((__force upf_t) (0x0030))
#define UPF_SPD_SHI		((__force upf_t) (0x1000))
#define UPF_SPD_WARP		((__force upf_t) (0x1010))
#define UPF_SKIP_TEST		((__force upf_t) (1 << 6))
#define UPF_AUTO_IRQ		((__force upf_t) (1 << 7))
#define UPF_HARDPPS_CD		((__force upf_t) (1 << 11))
#define UPF_LOW_LATENCY		((__force upf_t) (1 << 13))
#define UPF_BUGGY_UART		((__force upf_t) (1 << 14))
#define UPF_NO_TXEN_TEST	((__force upf_t) (1 << 15))
#define UPF_MAGIC_MULTIPLIER	((__force upf_t) (1 << 16))
#define UPF_CONS_FLOW		((__force upf_t) (1 << 23))
#define UPF_SHARE_IRQ		((__force upf_t) (1 << 24))
/* The exact UART type is known and should not be probed.  */
#define UPF_FIXED_TYPE		((__force upf_t) (1 << 27))
#define UPF_BOOT_AUTOCONF	((__force upf_t) (1 << 28))
#define UPF_FIXED_PORT		((__force upf_t) (1 << 29))
#define UPF_DEAD		((__force upf_t) (1 << 30))
#define UPF_IOREMAP		((__force upf_t) (1 << 31))

#define UPF_CHANGE_MASK		((__force upf_t) (0x17fff))
#define UPF_USR_MASK		((__force upf_t) (UPF_SPD_MASK|UPF_LOW_LATENCY))

	unsigned int		mctrl;			/* current modem ctrl settings */
	unsigned int		timeout;		/* character-based timeout */
	unsigned int		type;			/* port type */
	const struct uart_ops	*ops;
	unsigned int		custom_divisor;
	unsigned int		line;			/* port index */
	resource_size_t		mapbase;		/* for ioremap */
	struct device		*dev;			/* parent device */
	unsigned char		hub6;			/* this should be in the 8250 driver */
	unsigned char		suspended;
	unsigned char		unused[2];
	void			*private_data;		/* generic platform data pointer */
};

/*
 * This is the state information which is persistent across opens.
 */
struct uart_state {
	struct tty_port		port;

	int			pm_state;
	struct circ_buf		xmit;

	struct tasklet_struct	tlet;
	struct uart_port	*uart_port;
};

#define UART_XMIT_SIZE	PAGE_SIZE


/* number of characters left in xmit buffer before we ask for more */
#define WAKEUP_CHARS		256

struct module;
struct tty_driver;

struct uart_driver {
	struct module		*owner;
	const char		*driver_name;
	const char		*dev_name;
	int			 major;
	int			 minor;
	int			 nr;
	struct console		*cons;

	/*
	 * these are private; the low level driver should not
	 * touch these; they should be initialised to NULL
	 */
	struct uart_state	*state;
	struct tty_driver	*tty_driver;
};

void uart_write_wakeup(struct uart_port *port);

/*
 * Baud rate helpers.
 */
void uart_update_timeout(struct uart_port *port, unsigned int cflag,
			 unsigned int baud);
unsigned int uart_get_baud_rate(struct uart_port *port, struct ktermios *termios,
				struct ktermios *old, unsigned int min,
				unsigned int max);
unsigned int uart_get_divisor(struct uart_port *port, unsigned int baud);

/*
 * Console helpers.
 */
struct uart_port *uart_get_console(struct uart_port *ports, int nr,
				   struct console *c);
void uart_parse_options(char *options, int *baud, int *parity, int *bits,
			int *flow);
int uart_set_options(struct uart_port *port, struct console *co, int baud,
		     int parity, int bits, int flow);
struct tty_driver *uart_console_device(struct console *co, int *index);
void uart_console_write(struct uart_port *port, const char *s,
			unsigned int count,
			void (*putchar)(struct uart_port *, int));

/*
 * Port/driver registration/removal
 */
int uart_register_driver(struct uart_driver *uart);
void uart_unregister_driver(struct uart_driver *uart);
int uart_add_one_port(struct uart_driver *reg, struct uart_port *port);
int uart_remove_one_port(struct uart_driver *reg, struct uart_port *port);
int uart_match_port(struct uart_port *port1, struct uart_port *port2);

/*
 * Power Management
 */
int uart_suspend_port(struct uart_driver *reg, struct uart_port *port);
int uart_resume_port(struct uart_driver *reg, struct uart_port *port);

#define uart_circ_empty(circ)		((circ)->head == (circ)->tail)
#define uart_circ_clear(circ)		((circ)->head = (circ)->tail = 0)

#define uart_circ_chars_pending(circ)	\
	(CIRC_CNT((circ)->head, (circ)->tail, UART_XMIT_SIZE))

#define uart_circ_chars_free(circ)	\
	(CIRC_SPACE((circ)->head, (circ)->tail, UART_XMIT_SIZE))

static inline int uart_tx_stopped(struct uart_port *port)
{
	struct tty_struct *tty = port->state->port.tty;
	if(tty->stopped || tty->hw_stopped)
		return 1;
	return 0;
}

/*
 * The following are helper functions for the low level drivers.
 */
static inline int
uart_handle_sysrq_char(struct uart_port *port, unsigned int ch)
{
#ifdef SUPPORT_SYSRQ
	if (port->sysrq) {
		if (ch && time_before(jiffies, port->sysrq)) {
			handle_sysrq(ch, port->state->port.tty);
			port->sysrq = 0;
			return 1;
		}
		port->sysrq = 0;
	}
#endif
	return 0;
}
#ifndef SUPPORT_SYSRQ
#define uart_handle_sysrq_char(port,ch) uart_handle_sysrq_char(port, 0)
#endif

/*
 * We do the SysRQ and SAK checking like this...
 */
static inline int uart_handle_break(struct uart_port *port)
{
	struct uart_state *state = port->state;
#ifdef SUPPORT_SYSRQ
	if (port->cons && port->cons->index == port->line) {
		if (!port->sysrq) {
			port->sysrq = jiffies + HZ*5;
			return 1;
		}
		port->sysrq = 0;
	}
#endif
	if (port->flags & UPF_SAK)
		do_SAK(state->port.tty);
	return 0;
}

/**
 *	uart_handle_dcd_change - handle a change of carrier detect state
 *	@uport: uart_port structure for the open port
 *	@status: new carrier detect status, nonzero if active
 */
static inline void
uart_handle_dcd_change(struct uart_port *uport, unsigned int status)
{
	struct uart_state *state = uport->state;
	struct tty_port *port = &state->port;
	struct tty_ldisc *ld = tty_ldisc_ref(port->tty);
	struct timespec ts;

	if (ld && ld->ops->dcd_change)
		getnstimeofday(&ts);

	uport->icount.dcd++;
#ifdef CONFIG_HARD_PPS
	if ((uport->flags & UPF_HARDPPS_CD) && status)
		hardpps();
#endif

	if (port->flags & ASYNC_CHECK_CD) {
		if (status)
			wake_up_interruptible(&port->open_wait);
		else if (port->tty)
			tty_hangup(port->tty);
	}

	if (ld && ld->ops->dcd_change)
		ld->ops->dcd_change(port->tty, status, &ts);
	if (ld)
		tty_ldisc_deref(ld);
}

/**
 *	uart_handle_cts_change - handle a change of clear-to-send state
 *	@uport: uart_port structure for the open port
 *	@status: new clear to send status, nonzero if active
 */
static inline void
uart_handle_cts_change(struct uart_port *uport, unsigned int status)
{
	struct tty_port *port = &uport->state->port;
	struct tty_struct *tty = port->tty;

	uport->icount.cts++;

	if (port->flags & ASYNC_CTS_FLOW) {
		if (tty->hw_stopped) {
			if (status) {
				tty->hw_stopped = 0;
				uport->ops->start_tx(uport);
				uart_write_wakeup(uport);
			}
		} else {
			if (!status) {
				tty->hw_stopped = 1;
				uport->ops->stop_tx(uport);
			}
		}
	}
}

#include <linux/tty_flip.h>

static inline void
uart_insert_char(struct uart_port *port, unsigned int status,
		 unsigned int overrun, unsigned int ch, unsigned int flag)
{
	struct tty_struct *tty = port->state->port.tty;

	if ((status & port->ignore_status_mask & ~overrun) == 0)
		tty_insert_flip_char(tty, ch, flag);

	/*
	 * Overrun is special.  Since it's reported immediately,
	 * it doesn't affect the current character.
	 */
	if (status & ~port->ignore_status_mask & overrun)
		tty_insert_flip_char(tty, 0, TTY_OVERRUN);
}

/*
 *	UART_ENABLE_MS - determine if port should enable modem status irqs
 */
#define UART_ENABLE_MS(port,cflag)	((port)->flags & UPF_HARDPPS_CD || \
					 (cflag) & CRTSCTS || \
					 !((cflag) & CLOCAL))

#endif

#endif /* LINUX_SERIAL_CORE_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/drivers/char/serial_core.h
	3	*
	4	* Copyright (C) 2000 Deep Blue Solutions Ltd.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#ifndef LINUX_SERIAL_CORE_H
	21	#define LINUX_SERIAL_CORE_H
	22
ccce6deb AC	23	#include <linux/serial.h>
ccce6deb AC	24
1da177e4 LT	25	/*
	26	* The type definitions. These are from Ted Ts'o's serial.h
	27	*/
	28	#define PORT_UNKNOWN 0
	29	#define PORT_8250 1
	30	#define PORT_16450 2
	31	#define PORT_16550 3
	32	#define PORT_16550A 4
	33	#define PORT_CIRRUS 5
	34	#define PORT_16650 6
	35	#define PORT_16650V2 7
	36	#define PORT_16750 8
	37	#define PORT_STARTECH 9
	38	#define PORT_16C950 10
	39	#define PORT_16654 11
	40	#define PORT_16850 12
	41	#define PORT_RSA 13
	42	#define PORT_NS16550A 14
	43	#define PORT_XSCALE 15
bd71c182	44	#define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */
6b06f191	45	#define PORT_OCTEON 17 /* Cavium OCTEON internal UART */
08e0992f FF	46	#define PORT_AR7 18 /* Texas Instruments AR7 internal UART */
08e0992f FF	47	#define PORT_MAX_8250 18 /* max port ID */
1da177e4 LT	48
	49	/*
	50	* ARM specific type numbers. These are not currently guaranteed
	51	* to be implemented, and will change in the future. These are
	52	* separate so any additions to the old serial.c that occur before
	53	* we are merged can be easily merged here.
	54	*/
	55	#define PORT_PXA 31
	56	#define PORT_AMBA 32
	57	#define PORT_CLPS711X 33
	58	#define PORT_SA1100 34
	59	#define PORT_UART00 35
	60	#define PORT_21285 37
	61
	62	/* Sparc type numbers. */
	63	#define PORT_SUNZILOG 38
	64	#define PORT_SUNSAB 39
	65
8b4a4080 MR	66	/* DEC */
	67	#define PORT_DZ 46
	68	#define PORT_ZS 47
1da177e4 LT	69
	70	/* Parisc type numbers. */
	71	#define PORT_MUX 48
	72
9ab4f88b HS	73	/* Atmel AT91 / AT32 SoC */
9ab4f88b HS	74	#define PORT_ATMEL 49
1e6c9c28	75
1da177e4 LT	76	/* Macintosh Zilog type numbers */
	77	#define PORT_MAC_ZILOG 50 /* m68k : not yet implemented */
	78	#define PORT_PMAC_ZILOG 51
	79
	80	/* SH-SCI */
	81	#define PORT_SCI 52
	82	#define PORT_SCIF 53
	83	#define PORT_IRDA 54
	84
	85	/* Samsung S3C2410 SoC and derivatives thereof */
	86	#define PORT_S3C2410 55
	87
	88	/* SGI IP22 aka Indy / Challenge S / Indigo 2 */
	89	#define PORT_IP22ZILOG 56
	90
	91	/* Sharp LH7a40x -- an ARM9 SoC series */
	92	#define PORT_LH7A40X 57
	93
	94	/* PPC CPM type number */
	95	#define PORT_CPM 58
	96
	97	/* MPC52xx type numbers */
	98	#define PORT_MPC52xx 59
	99
	100	/* IBM icom */
	101	#define PORT_ICOM 60
	102
	103	/* Samsung S3C2440 SoC */
	104	#define PORT_S3C2440 61
	105
	106	/* Motorola i.MX SoC */
	107	#define PORT_IMX 62
	108
	109	/* Marvell MPSC */
	110	#define PORT_MPSC 63
	111
	112	/* TXX9 type number */
e5c2d749	113	#define PORT_TXX9 64
1da177e4 LT	114
	115	/* NEC VR4100 series SIU/DSIU */
	116	#define PORT_VR41XX_SIU 65
	117	#define PORT_VR41XX_DSIU 66
	118
	119	/* Samsung S3C2400 SoC */
	120	#define PORT_S3C2400 67
	121
	122	/* M32R SIO */
	123	#define PORT_M32R_SIO 68
	124
	125	/Digi jsm /
913ade51 RK	126	#define PORT_JSM 69
913ade51 RK	127
e6fa0ba3	128	#define PORT_PNX8XXX 70
1da177e4	129
f5417612 SH	130	/* Hilscher netx */
	131	#define PORT_NETX 71
	132
02fd473b DM	133	/* SUN4V Hypervisor Console */
	134	#define PORT_SUNHV 72
	135
73e55cb3 BD	136	#define PORT_S3C2412 73
73e55cb3 BD	137
238b8721 PK	138	/* Xilinx uartlite */
238b8721 PK	139	#define PORT_UARTLITE 74
73e55cb3	140
194de561 BW	141	/* Blackfin bf5xx */
	142	#define PORT_BFIN 75
	143
2c7ee6ab AV	144	/* Micrel KS8695 */
	145	#define PORT_KS8695 76
	146
b45d5279 MR	147	/* Broadcom SB1250, etc. SOC */
	148	#define PORT_SB1250_DUART 77
	149
f0c15f48 GU	150	/* Freescale ColdFire */
	151	#define PORT_MCF 78
	152
2f351741 BW	153	/* Blackfin SPORT */
2f351741 BW	154	#define PORT_BFIN_SPORT 79
2c7ee6ab	155
ef3d5347 DH	156	/* MN10300 on-chip UART numbers */
	157	#define PORT_MN10300 80
	158	#define PORT_MN10300_CTS 81
	159
2f351741 BW	160	#define PORT_SC26XX 82
2f351741 BW	161
1a22f08d YS	162	/* SH-SCI */
	163	#define PORT_SCIFA 83
	164
b690ace5 BD	165	#define PORT_S3C6400 84
b690ace5 BD	166
5886188d BK	167	/* NWPSERIAL */
	168	#define PORT_NWPSERIAL 85
	169
1dcb884c CP	170	/* MAX3100 */
	171	#define PORT_MAX3100 86
	172
34aec591 RR	173	/* Timberdale UART */
	174	#define PORT_TIMBUART 87
	175
04896a77 RL	176	/* Qualcomm MSM SoCs */
	177	#define PORT_MSM 88
	178
9fcd66e5 MB	179	/* BCM63xx family SoCs */
	180	#define PORT_BCM63XX 89
	181
d4ac42a5 KG	182	/* Aeroflex Gaisler GRLIB APBUART */
	183	#define PORT_APBUART 90
	184
5bcd6010 TK	185	/* Altera UARTs */
5bcd6010 TK	186	#define PORT_ALTERA_JTAGUART 91
6b7d8f8b	187	#define PORT_ALTERA_UART 92
5bcd6010	188
61fd1526 AC	189	/* MAX3107 */
	190	#define PORT_MAX3107 94
	191
	192
1da177e4 LT	193	#ifdef __KERNEL__
1da177e4 LT	194
661f83a6	195	#include <linux/compiler.h>
1da177e4 LT	196	#include <linux/interrupt.h>
	197	#include <linux/circ_buf.h>
	198	#include <linux/spinlock.h>
	199	#include <linux/sched.h>
	200	#include <linux/tty.h>
e2862f6a	201	#include <linux/mutex.h>
b11115c1	202	#include <linux/sysrq.h>
1da177e4 LT	203
1da177e4 LT	204	struct uart_port;
1da177e4 LT	205	struct serial_struct;
	206	struct device;
	207
	208	/*
	209	* This structure describes all the operations that can be
	210	* done on the physical hardware.
	211	*/
	212	struct uart_ops {
	213	unsigned int (tx_empty)(struct uart_port );
	214	void (set_mctrl)(struct uart_port , unsigned int mctrl);
	215	unsigned int (get_mctrl)(struct uart_port );
b129a8cc RK	216	void (stop_tx)(struct uart_port );
b129a8cc RK	217	void (start_tx)(struct uart_port );
1da177e4 LT	218	void (send_xchar)(struct uart_port , char ch);
	219	void (stop_rx)(struct uart_port );
	220	void (enable_ms)(struct uart_port );
	221	void (break_ctl)(struct uart_port , int ctl);
	222	int (startup)(struct uart_port );
	223	void (shutdown)(struct uart_port );
6bb0e3a5	224	void (flush_buffer)(struct uart_port );
606d099c AC	225	void (set_termios)(struct uart_port , struct ktermios *new,
606d099c AC	226	struct ktermios *old);
d87d9b7d	227	void (set_ldisc)(struct uart_port , int new);
1da177e4 LT	228	void (pm)(struct uart_port , unsigned int state,
	229	unsigned int oldstate);
	230	int (set_wake)(struct uart_port , unsigned int state);
	231
	232	/*
	233	* Return a string describing the type of the port
	234	*/
	235	const char (type)(struct uart_port *);
	236
	237	/*
	238	* Release IO and memory resources used by the port.
	239	* This includes iounmap if necessary.
	240	*/
	241	void (release_port)(struct uart_port );
	242
	243	/*
	244	* Request IO and memory resources used by the port.
	245	* This includes iomapping the port if necessary.
	246	*/
	247	int (request_port)(struct uart_port );
	248	void (config_port)(struct uart_port , int);
	249	int (verify_port)(struct uart_port , struct serial_struct *);
	250	int (ioctl)(struct uart_port , unsigned int, unsigned long);
f2d937f3 JW	251	#ifdef CONFIG_CONSOLE_POLL
	252	void (poll_put_char)(struct uart_port , unsigned char);
	253	int (poll_get_char)(struct uart_port );
	254	#endif
1da177e4 LT	255	};
1da177e4 LT	256
f5316b4a	257	#define NO_POLL_CHAR 0x00ff0000
1da177e4 LT	258	#define UART_CONFIG_TYPE (1 << 0)
	259	#define UART_CONFIG_IRQ (1 << 1)
	260
	261	struct uart_icount {
	262	__u32 cts;
	263	__u32 dsr;
	264	__u32 rng;
	265	__u32 dcd;
	266	__u32 rx;
	267	__u32 tx;
	268	__u32 frame;
	269	__u32 overrun;
	270	__u32 parity;
	271	__u32 brk;
	272	__u32 buf_overrun;
	273	};
	274
0077d45e RK	275	typedef unsigned int __bitwise__ upf_t;
0077d45e RK	276
1da177e4 LT	277	struct uart_port {
1da177e4 LT	278	spinlock_t lock; /* port lock */
0c8946d9	279	unsigned long iobase; /* in/out[bwl] */
1da177e4	280	unsigned char __iomem membase; / read/write[bwl] */
7d6a07d1 DD	281	unsigned int (serial_in)(struct uart_port , int);
7d6a07d1 DD	282	void (serial_out)(struct uart_port , int, int);
1da177e4	283	unsigned int irq; /* irq number */
1c2f0493	284	unsigned long irqflags; /* irq flags */
1da177e4	285	unsigned int uartclk; /* base uart clock */
947deee8	286	unsigned int fifosize; /* tx fifo size */
1da177e4 LT	287	unsigned char x_char; /* xon/xoff char */
	288	unsigned char regshift; /* reg offset shift */
	289	unsigned char iotype; /* io access style */
947deee8	290	unsigned char unused1;
1da177e4 LT	291
	292	#define UPIO_PORT (0)
	293	#define UPIO_HUB6 (1)
	294	#define UPIO_MEM (2)
	295	#define UPIO_MEM32 (3)
21c614a7	296	#define UPIO_AU (4) /* Au1x00 type IO */
3be91ec7	297	#define UPIO_TSI (5) /* Tsi108/109 type IO */
beab697a	298	#define UPIO_DWAPB (6) /* DesignWare APB UART */
bd71c182	299	#define UPIO_RM9000 (7) /* RM9000 type IO */
1da177e4 LT	300
	301	unsigned int read_status_mask; /* driver specific */
	302	unsigned int ignore_status_mask; /* driver specific */
ebd2c8f6	303	struct uart_state state; / pointer to parent state */
1da177e4 LT	304	struct uart_icount icount; /* statistics */
	305
	306	struct console cons; / struct console, if any */
06e82df0	307	#if defined(CONFIG_SERIAL_CORE_CONSOLE) \|\| defined(SUPPORT_SYSRQ)
1da177e4 LT	308	unsigned long sysrq; /* sysrq timeout */
	309	#endif
	310
0077d45e RK	311	upf_t flags;
	312
	313	#define UPF_FOURPORT ((__force upf_t) (1 << 1))
	314	#define UPF_SAK ((__force upf_t) (1 << 2))
	315	#define UPF_SPD_MASK ((__force upf_t) (0x1030))
	316	#define UPF_SPD_HI ((__force upf_t) (0x0010))
	317	#define UPF_SPD_VHI ((__force upf_t) (0x0020))
	318	#define UPF_SPD_CUST ((__force upf_t) (0x0030))
	319	#define UPF_SPD_SHI ((__force upf_t) (0x1000))
	320	#define UPF_SPD_WARP ((__force upf_t) (0x1010))
	321	#define UPF_SKIP_TEST ((__force upf_t) (1 << 6))
	322	#define UPF_AUTO_IRQ ((__force upf_t) (1 << 7))
	323	#define UPF_HARDPPS_CD ((__force upf_t) (1 << 11))
	324	#define UPF_LOW_LATENCY ((__force upf_t) (1 << 13))
	325	#define UPF_BUGGY_UART ((__force upf_t) (1 << 14))
b6adea33	326	#define UPF_NO_TXEN_TEST ((__force upf_t) (1 << 15))
0077d45e RK	327	#define UPF_MAGIC_MULTIPLIER ((__force upf_t) (1 << 16))
	328	#define UPF_CONS_FLOW ((__force upf_t) (1 << 23))
	329	#define UPF_SHARE_IRQ ((__force upf_t) (1 << 24))
8e23fcc8 DD	330	/* The exact UART type is known and should not be probed. */
8e23fcc8 DD	331	#define UPF_FIXED_TYPE ((__force upf_t) (1 << 27))
0077d45e	332	#define UPF_BOOT_AUTOCONF ((__force upf_t) (1 << 28))
abb4a239	333	#define UPF_FIXED_PORT ((__force upf_t) (1 << 29))
68ac64cd	334	#define UPF_DEAD ((__force upf_t) (1 << 30))
0077d45e RK	335	#define UPF_IOREMAP ((__force upf_t) (1 << 31))
	336
	337	#define UPF_CHANGE_MASK ((__force upf_t) (0x17fff))
	338	#define UPF_USR_MASK ((__force upf_t) (UPF_SPD_MASK\|UPF_LOW_LATENCY))
1da177e4 LT	339
	340	unsigned int mctrl; /* current modem ctrl settings */
	341	unsigned int timeout; /* character-based timeout */
	342	unsigned int type; /* port type */
ba899dbc	343	const struct uart_ops *ops;
1da177e4 LT	344	unsigned int custom_divisor;
1da177e4 LT	345	unsigned int line; /* port index */
4f640efb	346	resource_size_t mapbase; /* for ioremap */
1da177e4 LT	347	struct device dev; / parent device */
1da177e4 LT	348	unsigned char hub6; /* this should be in the 8250 driver */
b3b708fa GL	349	unsigned char suspended;
b3b708fa GL	350	unsigned char unused[2];
beab697a	351	void private_data; / generic platform data pointer */
1da177e4 LT	352	};
1da177e4 LT	353
ebd2c8f6 AC	354	/*
ebd2c8f6 AC	355	* This is the state information which is persistent across opens.
ebd2c8f6 AC	356	*/
ebd2c8f6 AC	357	struct uart_state {
df4f4dd4	358	struct tty_port port;
ebd2c8f6	359
ebd2c8f6	360	int pm_state;
1da177e4	361	struct circ_buf xmit;
1da177e4	362
1da177e4	363	struct tasklet_struct tlet;
ebd2c8f6	364	struct uart_port *uart_port;
f751928e AC	365	};
	366
	367	#define UART_XMIT_SIZE PAGE_SIZE
	368
	369
1da177e4 LT	370	/* number of characters left in xmit buffer before we ask for more */
	371	#define WAKEUP_CHARS 256
	372
	373	struct module;
	374	struct tty_driver;
	375
	376	struct uart_driver {
	377	struct module *owner;
	378	const char *driver_name;
	379	const char *dev_name;
1da177e4 LT	380	int major;
	381	int minor;
	382	int nr;
	383	struct console *cons;
	384
	385	/*
	386	* these are private; the low level driver should not
	387	* touch these; they should be initialised to NULL
	388	*/
	389	struct uart_state *state;
	390	struct tty_driver *tty_driver;
	391	};
	392
	393	void uart_write_wakeup(struct uart_port *port);
	394
	395	/*
	396	* Baud rate helpers.
	397	*/
	398	void uart_update_timeout(struct uart_port *port, unsigned int cflag,
	399	unsigned int baud);
606d099c AC	400	unsigned int uart_get_baud_rate(struct uart_port port, struct ktermios termios,
606d099c AC	401	struct ktermios *old, unsigned int min,
1da177e4 LT	402	unsigned int max);
	403	unsigned int uart_get_divisor(struct uart_port *port, unsigned int baud);
	404
	405	/*
	406	* Console helpers.
	407	*/
	408	struct uart_port uart_get_console(struct uart_port ports, int nr,
	409	struct console *c);
	410	void uart_parse_options(char options, int baud, int parity, int bits,
	411	int *flow);
	412	int uart_set_options(struct uart_port port, struct console co, int baud,
	413	int parity, int bits, int flow);
	414	struct tty_driver uart_console_device(struct console co, int *index);
d358788f RK	415	void uart_console_write(struct uart_port port, const char s,
	416	unsigned int count,
	417	void (putchar)(struct uart_port , int));
1da177e4 LT	418
	419	/*
	420	* Port/driver registration/removal
	421	*/
	422	int uart_register_driver(struct uart_driver *uart);
	423	void uart_unregister_driver(struct uart_driver *uart);
1da177e4 LT	424	int uart_add_one_port(struct uart_driver reg, struct uart_port port);
	425	int uart_remove_one_port(struct uart_driver reg, struct uart_port port);
	426	int uart_match_port(struct uart_port port1, struct uart_port port2);
	427
	428	/*
	429	* Power Management
	430	*/
	431	int uart_suspend_port(struct uart_driver reg, struct uart_port port);
	432	int uart_resume_port(struct uart_driver reg, struct uart_port port);
	433
	434	#define uart_circ_empty(circ) ((circ)->head == (circ)->tail)
	435	#define uart_circ_clear(circ) ((circ)->head = (circ)->tail = 0)
	436
	437	#define uart_circ_chars_pending(circ) \
	438	(CIRC_CNT((circ)->head, (circ)->tail, UART_XMIT_SIZE))
	439
	440	#define uart_circ_chars_free(circ) \
	441	(CIRC_SPACE((circ)->head, (circ)->tail, UART_XMIT_SIZE))
	442
f751928e AC	443	static inline int uart_tx_stopped(struct uart_port *port)
f751928e AC	444	{
ebd2c8f6	445	struct tty_struct *tty = port->state->port.tty;
f751928e AC	446	if(tty->stopped \|\| tty->hw_stopped)
	447	return 1;
	448	return 0;
	449	}
1da177e4 LT	450
	451	/*
	452	* The following are helper functions for the low level drivers.
	453	*/
1da177e4	454	static inline int
7d12e780	455	uart_handle_sysrq_char(struct uart_port *port, unsigned int ch)
1da177e4	456	{
93c37f29	457	#ifdef SUPPORT_SYSRQ
1da177e4 LT	458	if (port->sysrq) {
1da177e4 LT	459	if (ch && time_before(jiffies, port->sysrq)) {
ebd2c8f6	460	handle_sysrq(ch, port->state->port.tty);
1da177e4 LT	461	port->sysrq = 0;
	462	return 1;
	463	}
	464	port->sysrq = 0;
	465	}
93c37f29	466	#endif
1da177e4 LT	467	return 0;
1da177e4 LT	468	}
4e149184	469	#ifndef SUPPORT_SYSRQ
7d12e780	470	#define uart_handle_sysrq_char(port,ch) uart_handle_sysrq_char(port, 0)
4e149184	471	#endif
1da177e4 LT	472
	473	/*
	474	* We do the SysRQ and SAK checking like this...
	475	*/
	476	static inline int uart_handle_break(struct uart_port *port)
	477	{
ebd2c8f6	478	struct uart_state *state = port->state;
1da177e4 LT	479	#ifdef SUPPORT_SYSRQ
	480	if (port->cons && port->cons->index == port->line) {
	481	if (!port->sysrq) {
	482	port->sysrq = jiffies + HZ*5;
	483	return 1;
	484	}
	485	port->sysrq = 0;
	486	}
	487	#endif
27ae7a74	488	if (port->flags & UPF_SAK)
ebd2c8f6	489	do_SAK(state->port.tty);
1da177e4 LT	490	return 0;
	491	}
	492
	493	/**
	494	* uart_handle_dcd_change - handle a change of carrier detect state
1b9894f3	495	* @uport: uart_port structure for the open port
1da177e4 LT	496	* @status: new carrier detect status, nonzero if active
	497	*/
	498	static inline void
ccce6deb	499	uart_handle_dcd_change(struct uart_port *uport, unsigned int status)
1da177e4	500	{
ccce6deb AC	501	struct uart_state *state = uport->state;
ccce6deb AC	502	struct tty_port *port = &state->port;
a0880df0 RG	503	struct tty_ldisc *ld = tty_ldisc_ref(port->tty);
a0880df0 RG	504	struct timespec ts;
1da177e4	505
a0880df0 RG	506	if (ld && ld->ops->dcd_change)
a0880df0 RG	507	getnstimeofday(&ts);
1da177e4	508
a0880df0	509	uport->icount.dcd++;
1da177e4	510	#ifdef CONFIG_HARD_PPS
ccce6deb	511	if ((uport->flags & UPF_HARDPPS_CD) && status)
1da177e4 LT	512	hardpps();
	513	#endif
	514
ccce6deb	515	if (port->flags & ASYNC_CHECK_CD) {
1da177e4	516	if (status)
ccce6deb AC	517	wake_up_interruptible(&port->open_wait);
	518	else if (port->tty)
	519	tty_hangup(port->tty);
1da177e4	520	}
a0880df0 RG	521
	522	if (ld && ld->ops->dcd_change)
	523	ld->ops->dcd_change(port->tty, status, &ts);
	524	if (ld)
	525	tty_ldisc_deref(ld);
1da177e4 LT	526	}
	527
	528	/**
	529	* uart_handle_cts_change - handle a change of clear-to-send state
1b9894f3	530	* @uport: uart_port structure for the open port
1da177e4 LT	531	* @status: new clear to send status, nonzero if active
	532	*/
	533	static inline void
ccce6deb	534	uart_handle_cts_change(struct uart_port *uport, unsigned int status)
1da177e4	535	{
ccce6deb AC	536	struct tty_port *port = &uport->state->port;
ccce6deb AC	537	struct tty_struct *tty = port->tty;
1da177e4	538
ccce6deb	539	uport->icount.cts++;
1da177e4	540
ccce6deb	541	if (port->flags & ASYNC_CTS_FLOW) {
1da177e4 LT	542	if (tty->hw_stopped) {
	543	if (status) {
	544	tty->hw_stopped = 0;
ccce6deb AC	545	uport->ops->start_tx(uport);
ccce6deb AC	546	uart_write_wakeup(uport);
1da177e4 LT	547	}
	548	} else {
	549	if (!status) {
	550	tty->hw_stopped = 1;
ccce6deb	551	uport->ops->stop_tx(uport);
1da177e4 LT	552	}
	553	}
	554	}
	555	}
	556
05ab3014 RK	557	#include <linux/tty_flip.h>
	558
	559	static inline void
	560	uart_insert_char(struct uart_port *port, unsigned int status,
	561	unsigned int overrun, unsigned int ch, unsigned int flag)
	562	{
ebd2c8f6	563	struct tty_struct *tty = port->state->port.tty;
05ab3014 RK	564
	565	if ((status & port->ignore_status_mask & ~overrun) == 0)
	566	tty_insert_flip_char(tty, ch, flag);
	567
	568	/*
	569	* Overrun is special. Since it's reported immediately,
	570	* it doesn't affect the current character.
	571	*/
	572	if (status & ~port->ignore_status_mask & overrun)
	573	tty_insert_flip_char(tty, 0, TTY_OVERRUN);
	574	}
	575
1da177e4 LT	576	/*
	577	* UART_ENABLE_MS - determine if port should enable modem status irqs
	578	*/
	579	#define UART_ENABLE_MS(port,cflag) ((port)->flags & UPF_HARDPPS_CD \|\| \
	580	(cflag) & CRTSCTS \|\| \
	581	!((cflag) & CLOCAL))
	582
	583	#endif
	584
	585	#endif /* LINUX_SERIAL_CORE_H */