[linux-2.6-block.git] / include / linux / serial_core.h

/*
 *  linux/drivers/char/serial_core.h
 *
 *  Copyright (C) 2000 Deep Blue Solutions Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#ifndef LINUX_SERIAL_CORE_H
#define LINUX_SERIAL_CORE_H

#include <linux/serial.h>

/*
 * The type definitions.  These are from Ted Ts'o's serial.h
 */
#define PORT_UNKNOWN	0
#define PORT_8250	1
#define PORT_16450	2
#define PORT_16550	3
#define PORT_16550A	4
#define PORT_CIRRUS	5
#define PORT_16650	6
#define PORT_16650V2	7
#define PORT_16750	8
#define PORT_STARTECH	9
#define PORT_16C950	10
#define PORT_16654	11
#define PORT_16850	12
#define PORT_RSA	13
#define PORT_NS16550A	14
#define PORT_XSCALE	15
#define PORT_RM9000	16	/* PMC-Sierra RM9xxx internal UART */
#define PORT_OCTEON	17	/* Cavium OCTEON internal UART */
#define PORT_AR7	18	/* Texas Instruments AR7 internal UART */
#define PORT_U6_16550A	19	/* ST-Ericsson U6xxx internal UART */
#define PORT_TEGRA	20	/* NVIDIA Tegra internal UART */
#define PORT_XR17D15X	21	/* Exar XR17D15x UART */
#define PORT_MAX_8250	21	/* max port ID */

/*
 * ARM specific type numbers.  These are not currently guaranteed
 * to be implemented, and will change in the future.  These are
 * separate so any additions to the old serial.c that occur before
 * we are merged can be easily merged here.
 */
#define PORT_PXA	31
#define PORT_AMBA	32
#define PORT_CLPS711X	33
#define PORT_SA1100	34
#define PORT_UART00	35
#define PORT_21285	37

/* Sparc type numbers.  */
#define PORT_SUNZILOG	38
#define PORT_SUNSAB	39

/* DEC */
#define PORT_DZ		46
#define PORT_ZS		47

/* Parisc type numbers. */
#define PORT_MUX	48

/* Atmel AT91 / AT32 SoC */
#define PORT_ATMEL	49

/* Macintosh Zilog type numbers */
#define PORT_MAC_ZILOG	50	/* m68k : not yet implemented */
#define PORT_PMAC_ZILOG	51

/* SH-SCI */
#define PORT_SCI	52
#define PORT_SCIF	53
#define PORT_IRDA	54

/* Samsung S3C2410 SoC and derivatives thereof */
#define PORT_S3C2410    55

/* SGI IP22 aka Indy / Challenge S / Indigo 2 */
#define PORT_IP22ZILOG	56

/* Sharp LH7a40x -- an ARM9 SoC series */
#define PORT_LH7A40X	57

/* PPC CPM type number */
#define PORT_CPM        58

/* MPC52xx (and MPC512x) type numbers */
#define PORT_MPC52xx	59

/* IBM icom */
#define PORT_ICOM	60

/* Samsung S3C2440 SoC */
#define PORT_S3C2440	61

/* Motorola i.MX SoC */
#define PORT_IMX	62

/* Marvell MPSC */
#define PORT_MPSC	63

/* TXX9 type number */
#define PORT_TXX9	64

/* NEC VR4100 series SIU/DSIU */
#define PORT_VR41XX_SIU		65
#define PORT_VR41XX_DSIU	66

/* Samsung S3C2400 SoC */
#define PORT_S3C2400	67

/* M32R SIO */
#define PORT_M32R_SIO	68

/*Digi jsm */
#define PORT_JSM        69

#define PORT_PNX8XXX	70

/* Hilscher netx */
#define PORT_NETX	71

/* SUN4V Hypervisor Console */
#define PORT_SUNHV	72

#define PORT_S3C2412	73

/* Xilinx uartlite */
#define PORT_UARTLITE	74

/* Blackfin bf5xx */
#define PORT_BFIN	75

/* Micrel KS8695 */
#define PORT_KS8695	76

/* Broadcom SB1250, etc. SOC */
#define PORT_SB1250_DUART	77

/* Freescale ColdFire */
#define PORT_MCF	78

/* Blackfin SPORT */
#define PORT_BFIN_SPORT		79

/* MN10300 on-chip UART numbers */
#define PORT_MN10300		80
#define PORT_MN10300_CTS	81

#define PORT_SC26XX	82

/* SH-SCI */
#define PORT_SCIFA	83

#define PORT_S3C6400	84

/* NWPSERIAL */
#define PORT_NWPSERIAL	85

/* MAX3100 */
#define PORT_MAX3100    86

/* Timberdale UART */
#define PORT_TIMBUART	87

/* Qualcomm MSM SoCs */
#define PORT_MSM	88

/* BCM63xx family SoCs */
#define PORT_BCM63XX	89

/* Aeroflex Gaisler GRLIB APBUART */
#define PORT_APBUART    90

/* Altera UARTs */
#define PORT_ALTERA_JTAGUART	91
#define PORT_ALTERA_UART	92

/* SH-SCI */
#define PORT_SCIFB	93

/* MAX3107 */
#define PORT_MAX3107	94

/* High Speed UART for Medfield */
#define PORT_MFD	95

/* TI OMAP-UART */
#define PORT_OMAP	96

/* VIA VT8500 SoC */
#define PORT_VT8500	97

/* Xilinx PSS UART */
#define PORT_XUARTPS	98

/* Atheros AR933X SoC */
#define PORT_AR933X	99


#ifdef __KERNEL__

#include <linux/compiler.h>
#include <linux/interrupt.h>
#include <linux/circ_buf.h>
#include <linux/spinlock.h>
#include <linux/sched.h>
#include <linux/tty.h>
#include <linux/mutex.h>
#include <linux/sysrq.h>
#include <linux/pps_kernel.h>

struct uart_port;
struct serial_struct;
struct device;

/*
 * This structure describes all the operations that can be
 * done on the physical hardware.
 */
struct uart_ops {
	unsigned int	(*tx_empty)(struct uart_port *);
	void		(*set_mctrl)(struct uart_port *, unsigned int mctrl);
	unsigned int	(*get_mctrl)(struct uart_port *);
	void		(*stop_tx)(struct uart_port *);
	void		(*start_tx)(struct uart_port *);
	void		(*send_xchar)(struct uart_port *, char ch);
	void		(*stop_rx)(struct uart_port *);
	void		(*enable_ms)(struct uart_port *);
	void		(*break_ctl)(struct uart_port *, int ctl);
	int		(*startup)(struct uart_port *);
	void		(*shutdown)(struct uart_port *);
	void		(*flush_buffer)(struct uart_port *);
	void		(*set_termios)(struct uart_port *, struct ktermios *new,
				       struct ktermios *old);
	void		(*set_ldisc)(struct uart_port *, int new);
	void		(*pm)(struct uart_port *, unsigned int state,
			      unsigned int oldstate);
	int		(*set_wake)(struct uart_port *, unsigned int state);

	/*
	 * Return a string describing the type of the port
	 */
	const char *(*type)(struct uart_port *);

	/*
	 * Release IO and memory resources used by the port.
	 * This includes iounmap if necessary.
	 */
	void		(*release_port)(struct uart_port *);

	/*
	 * Request IO and memory resources used by the port.
	 * This includes iomapping the port if necessary.
	 */
	int		(*request_port)(struct uart_port *);
	void		(*config_port)(struct uart_port *, int);
	int		(*verify_port)(struct uart_port *, struct serial_struct *);
	int		(*ioctl)(struct uart_port *, unsigned int, unsigned long);
#ifdef CONFIG_CONSOLE_POLL
	void	(*poll_put_char)(struct uart_port *, unsigned char);
	int		(*poll_get_char)(struct uart_port *);
#endif
};

#define NO_POLL_CHAR		0x00ff0000
#define UART_CONFIG_TYPE	(1 << 0)
#define UART_CONFIG_IRQ		(1 << 1)

struct uart_icount {
	__u32	cts;
	__u32	dsr;
	__u32	rng;
	__u32	dcd;
	__u32	rx;
	__u32	tx;
	__u32	frame;
	__u32	overrun;
	__u32	parity;
	__u32	brk;
	__u32	buf_overrun;
};

typedef unsigned int __bitwise__ upf_t;

struct uart_port {
	spinlock_t		lock;			/* port lock */
	unsigned long		iobase;			/* in/out[bwl] */
	unsigned char __iomem	*membase;		/* read/write[bwl] */
	unsigned int		(*serial_in)(struct uart_port *, int);
	void			(*serial_out)(struct uart_port *, int, int);
	void			(*set_termios)(struct uart_port *,
				               struct ktermios *new,
				               struct ktermios *old);
	int			(*handle_irq)(struct uart_port *);
	void			(*pm)(struct uart_port *, unsigned int state,
				      unsigned int old);
	unsigned int		irq;			/* irq number */
	unsigned long		irqflags;		/* irq flags  */
	unsigned int		uartclk;		/* base uart clock */
	unsigned int		fifosize;		/* tx fifo size */
	unsigned char		x_char;			/* xon/xoff char */
	unsigned char		regshift;		/* reg offset shift */
	unsigned char		iotype;			/* io access style */
	unsigned char		unused1;

#define UPIO_PORT		(0)
#define UPIO_HUB6		(1)
#define UPIO_MEM		(2)
#define UPIO_MEM32		(3)
#define UPIO_AU			(4)			/* Au1x00 type IO */
#define UPIO_TSI		(5)			/* Tsi108/109 type IO */
#define UPIO_RM9000		(6)			/* RM9000 type IO */

	unsigned int		read_status_mask;	/* driver specific */
	unsigned int		ignore_status_mask;	/* driver specific */
	struct uart_state	*state;			/* pointer to parent state */
	struct uart_icount	icount;			/* statistics */

	struct console		*cons;			/* struct console, if any */
#if defined(CONFIG_SERIAL_CORE_CONSOLE) || defined(SUPPORT_SYSRQ)
	unsigned long		sysrq;			/* sysrq timeout */
#endif

	upf_t			flags;

#define UPF_FOURPORT		((__force upf_t) (1 << 1))
#define UPF_SAK			((__force upf_t) (1 << 2))
#define UPF_SPD_MASK		((__force upf_t) (0x1030))
#define UPF_SPD_HI		((__force upf_t) (0x0010))
#define UPF_SPD_VHI		((__force upf_t) (0x0020))
#define UPF_SPD_CUST		((__force upf_t) (0x0030))
#define UPF_SPD_SHI		((__force upf_t) (0x1000))
#define UPF_SPD_WARP		((__force upf_t) (0x1010))
#define UPF_SKIP_TEST		((__force upf_t) (1 << 6))
#define UPF_AUTO_IRQ		((__force upf_t) (1 << 7))
#define UPF_HARDPPS_CD		((__force upf_t) (1 << 11))
#define UPF_LOW_LATENCY		((__force upf_t) (1 << 13))
#define UPF_BUGGY_UART		((__force upf_t) (1 << 14))
#define UPF_NO_TXEN_TEST	((__force upf_t) (1 << 15))
#define UPF_MAGIC_MULTIPLIER	((__force upf_t) (1 << 16))
#define UPF_CONS_FLOW		((__force upf_t) (1 << 23))
#define UPF_SHARE_IRQ		((__force upf_t) (1 << 24))
#define UPF_EXAR_EFR		((__force upf_t) (1 << 25))
#define UPF_IIR_ONCE		((__force upf_t) (1 << 26))
/* The exact UART type is known and should not be probed.  */
#define UPF_FIXED_TYPE		((__force upf_t) (1 << 27))
#define UPF_BOOT_AUTOCONF	((__force upf_t) (1 << 28))
#define UPF_FIXED_PORT		((__force upf_t) (1 << 29))
#define UPF_DEAD		((__force upf_t) (1 << 30))
#define UPF_IOREMAP		((__force upf_t) (1 << 31))

#define UPF_CHANGE_MASK		((__force upf_t) (0x17fff))
#define UPF_USR_MASK		((__force upf_t) (UPF_SPD_MASK|UPF_LOW_LATENCY))

	unsigned int		mctrl;			/* current modem ctrl settings */
	unsigned int		timeout;		/* character-based timeout */
	unsigned int		type;			/* port type */
	const struct uart_ops	*ops;
	unsigned int		custom_divisor;
	unsigned int		line;			/* port index */
	resource_size_t		mapbase;		/* for ioremap */
	struct device		*dev;			/* parent device */
	unsigned char		hub6;			/* this should be in the 8250 driver */
	unsigned char		suspended;
	unsigned char		irq_wake;
	unsigned char		unused[2];
	void			*private_data;		/* generic platform data pointer */
};

/*
 * This is the state information which is persistent across opens.
 */
struct uart_state {
	struct tty_port		port;

	int			pm_state;
	struct circ_buf		xmit;

	struct uart_port	*uart_port;
};

#define UART_XMIT_SIZE	PAGE_SIZE


/* number of characters left in xmit buffer before we ask for more */
#define WAKEUP_CHARS		256

struct module;
struct tty_driver;

struct uart_driver {
	struct module		*owner;
	const char		*driver_name;
	const char		*dev_name;
	int			 major;
	int			 minor;
	int			 nr;
	struct console		*cons;

	/*
	 * these are private; the low level driver should not
	 * touch these; they should be initialised to NULL
	 */
	struct uart_state	*state;
	struct tty_driver	*tty_driver;
};

void uart_write_wakeup(struct uart_port *port);

/*
 * Baud rate helpers.
 */
void uart_update_timeout(struct uart_port *port, unsigned int cflag,
			 unsigned int baud);
unsigned int uart_get_baud_rate(struct uart_port *port, struct ktermios *termios,
				struct ktermios *old, unsigned int min,
				unsigned int max);
unsigned int uart_get_divisor(struct uart_port *port, unsigned int baud);

/* Base timer interval for polling */
static inline int uart_poll_timeout(struct uart_port *port)
{
	int timeout = port->timeout;

	return timeout > 6 ? (timeout / 2 - 2) : 1;
}

/*
 * Console helpers.
 */
struct uart_port *uart_get_console(struct uart_port *ports, int nr,
				   struct console *c);
void uart_parse_options(char *options, int *baud, int *parity, int *bits,
			int *flow);
int uart_set_options(struct uart_port *port, struct console *co, int baud,
		     int parity, int bits, int flow);
struct tty_driver *uart_console_device(struct console *co, int *index);
void uart_console_write(struct uart_port *port, const char *s,
			unsigned int count,
			void (*putchar)(struct uart_port *, int));

/*
 * Port/driver registration/removal
 */
int uart_register_driver(struct uart_driver *uart);
void uart_unregister_driver(struct uart_driver *uart);
int uart_add_one_port(struct uart_driver *reg, struct uart_port *port);
int uart_remove_one_port(struct uart_driver *reg, struct uart_port *port);
int uart_match_port(struct uart_port *port1, struct uart_port *port2);

/*
 * Power Management
 */
int uart_suspend_port(struct uart_driver *reg, struct uart_port *port);
int uart_resume_port(struct uart_driver *reg, struct uart_port *port);

#define uart_circ_empty(circ)		((circ)->head == (circ)->tail)
#define uart_circ_clear(circ)		((circ)->head = (circ)->tail = 0)

#define uart_circ_chars_pending(circ)	\
	(CIRC_CNT((circ)->head, (circ)->tail, UART_XMIT_SIZE))

#define uart_circ_chars_free(circ)	\
	(CIRC_SPACE((circ)->head, (circ)->tail, UART_XMIT_SIZE))

static inline int uart_tx_stopped(struct uart_port *port)
{
	struct tty_struct *tty = port->state->port.tty;
	if(tty->stopped || tty->hw_stopped)
		return 1;
	return 0;
}

/*
 * The following are helper functions for the low level drivers.
 */

extern void uart_handle_dcd_change(struct uart_port *uport,
		unsigned int status);
extern void uart_handle_cts_change(struct uart_port *uport,
		unsigned int status);

extern void uart_insert_char(struct uart_port *port, unsigned int status,
		 unsigned int overrun, unsigned int ch, unsigned int flag);

#ifdef SUPPORT_SYSRQ
static inline int
uart_handle_sysrq_char(struct uart_port *port, unsigned int ch)
{
	if (port->sysrq) {
		if (ch && time_before(jiffies, port->sysrq)) {
			handle_sysrq(ch);
			port->sysrq = 0;
			return 1;
		}
		port->sysrq = 0;
	}
	return 0;
}
#else
#define uart_handle_sysrq_char(port,ch) ({ (void)port; 0; })
#endif

/*
 * We do the SysRQ and SAK checking like this...
 */
static inline int uart_handle_break(struct uart_port *port)
{
	struct uart_state *state = port->state;
#ifdef SUPPORT_SYSRQ
	if (port->cons && port->cons->index == port->line) {
		if (!port->sysrq) {
			port->sysrq = jiffies + HZ*5;
			return 1;
		}
		port->sysrq = 0;
	}
#endif
	if (port->flags & UPF_SAK)
		do_SAK(state->port.tty);
	return 0;
}

/*
 *	UART_ENABLE_MS - determine if port should enable modem status irqs
 */
#define UART_ENABLE_MS(port,cflag)	((port)->flags & UPF_HARDPPS_CD || \
					 (cflag) & CRTSCTS || \
					 !((cflag) & CLOCAL))

#endif

#endif /* LINUX_SERIAL_CORE_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/drivers/char/serial_core.h
	3	*
	4	* Copyright (C) 2000 Deep Blue Solutions Ltd.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#ifndef LINUX_SERIAL_CORE_H
	21	#define LINUX_SERIAL_CORE_H
	22
ccce6deb AC	23	#include <linux/serial.h>
ccce6deb AC	24
1da177e4 LT	25	/*
	26	* The type definitions. These are from Ted Ts'o's serial.h
	27	*/
	28	#define PORT_UNKNOWN 0
	29	#define PORT_8250 1
	30	#define PORT_16450 2
	31	#define PORT_16550 3
	32	#define PORT_16550A 4
	33	#define PORT_CIRRUS 5
	34	#define PORT_16650 6
	35	#define PORT_16650V2 7
	36	#define PORT_16750 8
	37	#define PORT_STARTECH 9
	38	#define PORT_16C950 10
	39	#define PORT_16654 11
	40	#define PORT_16850 12
	41	#define PORT_RSA 13
	42	#define PORT_NS16550A 14
	43	#define PORT_XSCALE 15
bd71c182	44	#define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */
6b06f191	45	#define PORT_OCTEON 17 /* Cavium OCTEON internal UART */
08e0992f	46	#define PORT_AR7 18 /* Texas Instruments AR7 internal UART */
71cad055	47	#define PORT_U6_16550A 19 /* ST-Ericsson U6xxx internal UART */
4539c24f	48	#define PORT_TEGRA 20 /* NVIDIA Tegra internal UART */
06315348 SH	49	#define PORT_XR17D15X 21 /* Exar XR17D15x UART */
06315348 SH	50	#define PORT_MAX_8250 21 /* max port ID */
1da177e4 LT	51
	52	/*
	53	* ARM specific type numbers. These are not currently guaranteed
	54	* to be implemented, and will change in the future. These are
	55	* separate so any additions to the old serial.c that occur before
	56	* we are merged can be easily merged here.
	57	*/
	58	#define PORT_PXA 31
	59	#define PORT_AMBA 32
	60	#define PORT_CLPS711X 33
	61	#define PORT_SA1100 34
	62	#define PORT_UART00 35
	63	#define PORT_21285 37
	64
	65	/* Sparc type numbers. */
	66	#define PORT_SUNZILOG 38
	67	#define PORT_SUNSAB 39
	68
8b4a4080 MR	69	/* DEC */
	70	#define PORT_DZ 46
	71	#define PORT_ZS 47
1da177e4 LT	72
	73	/* Parisc type numbers. */
	74	#define PORT_MUX 48
	75
9ab4f88b HS	76	/* Atmel AT91 / AT32 SoC */
9ab4f88b HS	77	#define PORT_ATMEL 49
1e6c9c28	78
1da177e4 LT	79	/* Macintosh Zilog type numbers */
	80	#define PORT_MAC_ZILOG 50 /* m68k : not yet implemented */
	81	#define PORT_PMAC_ZILOG 51
	82
	83	/* SH-SCI */
	84	#define PORT_SCI 52
	85	#define PORT_SCIF 53
	86	#define PORT_IRDA 54
	87
	88	/* Samsung S3C2410 SoC and derivatives thereof */
	89	#define PORT_S3C2410 55
	90
	91	/* SGI IP22 aka Indy / Challenge S / Indigo 2 */
	92	#define PORT_IP22ZILOG 56
	93
	94	/* Sharp LH7a40x -- an ARM9 SoC series */
	95	#define PORT_LH7A40X 57
	96
	97	/* PPC CPM type number */
	98	#define PORT_CPM 58
	99
e44dcb6c	100	/* MPC52xx (and MPC512x) type numbers */
1da177e4 LT	101	#define PORT_MPC52xx 59
	102
	103	/* IBM icom */
	104	#define PORT_ICOM 60
	105
	106	/* Samsung S3C2440 SoC */
	107	#define PORT_S3C2440 61
	108
	109	/* Motorola i.MX SoC */
	110	#define PORT_IMX 62
	111
	112	/* Marvell MPSC */
	113	#define PORT_MPSC 63
	114
	115	/* TXX9 type number */
e5c2d749	116	#define PORT_TXX9 64
1da177e4 LT	117
	118	/* NEC VR4100 series SIU/DSIU */
	119	#define PORT_VR41XX_SIU 65
	120	#define PORT_VR41XX_DSIU 66
	121
	122	/* Samsung S3C2400 SoC */
	123	#define PORT_S3C2400 67
	124
	125	/* M32R SIO */
	126	#define PORT_M32R_SIO 68
	127
	128	/Digi jsm /
913ade51 RK	129	#define PORT_JSM 69
913ade51 RK	130
e6fa0ba3	131	#define PORT_PNX8XXX 70
1da177e4	132
f5417612 SH	133	/* Hilscher netx */
	134	#define PORT_NETX 71
	135
02fd473b DM	136	/* SUN4V Hypervisor Console */
	137	#define PORT_SUNHV 72
	138
73e55cb3 BD	139	#define PORT_S3C2412 73
73e55cb3 BD	140
238b8721 PK	141	/* Xilinx uartlite */
238b8721 PK	142	#define PORT_UARTLITE 74
73e55cb3	143
194de561 BW	144	/* Blackfin bf5xx */
	145	#define PORT_BFIN 75
	146
2c7ee6ab AV	147	/* Micrel KS8695 */
	148	#define PORT_KS8695 76
	149
b45d5279 MR	150	/* Broadcom SB1250, etc. SOC */
	151	#define PORT_SB1250_DUART 77
	152
f0c15f48 GU	153	/* Freescale ColdFire */
	154	#define PORT_MCF 78
	155
2f351741 BW	156	/* Blackfin SPORT */
2f351741 BW	157	#define PORT_BFIN_SPORT 79
2c7ee6ab	158
ef3d5347 DH	159	/* MN10300 on-chip UART numbers */
	160	#define PORT_MN10300 80
	161	#define PORT_MN10300_CTS 81
	162
2f351741 BW	163	#define PORT_SC26XX 82
2f351741 BW	164
1a22f08d YS	165	/* SH-SCI */
	166	#define PORT_SCIFA 83
	167
b690ace5 BD	168	#define PORT_S3C6400 84
b690ace5 BD	169
5886188d BK	170	/* NWPSERIAL */
	171	#define PORT_NWPSERIAL 85
	172
1dcb884c CP	173	/* MAX3100 */
	174	#define PORT_MAX3100 86
	175
34aec591 RR	176	/* Timberdale UART */
	177	#define PORT_TIMBUART 87
	178
04896a77 RL	179	/* Qualcomm MSM SoCs */
	180	#define PORT_MSM 88
	181
9fcd66e5 MB	182	/* BCM63xx family SoCs */
	183	#define PORT_BCM63XX 89
	184
d4ac42a5 KG	185	/* Aeroflex Gaisler GRLIB APBUART */
	186	#define PORT_APBUART 90
	187
5bcd6010 TK	188	/* Altera UARTs */
5bcd6010 TK	189	#define PORT_ALTERA_JTAGUART 91
6b7d8f8b	190	#define PORT_ALTERA_UART 92
5bcd6010	191
75b93489 GL	192	/* SH-SCI */
	193	#define PORT_SCIFB 93
	194
61fd1526 AC	195	/* MAX3107 */
	196	#define PORT_MAX3107 94
	197
d843fc6e FT	198	/* High Speed UART for Medfield */
d843fc6e FT	199	#define PORT_MFD 95
61fd1526	200
b612633b G	201	/* TI OMAP-UART */
	202	#define PORT_OMAP 96
	203
304e1266 AC	204	/* VIA VT8500 SoC */
	205	#define PORT_VT8500 97
	206
61ec9016 JL	207	/* Xilinx PSS UART */
	208	#define PORT_XUARTPS 98
	209
d57f341b GJ	210	/* Atheros AR933X SoC */
	211	#define PORT_AR933X 99
	212
	213
1da177e4 LT	214	#ifdef __KERNEL__
1da177e4 LT	215
661f83a6	216	#include <linux/compiler.h>
1da177e4 LT	217	#include <linux/interrupt.h>
	218	#include <linux/circ_buf.h>
	219	#include <linux/spinlock.h>
	220	#include <linux/sched.h>
	221	#include <linux/tty.h>
e2862f6a	222	#include <linux/mutex.h>
b11115c1	223	#include <linux/sysrq.h>
6f4229b5	224	#include <linux/pps_kernel.h>
1da177e4 LT	225
1da177e4 LT	226	struct uart_port;
1da177e4 LT	227	struct serial_struct;
	228	struct device;
	229
	230	/*
	231	* This structure describes all the operations that can be
	232	* done on the physical hardware.
	233	*/
	234	struct uart_ops {
	235	unsigned int (tx_empty)(struct uart_port );
	236	void (set_mctrl)(struct uart_port , unsigned int mctrl);
	237	unsigned int (get_mctrl)(struct uart_port );
b129a8cc RK	238	void (stop_tx)(struct uart_port );
b129a8cc RK	239	void (start_tx)(struct uart_port );
1da177e4 LT	240	void (send_xchar)(struct uart_port , char ch);
	241	void (stop_rx)(struct uart_port );
	242	void (enable_ms)(struct uart_port );
	243	void (break_ctl)(struct uart_port , int ctl);
	244	int (startup)(struct uart_port );
	245	void (shutdown)(struct uart_port );
6bb0e3a5	246	void (flush_buffer)(struct uart_port );
606d099c AC	247	void (set_termios)(struct uart_port , struct ktermios *new,
606d099c AC	248	struct ktermios *old);
d87d9b7d	249	void (set_ldisc)(struct uart_port , int new);
1da177e4 LT	250	void (pm)(struct uart_port , unsigned int state,
	251	unsigned int oldstate);
	252	int (set_wake)(struct uart_port , unsigned int state);
	253
	254	/*
	255	* Return a string describing the type of the port
	256	*/
	257	const char (type)(struct uart_port *);
	258
	259	/*
	260	* Release IO and memory resources used by the port.
	261	* This includes iounmap if necessary.
	262	*/
	263	void (release_port)(struct uart_port );
	264
	265	/*
	266	* Request IO and memory resources used by the port.
	267	* This includes iomapping the port if necessary.
	268	*/
	269	int (request_port)(struct uart_port );
	270	void (config_port)(struct uart_port , int);
	271	int (verify_port)(struct uart_port , struct serial_struct *);
	272	int (ioctl)(struct uart_port , unsigned int, unsigned long);
f2d937f3 JW	273	#ifdef CONFIG_CONSOLE_POLL
	274	void (poll_put_char)(struct uart_port , unsigned char);
	275	int (poll_get_char)(struct uart_port );
	276	#endif
1da177e4 LT	277	};
1da177e4 LT	278
f5316b4a	279	#define NO_POLL_CHAR 0x00ff0000
1da177e4 LT	280	#define UART_CONFIG_TYPE (1 << 0)
	281	#define UART_CONFIG_IRQ (1 << 1)
	282
	283	struct uart_icount {
	284	__u32 cts;
	285	__u32 dsr;
	286	__u32 rng;
	287	__u32 dcd;
	288	__u32 rx;
	289	__u32 tx;
	290	__u32 frame;
	291	__u32 overrun;
	292	__u32 parity;
	293	__u32 brk;
	294	__u32 buf_overrun;
	295	};
	296
0077d45e RK	297	typedef unsigned int __bitwise__ upf_t;
0077d45e RK	298
1da177e4 LT	299	struct uart_port {
1da177e4 LT	300	spinlock_t lock; /* port lock */
0c8946d9	301	unsigned long iobase; /* in/out[bwl] */
1da177e4	302	unsigned char __iomem membase; / read/write[bwl] */
7d6a07d1 DD	303	unsigned int (serial_in)(struct uart_port , int);
7d6a07d1 DD	304	void (serial_out)(struct uart_port , int, int);
235dae5d PL	305	void (set_termios)(struct uart_port ,
	306	struct ktermios *new,
	307	struct ktermios *old);
a74036f5	308	int (handle_irq)(struct uart_port );
c161afe9 ML	309	void (pm)(struct uart_port , unsigned int state,
c161afe9 ML	310	unsigned int old);
1da177e4	311	unsigned int irq; /* irq number */
1c2f0493	312	unsigned long irqflags; /* irq flags */
1da177e4	313	unsigned int uartclk; /* base uart clock */
947deee8	314	unsigned int fifosize; /* tx fifo size */
1da177e4 LT	315	unsigned char x_char; /* xon/xoff char */
	316	unsigned char regshift; /* reg offset shift */
	317	unsigned char iotype; /* io access style */
947deee8	318	unsigned char unused1;
1da177e4 LT	319
	320	#define UPIO_PORT (0)
	321	#define UPIO_HUB6 (1)
	322	#define UPIO_MEM (2)
	323	#define UPIO_MEM32 (3)
21c614a7	324	#define UPIO_AU (4) /* Au1x00 type IO */
3be91ec7	325	#define UPIO_TSI (5) /* Tsi108/109 type IO */
4834d028	326	#define UPIO_RM9000 (6) /* RM9000 type IO */
1da177e4 LT	327
	328	unsigned int read_status_mask; /* driver specific */
	329	unsigned int ignore_status_mask; /* driver specific */
ebd2c8f6	330	struct uart_state state; / pointer to parent state */
1da177e4 LT	331	struct uart_icount icount; /* statistics */
	332
	333	struct console cons; / struct console, if any */
06e82df0	334	#if defined(CONFIG_SERIAL_CORE_CONSOLE) \|\| defined(SUPPORT_SYSRQ)
1da177e4 LT	335	unsigned long sysrq; /* sysrq timeout */
	336	#endif
	337
0077d45e RK	338	upf_t flags;
	339
	340	#define UPF_FOURPORT ((__force upf_t) (1 << 1))
	341	#define UPF_SAK ((__force upf_t) (1 << 2))
	342	#define UPF_SPD_MASK ((__force upf_t) (0x1030))
	343	#define UPF_SPD_HI ((__force upf_t) (0x0010))
	344	#define UPF_SPD_VHI ((__force upf_t) (0x0020))
	345	#define UPF_SPD_CUST ((__force upf_t) (0x0030))
	346	#define UPF_SPD_SHI ((__force upf_t) (0x1000))
	347	#define UPF_SPD_WARP ((__force upf_t) (0x1010))
	348	#define UPF_SKIP_TEST ((__force upf_t) (1 << 6))
	349	#define UPF_AUTO_IRQ ((__force upf_t) (1 << 7))
	350	#define UPF_HARDPPS_CD ((__force upf_t) (1 << 11))
	351	#define UPF_LOW_LATENCY ((__force upf_t) (1 << 13))
	352	#define UPF_BUGGY_UART ((__force upf_t) (1 << 14))
b6adea33	353	#define UPF_NO_TXEN_TEST ((__force upf_t) (1 << 15))
0077d45e RK	354	#define UPF_MAGIC_MULTIPLIER ((__force upf_t) (1 << 16))
	355	#define UPF_CONS_FLOW ((__force upf_t) (1 << 23))
	356	#define UPF_SHARE_IRQ ((__force upf_t) (1 << 24))
06315348	357	#define UPF_EXAR_EFR ((__force upf_t) (1 << 25))
448ac154	358	#define UPF_IIR_ONCE ((__force upf_t) (1 << 26))
8e23fcc8 DD	359	/* The exact UART type is known and should not be probed. */
8e23fcc8 DD	360	#define UPF_FIXED_TYPE ((__force upf_t) (1 << 27))
0077d45e	361	#define UPF_BOOT_AUTOCONF ((__force upf_t) (1 << 28))
abb4a239	362	#define UPF_FIXED_PORT ((__force upf_t) (1 << 29))
68ac64cd	363	#define UPF_DEAD ((__force upf_t) (1 << 30))
0077d45e RK	364	#define UPF_IOREMAP ((__force upf_t) (1 << 31))
	365
	366	#define UPF_CHANGE_MASK ((__force upf_t) (0x17fff))
	367	#define UPF_USR_MASK ((__force upf_t) (UPF_SPD_MASK\|UPF_LOW_LATENCY))
1da177e4 LT	368
	369	unsigned int mctrl; /* current modem ctrl settings */
	370	unsigned int timeout; /* character-based timeout */
	371	unsigned int type; /* port type */
ba899dbc	372	const struct uart_ops *ops;
1da177e4 LT	373	unsigned int custom_divisor;
1da177e4 LT	374	unsigned int line; /* port index */
4f640efb	375	resource_size_t mapbase; /* for ioremap */
1da177e4 LT	376	struct device dev; / parent device */
1da177e4 LT	377	unsigned char hub6; /* this should be in the 8250 driver */
b3b708fa	378	unsigned char suspended;
3f960dbb	379	unsigned char irq_wake;
b3b708fa	380	unsigned char unused[2];
beab697a	381	void private_data; / generic platform data pointer */
1da177e4 LT	382	};
1da177e4 LT	383
ebd2c8f6 AC	384	/*
ebd2c8f6 AC	385	* This is the state information which is persistent across opens.
ebd2c8f6 AC	386	*/
ebd2c8f6 AC	387	struct uart_state {
df4f4dd4	388	struct tty_port port;
ebd2c8f6	389
ebd2c8f6	390	int pm_state;
1da177e4	391	struct circ_buf xmit;
1da177e4	392
ebd2c8f6	393	struct uart_port *uart_port;
f751928e AC	394	};
	395
	396	#define UART_XMIT_SIZE PAGE_SIZE
	397
	398
1da177e4 LT	399	/* number of characters left in xmit buffer before we ask for more */
	400	#define WAKEUP_CHARS 256
	401
	402	struct module;
	403	struct tty_driver;
	404
	405	struct uart_driver {
	406	struct module *owner;
	407	const char *driver_name;
	408	const char *dev_name;
1da177e4 LT	409	int major;
	410	int minor;
	411	int nr;
	412	struct console *cons;
	413
	414	/*
	415	* these are private; the low level driver should not
	416	* touch these; they should be initialised to NULL
	417	*/
	418	struct uart_state *state;
	419	struct tty_driver *tty_driver;
	420	};
	421
	422	void uart_write_wakeup(struct uart_port *port);
	423
	424	/*
	425	* Baud rate helpers.
	426	*/
	427	void uart_update_timeout(struct uart_port *port, unsigned int cflag,
	428	unsigned int baud);
606d099c AC	429	unsigned int uart_get_baud_rate(struct uart_port port, struct ktermios termios,
606d099c AC	430	struct ktermios *old, unsigned int min,
1da177e4 LT	431	unsigned int max);
	432	unsigned int uart_get_divisor(struct uart_port *port, unsigned int baud);
	433
54381067 AV	434	/* Base timer interval for polling */
	435	static inline int uart_poll_timeout(struct uart_port *port)
	436	{
	437	int timeout = port->timeout;
	438
	439	return timeout > 6 ? (timeout / 2 - 2) : 1;
	440	}
	441
1da177e4 LT	442	/*
	443	* Console helpers.
	444	*/
	445	struct uart_port uart_get_console(struct uart_port ports, int nr,
	446	struct console *c);
	447	void uart_parse_options(char options, int baud, int parity, int bits,
	448	int *flow);
	449	int uart_set_options(struct uart_port port, struct console co, int baud,
	450	int parity, int bits, int flow);
	451	struct tty_driver uart_console_device(struct console co, int *index);
d358788f RK	452	void uart_console_write(struct uart_port port, const char s,
	453	unsigned int count,
	454	void (putchar)(struct uart_port , int));
1da177e4 LT	455
	456	/*
	457	* Port/driver registration/removal
	458	*/
	459	int uart_register_driver(struct uart_driver *uart);
	460	void uart_unregister_driver(struct uart_driver *uart);
1da177e4 LT	461	int uart_add_one_port(struct uart_driver reg, struct uart_port port);
	462	int uart_remove_one_port(struct uart_driver reg, struct uart_port port);
	463	int uart_match_port(struct uart_port port1, struct uart_port port2);
	464
	465	/*
	466	* Power Management
	467	*/
	468	int uart_suspend_port(struct uart_driver reg, struct uart_port port);
	469	int uart_resume_port(struct uart_driver reg, struct uart_port port);
	470
	471	#define uart_circ_empty(circ) ((circ)->head == (circ)->tail)
	472	#define uart_circ_clear(circ) ((circ)->head = (circ)->tail = 0)
	473
	474	#define uart_circ_chars_pending(circ) \
	475	(CIRC_CNT((circ)->head, (circ)->tail, UART_XMIT_SIZE))
	476
	477	#define uart_circ_chars_free(circ) \
	478	(CIRC_SPACE((circ)->head, (circ)->tail, UART_XMIT_SIZE))
	479
f751928e AC	480	static inline int uart_tx_stopped(struct uart_port *port)
f751928e AC	481	{
ebd2c8f6	482	struct tty_struct *tty = port->state->port.tty;
f751928e AC	483	if(tty->stopped \|\| tty->hw_stopped)
	484	return 1;
	485	return 0;
	486	}
1da177e4 LT	487
	488	/*
	489	* The following are helper functions for the low level drivers.
	490	*/
027d7dac JS	491
	492	extern void uart_handle_dcd_change(struct uart_port *uport,
	493	unsigned int status);
	494	extern void uart_handle_cts_change(struct uart_port *uport,
	495	unsigned int status);
	496
	497	extern void uart_insert_char(struct uart_port *port, unsigned int status,
	498	unsigned int overrun, unsigned int ch, unsigned int flag);
	499
	500	#ifdef SUPPORT_SYSRQ
1da177e4	501	static inline int
7d12e780	502	uart_handle_sysrq_char(struct uart_port *port, unsigned int ch)
1da177e4 LT	503	{
	504	if (port->sysrq) {
	505	if (ch && time_before(jiffies, port->sysrq)) {
f335397d	506	handle_sysrq(ch);
1da177e4 LT	507	port->sysrq = 0;
	508	return 1;
	509	}
	510	port->sysrq = 0;
	511	}
	512	return 0;
	513	}
027d7dac JS	514	#else
027d7dac JS	515	#define uart_handle_sysrq_char(port,ch) ({ (void)port; 0; })
4e149184	516	#endif
1da177e4 LT	517
	518	/*
	519	* We do the SysRQ and SAK checking like this...
	520	*/
	521	static inline int uart_handle_break(struct uart_port *port)
	522	{
ebd2c8f6	523	struct uart_state *state = port->state;
1da177e4 LT	524	#ifdef SUPPORT_SYSRQ
	525	if (port->cons && port->cons->index == port->line) {
	526	if (!port->sysrq) {
	527	port->sysrq = jiffies + HZ*5;
	528	return 1;
	529	}
	530	port->sysrq = 0;
	531	}
	532	#endif
27ae7a74	533	if (port->flags & UPF_SAK)
ebd2c8f6	534	do_SAK(state->port.tty);
1da177e4 LT	535	return 0;
	536	}
	537
1da177e4 LT	538	/*
	539	* UART_ENABLE_MS - determine if port should enable modem status irqs
	540	*/
	541	#define UART_ENABLE_MS(port,cflag) ((port)->flags & UPF_HARDPPS_CD \|\| \
	542	(cflag) & CRTSCTS \|\| \
	543	!((cflag) & CLOCAL))
	544
	545	#endif
	546
	547	#endif /* LINUX_SERIAL_CORE_H */