Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * include/linux/serial.h | |
3 | * | |
4 | * Copyright (C) 1992 by Theodore Ts'o. | |
5 | * | |
6 | * Redistribution of this file is permitted under the terms of the GNU | |
7 | * Public License (GPL) | |
8 | */ | |
1da177e4 LT |
9 | #ifndef _LINUX_SERIAL_H |
10 | #define _LINUX_SERIAL_H | |
11 | ||
607ca46e | 12 | #include <uapi/linux/serial.h> |
34619de1 | 13 | #include <uapi/linux/serial_reg.h> |
1da177e4 | 14 | |
ef460db2 IJ |
15 | #define UART_IER_ALL_INTR (UART_IER_MSI | \ |
16 | UART_IER_RLSI | \ | |
17 | UART_IER_THRI | \ | |
18 | UART_IER_RDI) | |
19 | ||
797bd4d4 JS |
20 | /* Helper for dealing with UART_LCR_WLEN* defines */ |
21 | #define UART_LCR_WLEN(x) ((x) - 5) | |
ba3fe7ab | 22 | |
34619de1 IJ |
23 | /* FIFO and shifting register empty */ |
24 | #define UART_LSR_BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) | |
25 | ||
26 | static inline bool uart_lsr_tx_empty(u16 lsr) | |
27 | { | |
28 | return (lsr & UART_LSR_BOTH_EMPTY) == UART_LSR_BOTH_EMPTY; | |
29 | } | |
30 | ||
d9c1d3cb IJ |
31 | #define UART_MSR_STATUS_BITS (UART_MSR_DCD | \ |
32 | UART_MSR_RI | \ | |
33 | UART_MSR_DSR | \ | |
34 | UART_MSR_CTS) | |
35 | ||
1da177e4 LT |
36 | /* |
37 | * Counters of the input lines (CTS, DSR, RI, CD) interrupts | |
38 | */ | |
39 | ||
40 | struct async_icount { | |
41 | __u32 cts, dsr, rng, dcd, tx, rx; | |
42 | __u32 frame, parity, overrun, brk; | |
43 | __u32 buf_overrun; | |
44 | }; | |
45 | ||
661f83a6 RK |
46 | #include <linux/compiler.h> |
47 | ||
1da177e4 | 48 | #endif /* _LINUX_SERIAL_H */ |