projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| aaf4989b | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 67d16a46 WW |
2 | /* Driver for Realtek PCI-Express card reader |
| 3 | * | |
| 09fd8678 | 4 | * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. |
| 67d16a46 | 5 | * |
| 67d16a46 WW |
6 | * Author: |
| 7 | * Wei WANG <wei_wang@realsil.com.cn> | |
| 67d16a46 WW |
8 | */ |
| 9 | ||
| 10 | #ifndef __RTSX_PCI_H | |
| 11 | #define __RTSX_PCI_H | |
| 12 | ||
| 13 | #include <linux/sched.h> | |
| 14 | #include <linux/pci.h> | |
| e455b69d | 15 | #include <linux/rtsx_common.h> |
| 67d16a46 WW |
16 | |
| 17 | #define MAX_RW_REG_CNT 1024 | |
| 18 | ||
| 67d16a46 WW |
19 | #define RTSX_HCBAR 0x00 |
| 20 | #define RTSX_HCBCTLR 0x04 | |
| ada71f55 MC |
21 | #define STOP_CMD (0x01 << 28) |
| 22 | #define READ_REG_CMD 0 | |
| 23 | #define WRITE_REG_CMD 1 | |
| 24 | #define CHECK_REG_CMD 2 | |
| 25 | ||
| 67d16a46 | 26 | #define RTSX_HDBAR 0x08 |
| f16ee7c7 AB |
27 | #define RTSX_SG_INT 0x04 |
| 28 | #define RTSX_SG_END 0x02 | |
| 29 | #define RTSX_SG_VALID 0x01 | |
| 30 | #define RTSX_SG_NO_OP 0x00 | |
| 31 | #define RTSX_SG_TRANS_DATA (0x02 << 4) | |
| 32 | #define RTSX_SG_LINK_DESC (0x03 << 4) | |
| 67d16a46 | 33 | #define RTSX_HDBCTLR 0x0C |
| ada71f55 MC |
34 | #define SDMA_MODE 0x00 |
| 35 | #define ADMA_MODE (0x02 << 26) | |
| 36 | #define STOP_DMA (0x01 << 28) | |
| 37 | #define TRIG_DMA (0x01 << 31) | |
| 38 | ||
| 67d16a46 | 39 | #define RTSX_HAIMR 0x10 |
| ada71f55 MC |
40 | #define HAIMR_TRANS_START (0x01 << 31) |
| 41 | #define HAIMR_READ 0x00 | |
| 42 | #define HAIMR_WRITE (0x01 << 30) | |
| 43 | #define HAIMR_READ_START (HAIMR_TRANS_START | HAIMR_READ) | |
| 44 | #define HAIMR_WRITE_START (HAIMR_TRANS_START | HAIMR_WRITE) | |
| 45 | #define HAIMR_TRANS_END (HAIMR_TRANS_START) | |
| 67d16a46 | 46 | |
| ada71f55 MC |
47 | #define RTSX_BIPR 0x14 |
| 48 | #define CMD_DONE_INT (1 << 31) | |
| 49 | #define DATA_DONE_INT (1 << 30) | |
| 50 | #define TRANS_OK_INT (1 << 29) | |
| 51 | #define TRANS_FAIL_INT (1 << 28) | |
| 52 | #define XD_INT (1 << 27) | |
| 53 | #define MS_INT (1 << 26) | |
| 54 | #define SD_INT (1 << 25) | |
| 55 | #define GPIO0_INT (1 << 24) | |
| 56 | #define OC_INT (1 << 23) | |
| 57 | #define SD_WRITE_PROTECT (1 << 19) | |
| 58 | #define XD_EXIST (1 << 18) | |
| 59 | #define MS_EXIST (1 << 17) | |
| 60 | #define SD_EXIST (1 << 16) | |
| 61 | #define DELINK_INT GPIO0_INT | |
| 62 | #define MS_OC_INT (1 << 23) | |
| 63 | #define SD_OC_INT (1 << 22) | |
| 67d16a46 WW |
64 | |
| 65 | #define CARD_INT (XD_INT | MS_INT | SD_INT) | |
| 66 | #define NEED_COMPLETE_INT (DATA_DONE_INT | TRANS_OK_INT | TRANS_FAIL_INT) | |
| 67 | #define RTSX_INT (CMD_DONE_INT | NEED_COMPLETE_INT | \ | |
| 68 | CARD_INT | GPIO0_INT | OC_INT) | |
| 67d16a46 WW |
69 | #define CARD_EXIST (XD_EXIST | MS_EXIST | SD_EXIST) |
| 70 | ||
| ada71f55 MC |
71 | #define RTSX_BIER 0x18 |
| 72 | #define CMD_DONE_INT_EN (1 << 31) | |
| 73 | #define DATA_DONE_INT_EN (1 << 30) | |
| 74 | #define TRANS_OK_INT_EN (1 << 29) | |
| 75 | #define TRANS_FAIL_INT_EN (1 << 28) | |
| 76 | #define XD_INT_EN (1 << 27) | |
| 77 | #define MS_INT_EN (1 << 26) | |
| 78 | #define SD_INT_EN (1 << 25) | |
| 79 | #define GPIO0_INT_EN (1 << 24) | |
| 80 | #define OC_INT_EN (1 << 23) | |
| 81 | #define DELINK_INT_EN GPIO0_INT_EN | |
| 82 | #define MS_OC_INT_EN (1 << 23) | |
| 83 | #define SD_OC_INT_EN (1 << 22) | |
| 84 | ||
| 67d16a46 WW |
85 | |
| 86 | /* | |
| 87 | * macros for easy use | |
| 88 | */ | |
| 89 | #define rtsx_pci_writel(pcr, reg, value) \ | |
| 90 | iowrite32(value, (pcr)->remap_addr + reg) | |
| 91 | #define rtsx_pci_readl(pcr, reg) \ | |
| 92 | ioread32((pcr)->remap_addr + reg) | |
| 93 | #define rtsx_pci_writew(pcr, reg, value) \ | |
| 94 | iowrite16(value, (pcr)->remap_addr + reg) | |
| 95 | #define rtsx_pci_readw(pcr, reg) \ | |
| 96 | ioread16((pcr)->remap_addr + reg) | |
| 97 | #define rtsx_pci_writeb(pcr, reg, value) \ | |
| 98 | iowrite8(value, (pcr)->remap_addr + reg) | |
| 99 | #define rtsx_pci_readb(pcr, reg) \ | |
| 100 | ioread8((pcr)->remap_addr + reg) | |
| 101 | ||
| ada71f55 MC |
102 | #define STATE_TRANS_NONE 0 |
| 103 | #define STATE_TRANS_CMD 1 | |
| 104 | #define STATE_TRANS_BUF 2 | |
| 105 | #define STATE_TRANS_SG 3 | |
| 773ccdfd | 106 | |
| ada71f55 MC |
107 | #define TRANS_NOT_READY 0 |
| 108 | #define TRANS_RESULT_OK 1 | |
| 109 | #define TRANS_RESULT_FAIL 2 | |
| 110 | #define TRANS_NO_DEVICE 3 | |
| 67d16a46 | 111 | |
| ada71f55 MC |
112 | #define RTSX_RESV_BUF_LEN 4096 |
| 113 | #define HOST_CMDS_BUF_LEN 1024 | |
| 114 | #define HOST_SG_TBL_BUF_LEN (RTSX_RESV_BUF_LEN - HOST_CMDS_BUF_LEN) | |
| 115 | #define HOST_SG_TBL_ITEMS (HOST_SG_TBL_BUF_LEN / 8) | |
| 116 | #define MAX_SG_ITEM_LEN 0x80000 | |
| 117 | #define HOST_TO_DEVICE 0 | |
| 118 | #define DEVICE_TO_HOST 1 | |
| 119 | ||
| 120 | #define OUTPUT_3V3 0 | |
| 121 | #define OUTPUT_1V8 1 | |
| 67d16a46 | 122 | |
| ada71f55 MC |
123 | #define RTSX_PHASE_MAX 32 |
| 124 | #define RX_TUNING_CNT 3 | |
| 5947c167 | 125 | |
| 67d16a46 | 126 | #define MS_CFG 0xFD40 |
| ada71f55 MC |
127 | #define SAMPLE_TIME_RISING 0x00 |
| 128 | #define SAMPLE_TIME_FALLING 0x80 | |
| 129 | #define PUSH_TIME_DEFAULT 0x00 | |
| 130 | #define PUSH_TIME_ODD 0x40 | |
| 131 | #define NO_EXTEND_TOGGLE 0x00 | |
| 132 | #define EXTEND_TOGGLE_CHK 0x20 | |
| 133 | #define MS_BUS_WIDTH_1 0x00 | |
| 134 | #define MS_BUS_WIDTH_4 0x10 | |
| 135 | #define MS_BUS_WIDTH_8 0x18 | |
| 136 | #define MS_2K_SECTOR_MODE 0x04 | |
| 137 | #define MS_512_SECTOR_MODE 0x00 | |
| 138 | #define MS_TOGGLE_TIMEOUT_EN 0x00 | |
| 139 | #define MS_TOGGLE_TIMEOUT_DISEN 0x01 | |
| 140 | #define MS_NO_CHECK_INT 0x02 | |
| 67d16a46 WW |
141 | #define MS_TPC 0xFD41 |
| 142 | #define MS_TRANS_CFG 0xFD42 | |
| ada71f55 MC |
143 | #define WAIT_INT 0x80 |
| 144 | #define NO_WAIT_INT 0x00 | |
| 145 | #define NO_AUTO_READ_INT_REG 0x00 | |
| 146 | #define AUTO_READ_INT_REG 0x40 | |
| 147 | #define MS_CRC16_ERR 0x20 | |
| 148 | #define MS_RDY_TIMEOUT 0x10 | |
| 149 | #define MS_INT_CMDNK 0x08 | |
| 150 | #define MS_INT_BREQ 0x04 | |
| 151 | #define MS_INT_ERR 0x02 | |
| 152 | #define MS_INT_CED 0x01 | |
| 67d16a46 | 153 | #define MS_TRANSFER 0xFD43 |
| ada71f55 MC |
154 | #define MS_TRANSFER_START 0x80 |
| 155 | #define MS_TRANSFER_END 0x40 | |
| 156 | #define MS_TRANSFER_ERR 0x20 | |
| 157 | #define MS_BS_STATE 0x10 | |
| 158 | #define MS_TM_READ_BYTES 0x00 | |
| 159 | #define MS_TM_NORMAL_READ 0x01 | |
| 160 | #define MS_TM_WRITE_BYTES 0x04 | |
| 161 | #define MS_TM_NORMAL_WRITE 0x05 | |
| 162 | #define MS_TM_AUTO_READ 0x08 | |
| 163 | #define MS_TM_AUTO_WRITE 0x0C | |
| 67d16a46 WW |
164 | #define MS_INT_REG 0xFD44 |
| 165 | #define MS_BYTE_CNT 0xFD45 | |
| 166 | #define MS_SECTOR_CNT_L 0xFD46 | |
| 167 | #define MS_SECTOR_CNT_H 0xFD47 | |
| 168 | #define MS_DBUS_H 0xFD48 | |
| 169 | ||
| 170 | #define SD_CFG1 0xFDA0 | |
| ada71f55 MC |
171 | #define SD_CLK_DIVIDE_0 0x00 |
| 172 | #define SD_CLK_DIVIDE_256 0xC0 | |
| 173 | #define SD_CLK_DIVIDE_128 0x80 | |
| 174 | #define SD_BUS_WIDTH_1BIT 0x00 | |
| 175 | #define SD_BUS_WIDTH_4BIT 0x01 | |
| 176 | #define SD_BUS_WIDTH_8BIT 0x02 | |
| 177 | #define SD_ASYNC_FIFO_NOT_RST 0x10 | |
| 178 | #define SD_20_MODE 0x00 | |
| 179 | #define SD_DDR_MODE 0x04 | |
| 180 | #define SD_30_MODE 0x08 | |
| 181 | #define SD_CLK_DIVIDE_MASK 0xC0 | |
| 5da4e04a | 182 | #define SD_MODE_SELECT_MASK 0x0C |
| 67d16a46 | 183 | #define SD_CFG2 0xFDA1 |
| ada71f55 MC |
184 | #define SD_CALCULATE_CRC7 0x00 |
| 185 | #define SD_NO_CALCULATE_CRC7 0x80 | |
| 186 | #define SD_CHECK_CRC16 0x00 | |
| 187 | #define SD_NO_CHECK_CRC16 0x40 | |
| 188 | #define SD_NO_CHECK_WAIT_CRC_TO 0x20 | |
| 189 | #define SD_WAIT_BUSY_END 0x08 | |
| 190 | #define SD_NO_WAIT_BUSY_END 0x00 | |
| 191 | #define SD_CHECK_CRC7 0x00 | |
| 192 | #define SD_NO_CHECK_CRC7 0x04 | |
| 193 | #define SD_RSP_LEN_0 0x00 | |
| 194 | #define SD_RSP_LEN_6 0x01 | |
| 195 | #define SD_RSP_LEN_17 0x02 | |
| 196 | #define SD_RSP_TYPE_R0 0x04 | |
| 197 | #define SD_RSP_TYPE_R1 0x01 | |
| 198 | #define SD_RSP_TYPE_R1b 0x09 | |
| 199 | #define SD_RSP_TYPE_R2 0x02 | |
| 200 | #define SD_RSP_TYPE_R3 0x05 | |
| 201 | #define SD_RSP_TYPE_R4 0x05 | |
| 202 | #define SD_RSP_TYPE_R5 0x01 | |
| 203 | #define SD_RSP_TYPE_R6 0x01 | |
| 204 | #define SD_RSP_TYPE_R7 0x01 | |
| 67d16a46 | 205 | #define SD_CFG3 0xFDA2 |
| 5da4e04a | 206 | #define SD30_CLK_END_EN 0x10 |
| ada71f55 MC |
207 | #define SD_RSP_80CLK_TIMEOUT_EN 0x01 |
| 208 | ||
| 67d16a46 | 209 | #define SD_STAT1 0xFDA3 |
| ada71f55 MC |
210 | #define SD_CRC7_ERR 0x80 |
| 211 | #define SD_CRC16_ERR 0x40 | |
| 212 | #define SD_CRC_WRITE_ERR 0x20 | |
| 213 | #define SD_CRC_WRITE_ERR_MASK 0x1C | |
| 214 | #define GET_CRC_TIME_OUT 0x02 | |
| 215 | #define SD_TUNING_COMPARE_ERR 0x01 | |
| 67d16a46 | 216 | #define SD_STAT2 0xFDA4 |
| ada71f55 MC |
217 | #define SD_RSP_80CLK_TIMEOUT 0x01 |
| 218 | ||
| 67d16a46 | 219 | #define SD_BUS_STAT 0xFDA5 |
| ada71f55 MC |
220 | #define SD_CLK_TOGGLE_EN 0x80 |
| 221 | #define SD_CLK_FORCE_STOP 0x40 | |
| 222 | #define SD_DAT3_STATUS 0x10 | |
| 223 | #define SD_DAT2_STATUS 0x08 | |
| 224 | #define SD_DAT1_STATUS 0x04 | |
| 225 | #define SD_DAT0_STATUS 0x02 | |
| 226 | #define SD_CMD_STATUS 0x01 | |
| 67d16a46 | 227 | #define SD_PAD_CTL 0xFDA6 |
| ada71f55 MC |
228 | #define SD_IO_USING_1V8 0x80 |
| 229 | #define SD_IO_USING_3V3 0x7F | |
| 230 | #define TYPE_A_DRIVING 0x00 | |
| 231 | #define TYPE_B_DRIVING 0x01 | |
| 232 | #define TYPE_C_DRIVING 0x02 | |
| 233 | #define TYPE_D_DRIVING 0x03 | |
| 67d16a46 | 234 | #define SD_SAMPLE_POINT_CTL 0xFDA7 |
| ada71f55 MC |
235 | #define DDR_FIX_RX_DAT 0x00 |
| 236 | #define DDR_VAR_RX_DAT 0x80 | |
| 237 | #define DDR_FIX_RX_DAT_EDGE 0x00 | |
| 238 | #define DDR_FIX_RX_DAT_14_DELAY 0x40 | |
| 239 | #define DDR_FIX_RX_CMD 0x00 | |
| 240 | #define DDR_VAR_RX_CMD 0x20 | |
| 241 | #define DDR_FIX_RX_CMD_POS_EDGE 0x00 | |
| 242 | #define DDR_FIX_RX_CMD_14_DELAY 0x10 | |
| 243 | #define SD20_RX_POS_EDGE 0x00 | |
| 244 | #define SD20_RX_14_DELAY 0x08 | |
| 245 | #define SD20_RX_SEL_MASK 0x08 | |
| 67d16a46 | 246 | #define SD_PUSH_POINT_CTL 0xFDA8 |
| ada71f55 MC |
247 | #define DDR_FIX_TX_CMD_DAT 0x00 |
| 248 | #define DDR_VAR_TX_CMD_DAT 0x80 | |
| 249 | #define DDR_FIX_TX_DAT_14_TSU 0x00 | |
| 250 | #define DDR_FIX_TX_DAT_12_TSU 0x40 | |
| 251 | #define DDR_FIX_TX_CMD_NEG_EDGE 0x00 | |
| 252 | #define DDR_FIX_TX_CMD_14_AHEAD 0x20 | |
| 253 | #define SD20_TX_NEG_EDGE 0x00 | |
| 254 | #define SD20_TX_14_AHEAD 0x10 | |
| 255 | #define SD20_TX_SEL_MASK 0x10 | |
| 256 | #define DDR_VAR_SDCLK_POL_SWAP 0x01 | |
| 67d16a46 | 257 | #define SD_CMD0 0xFDA9 |
| a3b63979 | 258 | #define SD_CMD_START 0x40 |
| 67d16a46 WW |
259 | #define SD_CMD1 0xFDAA |
| 260 | #define SD_CMD2 0xFDAB | |
| 261 | #define SD_CMD3 0xFDAC | |
| 262 | #define SD_CMD4 0xFDAD | |
| 263 | #define SD_CMD5 0xFDAE | |
| 264 | #define SD_BYTE_CNT_L 0xFDAF | |
| 265 | #define SD_BYTE_CNT_H 0xFDB0 | |
| 266 | #define SD_BLOCK_CNT_L 0xFDB1 | |
| 267 | #define SD_BLOCK_CNT_H 0xFDB2 | |
| 268 | #define SD_TRANSFER 0xFDB3 | |
| ada71f55 MC |
269 | #define SD_TRANSFER_START 0x80 |
| 270 | #define SD_TRANSFER_END 0x40 | |
| 271 | #define SD_STAT_IDLE 0x20 | |
| 272 | #define SD_TRANSFER_ERR 0x10 | |
| 273 | #define SD_TM_NORMAL_WRITE 0x00 | |
| 274 | #define SD_TM_AUTO_WRITE_3 0x01 | |
| 275 | #define SD_TM_AUTO_WRITE_4 0x02 | |
| 276 | #define SD_TM_AUTO_READ_3 0x05 | |
| 277 | #define SD_TM_AUTO_READ_4 0x06 | |
| 278 | #define SD_TM_CMD_RSP 0x08 | |
| 279 | #define SD_TM_AUTO_WRITE_1 0x09 | |
| 280 | #define SD_TM_AUTO_WRITE_2 0x0A | |
| 281 | #define SD_TM_NORMAL_READ 0x0C | |
| 282 | #define SD_TM_AUTO_READ_1 0x0D | |
| 283 | #define SD_TM_AUTO_READ_2 0x0E | |
| 284 | #define SD_TM_AUTO_TUNING 0x0F | |
| 67d16a46 | 285 | #define SD_CMD_STATE 0xFDB5 |
| ada71f55 MC |
286 | #define SD_CMD_IDLE 0x80 |
| 287 | ||
| 67d16a46 | 288 | #define SD_DATA_STATE 0xFDB6 |
| ada71f55 | 289 | #define SD_DATA_IDLE 0x80 |
| 5da4e04a RF |
290 | #define REG_SD_STOP_SDCLK_CFG 0xFDB8 |
| 291 | #define SD30_CLK_STOP_CFG_EN 0x04 | |
| 292 | #define SD30_CLK_STOP_CFG1 0x02 | |
| 293 | #define SD30_CLK_STOP_CFG0 0x01 | |
| 294 | #define REG_PRE_RW_MODE 0xFD70 | |
| 295 | #define EN_INFINITE_MODE 0x01 | |
| 849a9366 RW |
296 | #define REG_CRC_DUMMY_0 0xFD71 |
| 297 | #define CFG_SD_POW_AUTO_PD (1<<0) | |
| 67d16a46 WW |
298 | |
| 299 | #define SRCTL 0xFC13 | |
| 300 | ||
| 84f00b1b | 301 | #define DCM_DRP_CTL 0xFC23 |
| ada71f55 MC |
302 | #define DCM_RESET 0x08 |
| 303 | #define DCM_LOCKED 0x04 | |
| 304 | #define DCM_208M 0x00 | |
| 305 | #define DCM_TX 0x01 | |
| 306 | #define DCM_RX 0x02 | |
| 84f00b1b | 307 | #define DCM_DRP_TRIG 0xFC24 |
| ada71f55 MC |
308 | #define DRP_START 0x80 |
| 309 | #define DRP_DONE 0x40 | |
| 84f00b1b | 310 | #define DCM_DRP_CFG 0xFC25 |
| ada71f55 MC |
311 | #define DRP_WRITE 0x80 |
| 312 | #define DRP_READ 0x00 | |
| 313 | #define DCM_WRITE_ADDRESS_50 0x50 | |
| 314 | #define DCM_WRITE_ADDRESS_51 0x51 | |
| 315 | #define DCM_READ_ADDRESS_00 0x00 | |
| 316 | #define DCM_READ_ADDRESS_51 0x51 | |
| 84f00b1b MC |
317 | #define DCM_DRP_WR_DATA_L 0xFC26 |
| 318 | #define DCM_DRP_WR_DATA_H 0xFC27 | |
| 319 | #define DCM_DRP_RD_DATA_L 0xFC28 | |
| 320 | #define DCM_DRP_RD_DATA_H 0xFC29 | |
| 67d16a46 WW |
321 | #define SD_VPCLK0_CTL 0xFC2A |
| 322 | #define SD_VPCLK1_CTL 0xFC2B | |
| 563be8b6 | 323 | #define PHASE_SELECT_MASK 0x1F |
| 67d16a46 WW |
324 | #define SD_DCMPS0_CTL 0xFC2C |
| 325 | #define SD_DCMPS1_CTL 0xFC2D | |
| 326 | #define SD_VPTX_CTL SD_VPCLK0_CTL | |
| 327 | #define SD_VPRX_CTL SD_VPCLK1_CTL | |
| ada71f55 MC |
328 | #define PHASE_CHANGE 0x80 |
| 329 | #define PHASE_NOT_RESET 0x40 | |
| 67d16a46 WW |
330 | #define SD_DCMPS_TX_CTL SD_DCMPS0_CTL |
| 331 | #define SD_DCMPS_RX_CTL SD_DCMPS1_CTL | |
| ada71f55 MC |
332 | #define DCMPS_CHANGE 0x80 |
| 333 | #define DCMPS_CHANGE_DONE 0x40 | |
| 334 | #define DCMPS_ERROR 0x20 | |
| 335 | #define DCMPS_CURRENT_PHASE 0x1F | |
| 67d16a46 | 336 | #define CARD_CLK_SOURCE 0xFC2E |
| ada71f55 MC |
337 | #define CRC_FIX_CLK (0x00 << 0) |
| 338 | #define CRC_VAR_CLK0 (0x01 << 0) | |
| 339 | #define CRC_VAR_CLK1 (0x02 << 0) | |
| 340 | #define SD30_FIX_CLK (0x00 << 2) | |
| 341 | #define SD30_VAR_CLK0 (0x01 << 2) | |
| 342 | #define SD30_VAR_CLK1 (0x02 << 2) | |
| 343 | #define SAMPLE_FIX_CLK (0x00 << 4) | |
| 344 | #define SAMPLE_VAR_CLK0 (0x01 << 4) | |
| 345 | #define SAMPLE_VAR_CLK1 (0x02 << 4) | |
| 67d16a46 | 346 | #define CARD_PWR_CTL 0xFD50 |
| ada71f55 MC |
347 | #define PMOS_STRG_MASK 0x10 |
| 348 | #define PMOS_STRG_800mA 0x10 | |
| 349 | #define PMOS_STRG_400mA 0x00 | |
| 350 | #define SD_POWER_OFF 0x03 | |
| 351 | #define SD_PARTIAL_POWER_ON 0x01 | |
| 352 | #define SD_POWER_ON 0x00 | |
| 353 | #define SD_POWER_MASK 0x03 | |
| 354 | #define MS_POWER_OFF 0x0C | |
| 355 | #define MS_PARTIAL_POWER_ON 0x04 | |
| 356 | #define MS_POWER_ON 0x00 | |
| 357 | #define MS_POWER_MASK 0x0C | |
| 358 | #define BPP_POWER_OFF 0x0F | |
| 359 | #define BPP_POWER_5_PERCENT_ON 0x0E | |
| 360 | #define BPP_POWER_10_PERCENT_ON 0x0C | |
| 361 | #define BPP_POWER_15_PERCENT_ON 0x08 | |
| 362 | #define BPP_POWER_ON 0x00 | |
| 363 | #define BPP_POWER_MASK 0x0F | |
| 364 | #define SD_VCC_PARTIAL_POWER_ON 0x02 | |
| 365 | #define SD_VCC_POWER_ON 0x00 | |
| 67d16a46 | 366 | #define CARD_CLK_SWITCH 0xFD51 |
| 9032eabd | 367 | #define RTL8411B_PACKAGE_MODE 0xFD51 |
| 67d16a46 | 368 | #define CARD_SHARE_MODE 0xFD52 |
| ada71f55 MC |
369 | #define CARD_SHARE_MASK 0x0F |
| 370 | #define CARD_SHARE_MULTI_LUN 0x00 | |
| 371 | #define CARD_SHARE_NORMAL 0x00 | |
| 372 | #define CARD_SHARE_48_SD 0x04 | |
| 373 | #define CARD_SHARE_48_MS 0x08 | |
| 374 | #define CARD_SHARE_BAROSSA_SD 0x01 | |
| 375 | #define CARD_SHARE_BAROSSA_MS 0x02 | |
| 67d16a46 | 376 | #define CARD_DRIVE_SEL 0xFD53 |
| ada71f55 MC |
377 | #define MS_DRIVE_8mA (0x01 << 6) |
| 378 | #define MMC_DRIVE_8mA (0x01 << 4) | |
| 379 | #define XD_DRIVE_8mA (0x01 << 2) | |
| 380 | #define GPIO_DRIVE_8mA 0x01 | |
| 381 | #define RTS5209_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | MMC_DRIVE_8mA |\ | |
| 382 | XD_DRIVE_8mA | GPIO_DRIVE_8mA) | |
| 383 | #define RTL8411_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | MMC_DRIVE_8mA |\ | |
| 384 | XD_DRIVE_8mA) | |
| 385 | #define RTSX_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | GPIO_DRIVE_8mA) | |
| 386 | ||
| 67d16a46 | 387 | #define CARD_STOP 0xFD54 |
| ada71f55 MC |
388 | #define SPI_STOP 0x01 |
| 389 | #define XD_STOP 0x02 | |
| 390 | #define SD_STOP 0x04 | |
| 391 | #define MS_STOP 0x08 | |
| 392 | #define SPI_CLR_ERR 0x10 | |
| 393 | #define XD_CLR_ERR 0x20 | |
| 394 | #define SD_CLR_ERR 0x40 | |
| 395 | #define MS_CLR_ERR 0x80 | |
| 67d16a46 | 396 | #define CARD_OE 0xFD55 |
| ada71f55 MC |
397 | #define SD_OUTPUT_EN 0x04 |
| 398 | #define MS_OUTPUT_EN 0x08 | |
| 67d16a46 WW |
399 | #define CARD_AUTO_BLINK 0xFD56 |
| 400 | #define CARD_GPIO_DIR 0xFD57 | |
| 401 | #define CARD_GPIO 0xFD58 | |
| 402 | #define CARD_DATA_SOURCE 0xFD5B | |
| ada71f55 MC |
403 | #define PINGPONG_BUFFER 0x01 |
| 404 | #define RING_BUFFER 0x00 | |
| e1237932 | 405 | #define SD30_CLK_DRIVE_SEL 0xFD5A |
| ada71f55 MC |
406 | #define DRIVER_TYPE_A 0x05 |
| 407 | #define DRIVER_TYPE_B 0x03 | |
| 408 | #define DRIVER_TYPE_C 0x02 | |
| 409 | #define DRIVER_TYPE_D 0x01 | |
| 67d16a46 | 410 | #define CARD_SELECT 0xFD5C |
| ada71f55 MC |
411 | #define SD_MOD_SEL 2 |
| 412 | #define MS_MOD_SEL 3 | |
| 67d16a46 | 413 | #define SD30_DRIVE_SEL 0xFD5E |
| ada71f55 MC |
414 | #define CFG_DRIVER_TYPE_A 0x02 |
| 415 | #define CFG_DRIVER_TYPE_B 0x03 | |
| 416 | #define CFG_DRIVER_TYPE_C 0x01 | |
| 417 | #define CFG_DRIVER_TYPE_D 0x00 | |
| e1237932 RT |
418 | #define SD30_CMD_DRIVE_SEL 0xFD5E |
| 419 | #define SD30_DAT_DRIVE_SEL 0xFD5F | |
| 67d16a46 | 420 | #define CARD_CLK_EN 0xFD69 |
| ada71f55 MC |
421 | #define SD_CLK_EN 0x04 |
| 422 | #define MS_CLK_EN 0x08 | |
| 5da4e04a | 423 | #define SD40_CLK_EN 0x10 |
| 67d16a46 WW |
424 | #define SDIO_CTRL 0xFD6B |
| 425 | #define CD_PAD_CTL 0xFD73 | |
| ada71f55 MC |
426 | #define CD_DISABLE_MASK 0x07 |
| 427 | #define MS_CD_DISABLE 0x04 | |
| 428 | #define SD_CD_DISABLE 0x02 | |
| 429 | #define XD_CD_DISABLE 0x01 | |
| 430 | #define CD_DISABLE 0x07 | |
| 431 | #define CD_ENABLE 0x00 | |
| 432 | #define MS_CD_EN_ONLY 0x03 | |
| 433 | #define SD_CD_EN_ONLY 0x05 | |
| 434 | #define XD_CD_EN_ONLY 0x06 | |
| 435 | #define FORCE_CD_LOW_MASK 0x38 | |
| 436 | #define FORCE_CD_XD_LOW 0x08 | |
| 437 | #define FORCE_CD_SD_LOW 0x10 | |
| 438 | #define FORCE_CD_MS_LOW 0x20 | |
| 439 | #define CD_AUTO_DISABLE 0x40 | |
| 67d16a46 | 440 | #define FPDCTL 0xFC00 |
| ada71f55 MC |
441 | #define SSC_POWER_DOWN 0x01 |
| 442 | #define SD_OC_POWER_DOWN 0x02 | |
| 5da4e04a RF |
443 | #define ALL_POWER_DOWN 0x03 |
| 444 | #define OC_POWER_DOWN 0x02 | |
| 67d16a46 WW |
445 | #define PDINFO 0xFC01 |
| 446 | ||
| 447 | #define CLK_CTL 0xFC02 | |
| ada71f55 MC |
448 | #define CHANGE_CLK 0x01 |
| 449 | #define CLK_LOW_FREQ 0x01 | |
| 450 | ||
| 67d16a46 | 451 | #define CLK_DIV 0xFC03 |
| ada71f55 MC |
452 | #define CLK_DIV_1 0x01 |
| 453 | #define CLK_DIV_2 0x02 | |
| 454 | #define CLK_DIV_4 0x03 | |
| 455 | #define CLK_DIV_8 0x04 | |
| 67d16a46 WW |
456 | #define CLK_SEL 0xFC04 |
| 457 | ||
| 458 | #define SSC_DIV_N_0 0xFC0F | |
| 459 | #define SSC_DIV_N_1 0xFC10 | |
| 460 | #define SSC_CTL1 0xFC11 | |
| ada71f55 MC |
461 | #define SSC_RSTB 0x80 |
| 462 | #define SSC_8X_EN 0x40 | |
| 463 | #define SSC_FIX_FRAC 0x20 | |
| 464 | #define SSC_SEL_1M 0x00 | |
| 465 | #define SSC_SEL_2M 0x08 | |
| 466 | #define SSC_SEL_4M 0x10 | |
| 467 | #define SSC_SEL_8M 0x18 | |
| 67d16a46 | 468 | #define SSC_CTL2 0xFC12 |
| ada71f55 MC |
469 | #define SSC_DEPTH_MASK 0x07 |
| 470 | #define SSC_DEPTH_DISALBE 0x00 | |
| 471 | #define SSC_DEPTH_4M 0x01 | |
| 472 | #define SSC_DEPTH_2M 0x02 | |
| 473 | #define SSC_DEPTH_1M 0x03 | |
| 474 | #define SSC_DEPTH_500K 0x04 | |
| 475 | #define SSC_DEPTH_250K 0x05 | |
| 67d16a46 WW |
476 | #define RCCTL 0xFC14 |
| 477 | ||
| 478 | #define FPGA_PULL_CTL 0xFC1D | |
| 479 | #define OLT_LED_CTL 0xFC1E | |
| 5da4e04a RF |
480 | #define LED_SHINE_MASK 0x08 |
| 481 | #define LED_SHINE_EN 0x08 | |
| 482 | #define LED_SHINE_DISABLE 0x00 | |
| 67d16a46 WW |
483 | #define GPIO_CTL 0xFC1F |
| 484 | ||
| 485 | #define LDO_CTL 0xFC1E | |
| ada71f55 MC |
486 | #define BPP_ASIC_1V7 0x00 |
| 487 | #define BPP_ASIC_1V8 0x01 | |
| 488 | #define BPP_ASIC_1V9 0x02 | |
| 489 | #define BPP_ASIC_2V0 0x03 | |
| 490 | #define BPP_ASIC_2V7 0x04 | |
| 491 | #define BPP_ASIC_2V8 0x05 | |
| 492 | #define BPP_ASIC_3V2 0x06 | |
| 493 | #define BPP_ASIC_3V3 0x07 | |
| 494 | #define BPP_REG_TUNED18 0x07 | |
| 495 | #define BPP_TUNED18_SHIFT_8402 5 | |
| 496 | #define BPP_TUNED18_SHIFT_8411 4 | |
| 497 | #define BPP_PAD_MASK 0x04 | |
| 498 | #define BPP_PAD_3V3 0x04 | |
| 499 | #define BPP_PAD_1V8 0x00 | |
| 500 | #define BPP_LDO_POWB 0x03 | |
| 501 | #define BPP_LDO_ON 0x00 | |
| 502 | #define BPP_LDO_SUSPEND 0x02 | |
| 503 | #define BPP_LDO_OFF 0x03 | |
| 5da4e04a RF |
504 | #define EFUSE_CTL 0xFC30 |
| 505 | #define EFUSE_ADD 0xFC31 | |
| 67d16a46 | 506 | #define SYS_VER 0xFC32 |
| 5da4e04a RF |
507 | #define EFUSE_DATAL 0xFC34 |
| 508 | #define EFUSE_DATAH 0xFC35 | |
| 67d16a46 WW |
509 | |
| 510 | #define CARD_PULL_CTL1 0xFD60 | |
| 511 | #define CARD_PULL_CTL2 0xFD61 | |
| 512 | #define CARD_PULL_CTL3 0xFD62 | |
| 513 | #define CARD_PULL_CTL4 0xFD63 | |
| 514 | #define CARD_PULL_CTL5 0xFD64 | |
| 515 | #define CARD_PULL_CTL6 0xFD65 | |
| 516 | ||
| 517 | /* PCI Express Related Registers */ | |
| 518 | #define IRQEN0 0xFE20 | |
| 519 | #define IRQSTAT0 0xFE21 | |
| ada71f55 MC |
520 | #define DMA_DONE_INT 0x80 |
| 521 | #define SUSPEND_INT 0x40 | |
| 522 | #define LINK_RDY_INT 0x20 | |
| 523 | #define LINK_DOWN_INT 0x10 | |
| 67d16a46 WW |
524 | #define IRQEN1 0xFE22 |
| 525 | #define IRQSTAT1 0xFE23 | |
| 526 | #define TLPRIEN 0xFE24 | |
| 527 | #define TLPRISTAT 0xFE25 | |
| 528 | #define TLPTIEN 0xFE26 | |
| 529 | #define TLPTISTAT 0xFE27 | |
| 530 | #define DMATC0 0xFE28 | |
| 531 | #define DMATC1 0xFE29 | |
| 532 | #define DMATC2 0xFE2A | |
| 533 | #define DMATC3 0xFE2B | |
| 534 | #define DMACTL 0xFE2C | |
| ada71f55 MC |
535 | #define DMA_RST 0x80 |
| 536 | #define DMA_BUSY 0x04 | |
| 537 | #define DMA_DIR_TO_CARD 0x00 | |
| 538 | #define DMA_DIR_FROM_CARD 0x02 | |
| 539 | #define DMA_EN 0x01 | |
| 540 | #define DMA_128 (0 << 4) | |
| 541 | #define DMA_256 (1 << 4) | |
| 542 | #define DMA_512 (2 << 4) | |
| 543 | #define DMA_1024 (3 << 4) | |
| 544 | #define DMA_PACK_SIZE_MASK 0x30 | |
| 67d16a46 WW |
545 | #define BCTL 0xFE2D |
| 546 | #define RBBC0 0xFE2E | |
| 547 | #define RBBC1 0xFE2F | |
| 548 | #define RBDAT 0xFE30 | |
| 549 | #define RBCTL 0xFE34 | |
| 5da4e04a RF |
550 | #define U_AUTO_DMA_EN_MASK 0x20 |
| 551 | #define U_AUTO_DMA_DISABLE 0x00 | |
| 552 | #define RB_FLUSH 0x80 | |
| 67d16a46 WW |
553 | #define CFGADDR0 0xFE35 |
| 554 | #define CFGADDR1 0xFE36 | |
| 555 | #define CFGDATA0 0xFE37 | |
| 556 | #define CFGDATA1 0xFE38 | |
| 557 | #define CFGDATA2 0xFE39 | |
| 558 | #define CFGDATA3 0xFE3A | |
| 559 | #define CFGRWCTL 0xFE3B | |
| 560 | #define PHYRWCTL 0xFE3C | |
| 561 | #define PHYDATA0 0xFE3D | |
| 562 | #define PHYDATA1 0xFE3E | |
| 563 | #define PHYADDR 0xFE3F | |
| 564 | #define MSGRXDATA0 0xFE40 | |
| 565 | #define MSGRXDATA1 0xFE41 | |
| 566 | #define MSGRXDATA2 0xFE42 | |
| 567 | #define MSGRXDATA3 0xFE43 | |
| 568 | #define MSGTXDATA0 0xFE44 | |
| 569 | #define MSGTXDATA1 0xFE45 | |
| 570 | #define MSGTXDATA2 0xFE46 | |
| 571 | #define MSGTXDATA3 0xFE47 | |
| 572 | #define MSGTXCTL 0xFE48 | |
| e1237932 | 573 | #define LTR_CTL 0xFE4A |
| 8275b77a RF |
574 | #define LTR_TX_EN_MASK BIT(7) |
| 575 | #define LTR_TX_EN_1 BIT(7) | |
| 576 | #define LTR_TX_EN_0 0 | |
| 577 | #define LTR_LATENCY_MODE_MASK BIT(6) | |
| 578 | #define LTR_LATENCY_MODE_HW 0 | |
| 579 | #define LTR_LATENCY_MODE_SW BIT(6) | |
| e1237932 | 580 | #define OBFF_CFG 0xFE4C |
| 5da4e04a RF |
581 | #define OBFF_EN_MASK 0x03 |
| 582 | #define OBFF_DISABLE 0x00 | |
| 67d16a46 WW |
583 | |
| 584 | #define CDRESUMECTL 0xFE52 | |
| 585 | #define WAKE_SEL_CTL 0xFE54 | |
| 663c425f MC |
586 | #define PCLK_CTL 0xFE55 |
| 587 | #define PCLK_MODE_SEL 0x20 | |
| 67d16a46 | 588 | #define PME_FORCE_CTL 0xFE56 |
| 663c425f | 589 | |
| 67d16a46 | 590 | #define ASPM_FORCE_CTL 0xFE57 |
| 663c425f | 591 | #define FORCE_ASPM_CTL0 0x10 |
| 849a9366 | 592 | #define FORCE_ASPM_CTL1 0x20 |
| 663c425f MC |
593 | #define FORCE_ASPM_VAL_MASK 0x03 |
| 594 | #define FORCE_ASPM_L1_EN 0x02 | |
| 595 | #define FORCE_ASPM_L0_EN 0x01 | |
| 596 | #define FORCE_ASPM_NO_ASPM 0x00 | |
| 67d16a46 | 597 | #define PM_CLK_FORCE_CTL 0xFE58 |
| 5da4e04a | 598 | #define CLK_PM_EN 0x01 |
| 0ccc0065 | 599 | #define FUNC_FORCE_CTL 0xFE59 |
| ce6a5acc | 600 | #define FUNC_FORCE_UPME_XMT_DBG 0x02 |
| 67d16a46 WW |
601 | #define PERST_GLITCH_WIDTH 0xFE5C |
| 602 | #define CHANGE_LINK_STATE 0xFE5B | |
| 603 | #define RESET_LOAD_REG 0xFE5E | |
| 604 | #define EFUSE_CONTENT 0xFE5F | |
| 605 | #define HOST_SLEEP_STATE 0xFE60 | |
| ada71f55 MC |
606 | #define HOST_ENTER_S1 1 |
| 607 | #define HOST_ENTER_S3 2 | |
| 608 | ||
| 67d16a46 | 609 | #define SDIO_CFG 0xFE70 |
| 663c425f MC |
610 | #define PM_EVENT_DEBUG 0xFE71 |
| 611 | #define PME_DEBUG_0 0x08 | |
| 67d16a46 WW |
612 | #define NFTS_TX_CTRL 0xFE72 |
| 613 | ||
| 614 | #define PWR_GATE_CTRL 0xFE75 | |
| ada71f55 MC |
615 | #define PWR_GATE_EN 0x01 |
| 616 | #define LDO3318_PWR_MASK 0x06 | |
| 617 | #define LDO_ON 0x00 | |
| 618 | #define LDO_SUSPEND 0x04 | |
| 619 | #define LDO_OFF 0x06 | |
| 67d16a46 WW |
620 | #define PWD_SUSPEND_EN 0xFE76 |
| 621 | #define LDO_PWR_SEL 0xFE78 | |
| 622 | ||
| 663c425f | 623 | #define L1SUB_CONFIG1 0xFE8D |
| 5da4e04a RF |
624 | #define AUX_CLK_ACTIVE_SEL_MASK 0x01 |
| 625 | #define MAC_CKSW_DONE 0x00 | |
| 663c425f MC |
626 | #define L1SUB_CONFIG2 0xFE8E |
| 627 | #define L1SUB_AUTO_CFG 0x02 | |
| 628 | #define L1SUB_CONFIG3 0xFE8F | |
| 8275b77a | 629 | #define L1OFF_MBIAS2_EN_5250 BIT(7) |
| 663c425f | 630 | |
| 67d16a46 | 631 | #define DUMMY_REG_RESET_0 0xFE90 |
| 5da4e04a | 632 | #define IC_VERSION_MASK 0x0F |
| 67d16a46 | 633 | |
| 5da4e04a RF |
634 | #define REG_VREF 0xFE97 |
| 635 | #define PWD_SUSPND_EN 0x10 | |
| 636 | #define RTS5260_DMA_RST_CTL_0 0xFEBF | |
| 637 | #define RTS5260_DMA_RST 0x80 | |
| 638 | #define RTS5260_ADMA3_RST 0x40 | |
| 773ccdfd | 639 | #define AUTOLOAD_CFG_BASE 0xFF00 |
| 5da4e04a | 640 | #define RELINK_TIME_MASK 0x01 |
| 9e33ce79 | 641 | #define PETXCFG 0xFF03 |
| 8275b77a RF |
642 | #define FORCE_CLKREQ_DELINK_MASK BIT(7) |
| 643 | #define FORCE_CLKREQ_LOW 0x80 | |
| 644 | #define FORCE_CLKREQ_HIGH 0x00 | |
| 773ccdfd | 645 | |
| 5947c167 | 646 | #define PM_CTRL1 0xFF44 |
| 663c425f MC |
647 | #define CD_RESUME_EN_MASK 0xF0 |
| 648 | ||
| 5947c167 WW |
649 | #define PM_CTRL2 0xFF45 |
| 650 | #define PM_CTRL3 0xFF46 | |
| 5cb5d961 MC |
651 | #define SDIO_SEND_PME_EN 0x80 |
| 652 | #define FORCE_RC_MODE_ON 0x40 | |
| 653 | #define FORCE_RX50_LINK_ON 0x20 | |
| 654 | #define D3_DELINK_MODE_EN 0x10 | |
| 655 | #define USE_PESRTB_CTL_DELINK 0x08 | |
| 656 | #define DELAY_PIN_WAKE 0x04 | |
| 657 | #define RESET_PIN_WAKE 0x02 | |
| 658 | #define PM_WAKE_EN 0x01 | |
| 5947c167 WW |
659 | #define PM_CTRL4 0xFF47 |
| 660 | ||
| 5afe8021 RF |
661 | #define RTS5261_FW_CFG0 0xFF54 |
| 662 | #define RTS5261_FW_ENTER_EXPRESS (0x01 << 0) | |
| 663 | ||
| 664 | #define RTS5261_FW_CFG1 0xFF55 | |
| 665 | #define RTS5261_SYS_CLK_SEL_MCU_CLK (0x01 << 7) | |
| 666 | #define RTS5261_CRC_CLK_SEL_MCU_CLK (0x01 << 6) | |
| 667 | #define RTS5261_FAKE_MCU_CLOCK_GATING (0x01 << 5) | |
| 668 | #define RTS5261_MCU_BUS_SEL_MASK (0x01 << 4) | |
| 669 | #define RTS5261_MCU_CLOCK_SEL_MASK (0x03 << 2) | |
| 670 | #define RTS5261_MCU_CLOCK_SEL_16M (0x01 << 2) | |
| 671 | #define RTS5261_MCU_CLOCK_GATING (0x01 << 1) | |
| 672 | #define RTS5261_DRIVER_ENABLE_FW (0x01 << 0) | |
| 673 | ||
| 849a9366 RW |
674 | #define REG_CFG_OOBS_OFF_TIMER 0xFEA6 |
| 675 | #define REG_CFG_OOBS_ON_TIMER 0xFEA7 | |
| 676 | #define REG_CFG_VCM_ON_TIMER 0xFEA8 | |
| 677 | #define REG_CFG_OOBS_POLLING 0xFEA9 | |
| 678 | ||
| 67d16a46 WW |
679 | /* Memory mapping */ |
| 680 | #define SRAM_BASE 0xE600 | |
| 681 | #define RBUF_BASE 0xF400 | |
| 682 | #define PPBUF_BASE1 0xF800 | |
| 683 | #define PPBUF_BASE2 0xFA00 | |
| 684 | #define IMAGE_FLAG_ADDR0 0xCE80 | |
| 685 | #define IMAGE_FLAG_ADDR1 0xCE81 | |
| 686 | ||
| 663c425f MC |
687 | #define RREF_CFG 0xFF6C |
| 688 | #define RREF_VBGSEL_MASK 0x38 | |
| 689 | #define RREF_VBGSEL_1V25 0x28 | |
| 690 | ||
| 691 | #define OOBS_CONFIG 0xFF6E | |
| 692 | #define OOBS_AUTOK_DIS 0x80 | |
| 693 | #define OOBS_VAL_MASK 0x1F | |
| 694 | ||
| 695 | #define LDO_DV18_CFG 0xFF70 | |
| 696 | #define LDO_DV18_SR_MASK 0xC0 | |
| 697 | #define LDO_DV18_SR_DF 0x40 | |
| 5da4e04a RF |
698 | #define DV331812_MASK 0x70 |
| 699 | #define DV331812_33 0x70 | |
| 700 | #define DV331812_17 0x30 | |
| 663c425f MC |
701 | |
| 702 | #define LDO_CONFIG2 0xFF71 | |
| 703 | #define LDO_D3318_MASK 0x07 | |
| 704 | #define LDO_D3318_33V 0x07 | |
| 705 | #define LDO_D3318_18V 0x02 | |
| 5da4e04a RF |
706 | #define DV331812_VDD1 0x04 |
| 707 | #define DV331812_POWERON 0x08 | |
| 708 | #define DV331812_POWEROFF 0x00 | |
| 663c425f MC |
709 | |
| 710 | #define LDO_VCC_CFG0 0xFF72 | |
| 711 | #define LDO_VCC_LMTVTH_MASK 0x30 | |
| 712 | #define LDO_VCC_LMTVTH_2A 0x10 | |
| 5da4e04a RF |
713 | /*RTS5260*/ |
| 714 | #define RTS5260_DVCC_TUNE_MASK 0x70 | |
| 715 | #define RTS5260_DVCC_33 0x70 | |
| 663c425f | 716 | |
| 5afe8021 RF |
717 | /*RTS5261*/ |
| 718 | #define RTS5261_LDO1_CFG0 0xFF72 | |
| 719 | #define RTS5261_LDO1_OCP_THD_MASK (0x07 << 5) | |
| 720 | #define RTS5261_LDO1_OCP_EN (0x01 << 4) | |
| 721 | #define RTS5261_LDO1_OCP_LMT_THD_MASK (0x03 << 2) | |
| 722 | #define RTS5261_LDO1_OCP_LMT_EN (0x01 << 1) | |
| 723 | ||
| 663c425f MC |
724 | #define LDO_VCC_CFG1 0xFF73 |
| 725 | #define LDO_VCC_REF_TUNE_MASK 0x30 | |
| 726 | #define LDO_VCC_REF_1V2 0x20 | |
| 727 | #define LDO_VCC_TUNE_MASK 0x07 | |
| 728 | #define LDO_VCC_1V8 0x04 | |
| 729 | #define LDO_VCC_3V3 0x07 | |
| 730 | #define LDO_VCC_LMT_EN 0x08 | |
| 5da4e04a RF |
731 | /*RTS5260*/ |
| 732 | #define LDO_POW_SDVDD1_MASK 0x08 | |
| 733 | #define LDO_POW_SDVDD1_ON 0x08 | |
| 734 | #define LDO_POW_SDVDD1_OFF 0x00 | |
| 663c425f MC |
735 | |
| 736 | #define LDO_VIO_CFG 0xFF75 | |
| 737 | #define LDO_VIO_SR_MASK 0xC0 | |
| 738 | #define LDO_VIO_SR_DF 0x40 | |
| 739 | #define LDO_VIO_REF_TUNE_MASK 0x30 | |
| 740 | #define LDO_VIO_REF_1V2 0x20 | |
| 741 | #define LDO_VIO_TUNE_MASK 0x07 | |
| 742 | #define LDO_VIO_1V7 0x03 | |
| 743 | #define LDO_VIO_1V8 0x04 | |
| 744 | #define LDO_VIO_3V3 0x07 | |
| 745 | ||
| 746 | #define LDO_DV12S_CFG 0xFF76 | |
| 747 | #define LDO_REF12_TUNE_MASK 0x18 | |
| 748 | #define LDO_REF12_TUNE_DF 0x10 | |
| 749 | #define LDO_D12_TUNE_MASK 0x07 | |
| 750 | #define LDO_D12_TUNE_DF 0x04 | |
| 751 | ||
| 752 | #define LDO_AV12S_CFG 0xFF77 | |
| 753 | #define LDO_AV12S_TUNE_MASK 0x07 | |
| 754 | #define LDO_AV12S_TUNE_DF 0x04 | |
| 755 | ||
| 756 | #define SD40_LDO_CTL1 0xFE7D | |
| 757 | #define SD40_VIO_TUNE_MASK 0x70 | |
| 758 | #define SD40_VIO_TUNE_1V7 0x30 | |
| 759 | #define SD_VIO_LDO_1V8 0x40 | |
| 760 | #define SD_VIO_LDO_3V3 0x70 | |
| 761 | ||
| 5da4e04a RF |
762 | #define RTS5260_AUTOLOAD_CFG4 0xFF7F |
| 763 | #define RTS5260_MIMO_DISABLE 0x8A | |
| 5afe8021 RF |
764 | /*RTS5261*/ |
| 765 | #define RTS5261_AUX_CLK_16M_EN (1 << 5) | |
| 5da4e04a RF |
766 | |
| 767 | #define RTS5260_REG_GPIO_CTL0 0xFC1A | |
| 768 | #define RTS5260_REG_GPIO_MASK 0x01 | |
| 769 | #define RTS5260_REG_GPIO_ON 0x01 | |
| 770 | #define RTS5260_REG_GPIO_OFF 0x00 | |
| 771 | ||
| 772 | #define PWR_GLOBAL_CTRL 0xF200 | |
| 773 | #define PCIE_L1_2_EN 0x0C | |
| 774 | #define PCIE_L1_1_EN 0x0A | |
| 775 | #define PCIE_L1_0_EN 0x09 | |
| 776 | #define PWR_FE_CTL 0xF201 | |
| 777 | #define PCIE_L1_2_PD_FE_EN 0x0C | |
| 778 | #define PCIE_L1_1_PD_FE_EN 0x0A | |
| 779 | #define PCIE_L1_0_PD_FE_EN 0x09 | |
| 780 | #define CFG_PCIE_APHY_OFF_0 0xF204 | |
| 781 | #define CFG_PCIE_APHY_OFF_0_DEFAULT 0xBF | |
| 782 | #define CFG_PCIE_APHY_OFF_1 0xF205 | |
| 783 | #define CFG_PCIE_APHY_OFF_1_DEFAULT 0xFF | |
| 784 | #define CFG_PCIE_APHY_OFF_2 0xF206 | |
| 785 | #define CFG_PCIE_APHY_OFF_2_DEFAULT 0x01 | |
| 786 | #define CFG_PCIE_APHY_OFF_3 0xF207 | |
| 787 | #define CFG_PCIE_APHY_OFF_3_DEFAULT 0x00 | |
| 788 | #define CFG_L1_0_PCIE_MAC_RET_VALUE 0xF20C | |
| 789 | #define CFG_L1_0_PCIE_DPHY_RET_VALUE 0xF20E | |
| 790 | #define CFG_L1_0_SYS_RET_VALUE 0xF210 | |
| 791 | #define CFG_L1_0_CRC_MISC_RET_VALUE 0xF212 | |
| 792 | #define CFG_L1_0_CRC_SD30_RET_VALUE 0xF214 | |
| 793 | #define CFG_L1_0_CRC_SD40_RET_VALUE 0xF216 | |
| 794 | #define CFG_LP_FPWM_VALUE 0xF219 | |
| 795 | #define CFG_LP_FPWM_VALUE_DEFAULT 0x18 | |
| 796 | #define PWC_CDR 0xF253 | |
| 797 | #define PWC_CDR_DEFAULT 0x03 | |
| 798 | #define CFG_L1_0_RET_VALUE_DEFAULT 0x1B | |
| 799 | #define CFG_L1_0_CRC_MISC_RET_VALUE_DEFAULT 0x0C | |
| 800 | ||
| 801 | /* OCPCTL */ | |
| 802 | #define SD_DETECT_EN 0x08 | |
| 803 | #define SD_OCP_INT_EN 0x04 | |
| 804 | #define SD_OCP_INT_CLR 0x02 | |
| 805 | #define SD_OC_CLR 0x01 | |
| 806 | ||
| 807 | #define SDVIO_DETECT_EN (1 << 7) | |
| 808 | #define SDVIO_OCP_INT_EN (1 << 6) | |
| 809 | #define SDVIO_OCP_INT_CLR (1 << 5) | |
| 810 | #define SDVIO_OC_CLR (1 << 4) | |
| 811 | ||
| 812 | /* OCPSTAT */ | |
| 813 | #define SD_OCP_DETECT 0x08 | |
| 814 | #define SD_OC_NOW 0x04 | |
| 815 | #define SD_OC_EVER 0x02 | |
| 816 | ||
| 817 | #define SDVIO_OC_NOW (1 << 6) | |
| 818 | #define SDVIO_OC_EVER (1 << 5) | |
| 819 | ||
| 820 | #define REG_OCPCTL 0xFD6A | |
| 821 | #define REG_OCPSTAT 0xFD6E | |
| 822 | #define REG_OCPGLITCH 0xFD6C | |
| 823 | #define REG_OCPPARA1 0xFD6B | |
| 824 | #define REG_OCPPARA2 0xFD6D | |
| 825 | ||
| 826 | /* rts5260 DV3318 OCP-related registers */ | |
| 827 | #define REG_DV3318_OCPCTL 0xFD89 | |
| 828 | #define DV3318_OCP_TIME_MASK 0xF0 | |
| 829 | #define DV3318_DETECT_EN 0x08 | |
| 830 | #define DV3318_OCP_INT_EN 0x04 | |
| 831 | #define DV3318_OCP_INT_CLR 0x02 | |
| 832 | #define DV3318_OCP_CLR 0x01 | |
| 833 | ||
| 834 | #define REG_DV3318_OCPSTAT 0xFD8A | |
| 835 | #define DV3318_OCP_GlITCH_TIME_MASK 0xF0 | |
| 836 | #define DV3318_OCP_DETECT 0x08 | |
| 837 | #define DV3318_OCP_NOW 0x04 | |
| 838 | #define DV3318_OCP_EVER 0x02 | |
| 839 | ||
| 840 | #define SD_OCP_GLITCH_MASK 0x0F | |
| 841 | ||
| 842 | /* OCPPARA1 */ | |
| 843 | #define SDVIO_OCP_TIME_60 0x00 | |
| 844 | #define SDVIO_OCP_TIME_100 0x10 | |
| 845 | #define SDVIO_OCP_TIME_200 0x20 | |
| 846 | #define SDVIO_OCP_TIME_400 0x30 | |
| 847 | #define SDVIO_OCP_TIME_600 0x40 | |
| 848 | #define SDVIO_OCP_TIME_800 0x50 | |
| 849 | #define SDVIO_OCP_TIME_1100 0x60 | |
| 850 | #define SDVIO_OCP_TIME_MASK 0x70 | |
| 851 | ||
| 852 | #define SD_OCP_TIME_60 0x00 | |
| 853 | #define SD_OCP_TIME_100 0x01 | |
| 854 | #define SD_OCP_TIME_200 0x02 | |
| 855 | #define SD_OCP_TIME_400 0x03 | |
| 856 | #define SD_OCP_TIME_600 0x04 | |
| 857 | #define SD_OCP_TIME_800 0x05 | |
| 858 | #define SD_OCP_TIME_1100 0x06 | |
| 859 | #define SD_OCP_TIME_MASK 0x07 | |
| 860 | ||
| 861 | /* OCPPARA2 */ | |
| 862 | #define SDVIO_OCP_THD_190 0x00 | |
| 863 | #define SDVIO_OCP_THD_250 0x10 | |
| 864 | #define SDVIO_OCP_THD_320 0x20 | |
| 865 | #define SDVIO_OCP_THD_380 0x30 | |
| 866 | #define SDVIO_OCP_THD_440 0x40 | |
| 867 | #define SDVIO_OCP_THD_500 0x50 | |
| 868 | #define SDVIO_OCP_THD_570 0x60 | |
| 869 | #define SDVIO_OCP_THD_630 0x70 | |
| 870 | #define SDVIO_OCP_THD_MASK 0x70 | |
| 871 | ||
| 872 | #define SD_OCP_THD_450 0x00 | |
| 873 | #define SD_OCP_THD_550 0x01 | |
| 874 | #define SD_OCP_THD_650 0x02 | |
| 875 | #define SD_OCP_THD_750 0x03 | |
| 876 | #define SD_OCP_THD_850 0x04 | |
| 877 | #define SD_OCP_THD_950 0x05 | |
| 878 | #define SD_OCP_THD_1050 0x06 | |
| 879 | #define SD_OCP_THD_1150 0x07 | |
| 880 | #define SD_OCP_THD_MASK 0x07 | |
| 881 | ||
| 882 | #define SDVIO_OCP_GLITCH_MASK 0xF0 | |
| 883 | #define SDVIO_OCP_GLITCH_NONE 0x00 | |
| 884 | #define SDVIO_OCP_GLITCH_50U 0x10 | |
| 885 | #define SDVIO_OCP_GLITCH_100U 0x20 | |
| 886 | #define SDVIO_OCP_GLITCH_200U 0x30 | |
| 887 | #define SDVIO_OCP_GLITCH_600U 0x40 | |
| 888 | #define SDVIO_OCP_GLITCH_800U 0x50 | |
| 889 | #define SDVIO_OCP_GLITCH_1M 0x60 | |
| 890 | #define SDVIO_OCP_GLITCH_2M 0x70 | |
| 891 | #define SDVIO_OCP_GLITCH_3M 0x80 | |
| 892 | #define SDVIO_OCP_GLITCH_4M 0x90 | |
| 893 | #define SDVIO_OCP_GLIVCH_5M 0xA0 | |
| 894 | #define SDVIO_OCP_GLITCH_6M 0xB0 | |
| 895 | #define SDVIO_OCP_GLITCH_7M 0xC0 | |
| 896 | #define SDVIO_OCP_GLITCH_8M 0xD0 | |
| 897 | #define SDVIO_OCP_GLITCH_9M 0xE0 | |
| 898 | #define SDVIO_OCP_GLITCH_10M 0xF0 | |
| 899 | ||
| 900 | #define SD_OCP_GLITCH_MASK 0x0F | |
| 901 | #define SD_OCP_GLITCH_NONE 0x00 | |
| 902 | #define SD_OCP_GLITCH_50U 0x01 | |
| 903 | #define SD_OCP_GLITCH_100U 0x02 | |
| 904 | #define SD_OCP_GLITCH_200U 0x03 | |
| 905 | #define SD_OCP_GLITCH_600U 0x04 | |
| 906 | #define SD_OCP_GLITCH_800U 0x05 | |
| 907 | #define SD_OCP_GLITCH_1M 0x06 | |
| 908 | #define SD_OCP_GLITCH_2M 0x07 | |
| 909 | #define SD_OCP_GLITCH_3M 0x08 | |
| 910 | #define SD_OCP_GLITCH_4M 0x09 | |
| 911 | #define SD_OCP_GLIVCH_5M 0x0A | |
| 912 | #define SD_OCP_GLITCH_6M 0x0B | |
| 913 | #define SD_OCP_GLITCH_7M 0x0C | |
| 914 | #define SD_OCP_GLITCH_8M 0x0D | |
| 915 | #define SD_OCP_GLITCH_9M 0x0E | |
| 916 | #define SD_OCP_GLITCH_10M 0x0F | |
| 917 | ||
| 4c4b8c10 WW |
918 | /* Phy register */ |
| 919 | #define PHY_PCR 0x00 | |
| b0385381 MC |
920 | #define PHY_PCR_FORCE_CODE 0xB000 |
| 921 | #define PHY_PCR_OOBS_CALI_50 0x0800 | |
| 922 | #define PHY_PCR_OOBS_VCM_08 0x0200 | |
| 923 | #define PHY_PCR_OOBS_SEN_90 0x0040 | |
| 924 | #define PHY_PCR_RSSI_EN 0x0002 | |
| 925 | #define PHY_PCR_RX10K 0x0001 | |
| 926 | ||
| 4c4b8c10 WW |
927 | #define PHY_RCR0 0x01 |
| 928 | #define PHY_RCR1 0x02 | |
| b0385381 MC |
929 | #define PHY_RCR1_ADP_TIME_4 0x0400 |
| 930 | #define PHY_RCR1_VCO_COARSE 0x001F | |
| ce6a5acc | 931 | #define PHY_RCR1_INIT_27S 0x0A1F |
| 663c425f MC |
932 | #define PHY_SSCCR2 0x02 |
| 933 | #define PHY_SSCCR2_PLL_NCODE 0x0A00 | |
| 934 | #define PHY_SSCCR2_TIME0 0x001C | |
| 935 | #define PHY_SSCCR2_TIME2_WIDTH 0x0003 | |
| b0385381 | 936 | |
| 4c4b8c10 | 937 | #define PHY_RCR2 0x03 |
| b0385381 MC |
938 | #define PHY_RCR2_EMPHASE_EN 0x8000 |
| 939 | #define PHY_RCR2_NADJR 0x4000 | |
| 940 | #define PHY_RCR2_CDR_SR_2 0x0100 | |
| 941 | #define PHY_RCR2_FREQSEL_12 0x0040 | |
| 942 | #define PHY_RCR2_CDR_SC_12P 0x0010 | |
| 943 | #define PHY_RCR2_CALIB_LATE 0x0002 | |
| ce6a5acc | 944 | #define PHY_RCR2_INIT_27S 0xC152 |
| 663c425f MC |
945 | #define PHY_SSCCR3 0x03 |
| 946 | #define PHY_SSCCR3_STEP_IN 0x2740 | |
| 947 | #define PHY_SSCCR3_CHECK_DELAY 0x0008 | |
| 41bc2334 MC |
948 | #define _PHY_ANA03 0x03 |
| 949 | #define _PHY_ANA03_TIMER_MAX 0x2700 | |
| 950 | #define _PHY_ANA03_OOBS_DEB_EN 0x0040 | |
| 951 | #define _PHY_CMU_DEBUG_EN 0x0008 | |
| b0385381 | 952 | |
| 4c4b8c10 WW |
953 | #define PHY_RTCR 0x04 |
| 954 | #define PHY_RDR 0x05 | |
| b0385381 MC |
955 | #define PHY_RDR_RXDSEL_1_9 0x4000 |
| 956 | #define PHY_SSC_AUTO_PWD 0x0600 | |
| 4c4b8c10 WW |
957 | #define PHY_TCR0 0x06 |
| 958 | #define PHY_TCR1 0x07 | |
| 959 | #define PHY_TUNE 0x08 | |
| b0385381 MC |
960 | #define PHY_TUNE_TUNEREF_1_0 0x4000 |
| 961 | #define PHY_TUNE_VBGSEL_1252 0x0C00 | |
| 962 | #define PHY_TUNE_SDBUS_33 0x0200 | |
| 963 | #define PHY_TUNE_TUNED18 0x01C0 | |
| 964 | #define PHY_TUNE_TUNED12 0X0020 | |
| 965 | #define PHY_TUNE_TUNEA12 0x0004 | |
| 663c425f MC |
966 | #define PHY_TUNE_VOLTAGE_MASK 0xFC3F |
| 967 | #define PHY_TUNE_VOLTAGE_3V3 0x03C0 | |
| 968 | #define PHY_TUNE_D18_1V8 0x0100 | |
| 969 | #define PHY_TUNE_D18_1V7 0x0080 | |
| 970 | #define PHY_ANA08 0x08 | |
| 971 | #define PHY_ANA08_RX_EQ_DCGAIN 0x5000 | |
| 972 | #define PHY_ANA08_SEL_RX_EN 0x0400 | |
| 973 | #define PHY_ANA08_RX_EQ_VAL 0x03C0 | |
| 974 | #define PHY_ANA08_SCP 0x0020 | |
| 975 | #define PHY_ANA08_SEL_IPI 0x0004 | |
| b0385381 | 976 | |
| 4c4b8c10 WW |
977 | #define PHY_IMR 0x09 |
| 978 | #define PHY_BPCR 0x0A | |
| b0385381 MC |
979 | #define PHY_BPCR_IBRXSEL 0x0400 |
| 980 | #define PHY_BPCR_IBTXSEL 0x0100 | |
| 981 | #define PHY_BPCR_IB_FILTER 0x0080 | |
| 982 | #define PHY_BPCR_CMIRROR_EN 0x0040 | |
| 983 | ||
| 4c4b8c10 WW |
984 | #define PHY_BIST 0x0B |
| 985 | #define PHY_RAW_L 0x0C | |
| 986 | #define PHY_RAW_H 0x0D | |
| 987 | #define PHY_RAW_DATA 0x0E | |
| 988 | #define PHY_HOST_CLK_CTRL 0x0F | |
| 989 | #define PHY_DMR 0x10 | |
| 990 | #define PHY_BACR 0x11 | |
| 663c425f | 991 | #define PHY_BACR_BASIC_MASK 0xFFF3 |
| 4c4b8c10 WW |
992 | #define PHY_IER 0x12 |
| 993 | #define PHY_BCSR 0x13 | |
| 994 | #define PHY_BPR 0x14 | |
| 995 | #define PHY_BPNR2 0x15 | |
| 996 | #define PHY_BPNR 0x16 | |
| 997 | #define PHY_BRNR2 0x17 | |
| 998 | #define PHY_BENR 0x18 | |
| b0385381 MC |
999 | #define PHY_REV 0x19 |
| 1000 | #define PHY_REV_RESV 0xE000 | |
| 1001 | #define PHY_REV_RXIDLE_LATCHED 0x1000 | |
| 1002 | #define PHY_REV_P1_EN 0x0800 | |
| 1003 | #define PHY_REV_RXIDLE_EN 0x0400 | |
| 1004 | #define PHY_REV_CLKREQ_TX_EN 0x0200 | |
| 1005 | #define PHY_REV_CLKREQ_RX_EN 0x0100 | |
| 1006 | #define PHY_REV_CLKREQ_DT_1_0 0x0040 | |
| 1007 | #define PHY_REV_STOP_CLKRD 0x0020 | |
| 1008 | #define PHY_REV_RX_PWST 0x0008 | |
| 1009 | #define PHY_REV_STOP_CLKWR 0x0004 | |
| 41bc2334 MC |
1010 | #define _PHY_REV0 0x19 |
| 1011 | #define _PHY_REV0_FILTER_OUT 0x3800 | |
| 1012 | #define _PHY_REV0_CDR_BYPASS_PFD 0x0100 | |
| 1013 | #define _PHY_REV0_CDR_RX_IDLE_BYPASS 0x0002 | |
| b0385381 | 1014 | |
| 4c4b8c10 | 1015 | #define PHY_FLD0 0x1A |
| 663c425f MC |
1016 | #define PHY_ANA1A 0x1A |
| 1017 | #define PHY_ANA1A_TXR_LOOPBACK 0x2000 | |
| 1018 | #define PHY_ANA1A_RXT_BIST 0x0500 | |
| 1019 | #define PHY_ANA1A_TXR_BIST 0x0040 | |
| 1020 | #define PHY_ANA1A_REV 0x0006 | |
| ce6a5acc | 1021 | #define PHY_FLD0_INIT_27S 0x2546 |
| 4c4b8c10 WW |
1022 | #define PHY_FLD1 0x1B |
| 1023 | #define PHY_FLD2 0x1C | |
| 1024 | #define PHY_FLD3 0x1D | |
| b0385381 MC |
1025 | #define PHY_FLD3_TIMER_4 0x0800 |
| 1026 | #define PHY_FLD3_TIMER_6 0x0020 | |
| 1027 | #define PHY_FLD3_RXDELINK 0x0004 | |
| ce6a5acc | 1028 | #define PHY_FLD3_INIT_27S 0x0004 |
| 663c425f MC |
1029 | #define PHY_ANA1D 0x1D |
| 1030 | #define PHY_ANA1D_DEBUG_ADDR 0x0004 | |
| 41bc2334 MC |
1031 | #define _PHY_FLD0 0x1D |
| 1032 | #define _PHY_FLD0_CLK_REQ_20C 0x8000 | |
| 1033 | #define _PHY_FLD0_RX_IDLE_EN 0x1000 | |
| 1034 | #define _PHY_FLD0_BIT_ERR_RSTN 0x0800 | |
| 1035 | #define _PHY_FLD0_BER_COUNT 0x01E0 | |
| 1036 | #define _PHY_FLD0_BER_TIMER 0x001E | |
| 1037 | #define _PHY_FLD0_CHECK_EN 0x0001 | |
| b0385381 | 1038 | |
| 4c4b8c10 | 1039 | #define PHY_FLD4 0x1E |
| b0385381 MC |
1040 | #define PHY_FLD4_FLDEN_SEL 0x4000 |
| 1041 | #define PHY_FLD4_REQ_REF 0x2000 | |
| 1042 | #define PHY_FLD4_RXAMP_OFF 0x1000 | |
| 1043 | #define PHY_FLD4_REQ_ADDA 0x0800 | |
| 1044 | #define PHY_FLD4_BER_COUNT 0x00E0 | |
| 1045 | #define PHY_FLD4_BER_TIMER 0x000A | |
| 1046 | #define PHY_FLD4_BER_CHK_EN 0x0001 | |
| ce6a5acc | 1047 | #define PHY_FLD4_INIT_27S 0x5C7F |
| 663c425f MC |
1048 | #define PHY_DIG1E 0x1E |
| 1049 | #define PHY_DIG1E_REV 0x4000 | |
| 1050 | #define PHY_DIG1E_D0_X_D1 0x1000 | |
| 1051 | #define PHY_DIG1E_RX_ON_HOST 0x0800 | |
| 1052 | #define PHY_DIG1E_RCLK_REF_HOST 0x0400 | |
| 1053 | #define PHY_DIG1E_RCLK_TX_EN_KEEP 0x0040 | |
| 1054 | #define PHY_DIG1E_RCLK_TX_TERM_KEEP 0x0020 | |
| 1055 | #define PHY_DIG1E_RCLK_RX_EIDLE_ON 0x0010 | |
| 1056 | #define PHY_DIG1E_TX_TERM_KEEP 0x0008 | |
| 1057 | #define PHY_DIG1E_RX_TERM_KEEP 0x0004 | |
| 1058 | #define PHY_DIG1E_TX_EN_KEEP 0x0002 | |
| 1059 | #define PHY_DIG1E_RX_EN_KEEP 0x0001 | |
| 4c4b8c10 WW |
1060 | #define PHY_DUM_REG 0x1F |
| 1061 | ||
| 773ccdfd WW |
1062 | #define PCR_SETTING_REG1 0x724 |
| 1063 | #define PCR_SETTING_REG2 0x814 | |
| 1064 | #define PCR_SETTING_REG3 0x747 | |
| 1065 | ||
| 67d16a46 WW |
1066 | #define rtsx_pci_init_cmd(pcr) ((pcr)->ci = 0) |
| 1067 | ||
| 87d28444 SF |
1068 | #define RTS5227_DEVICE_ID 0x5227 |
| 1069 | #define RTS_MAX_TIMES_FREQ_REDUCTION 8 | |
| 1070 | ||
| 67d16a46 WW |
1071 | struct rtsx_pcr; |
| 1072 | ||
| 1073 | struct pcr_handle { | |
| 1074 | struct rtsx_pcr *pcr; | |
| 1075 | }; | |
| 1076 | ||
| 1077 | struct pcr_ops { | |
| 663c425f MC |
1078 | int (*write_phy)(struct rtsx_pcr *pcr, u8 addr, u16 val); |
| 1079 | int (*read_phy)(struct rtsx_pcr *pcr, u8 addr, u16 *val); | |
| 67d16a46 WW |
1080 | int (*extra_init_hw)(struct rtsx_pcr *pcr); |
| 1081 | int (*optimize_phy)(struct rtsx_pcr *pcr); | |
| 1082 | int (*turn_on_led)(struct rtsx_pcr *pcr); | |
| 1083 | int (*turn_off_led)(struct rtsx_pcr *pcr); | |
| 1084 | int (*enable_auto_blink)(struct rtsx_pcr *pcr); | |
| 1085 | int (*disable_auto_blink)(struct rtsx_pcr *pcr); | |
| 1086 | int (*card_power_on)(struct rtsx_pcr *pcr, int card); | |
| 1087 | int (*card_power_off)(struct rtsx_pcr *pcr, int card); | |
| d817ac4e WW |
1088 | int (*switch_output_voltage)(struct rtsx_pcr *pcr, |
| 1089 | u8 voltage); | |
| 67d16a46 | 1090 | unsigned int (*cd_deglitch)(struct rtsx_pcr *pcr); |
| ab4e8f8b | 1091 | int (*conv_clk_and_div_n)(int clk, int dir); |
| 773ccdfd | 1092 | void (*fetch_vendor_settings)(struct rtsx_pcr *pcr); |
| eb891c65 | 1093 | void (*force_power_down)(struct rtsx_pcr *pcr, u8 pm_state); |
| 5da4e04a | 1094 | void (*stop_cmd)(struct rtsx_pcr *pcr); |
| 8275b77a RF |
1095 | |
| 1096 | void (*set_aspm)(struct rtsx_pcr *pcr, bool enable); | |
| 8275b77a | 1097 | void (*set_l1off_cfg_sub_d0)(struct rtsx_pcr *pcr, int active); |
| 5da4e04a RF |
1098 | void (*enable_ocp)(struct rtsx_pcr *pcr); |
| 1099 | void (*disable_ocp)(struct rtsx_pcr *pcr); | |
| 1100 | void (*init_ocp)(struct rtsx_pcr *pcr); | |
| 1101 | void (*process_ocp)(struct rtsx_pcr *pcr); | |
| 1102 | int (*get_ocpstat)(struct rtsx_pcr *pcr, u8 *val); | |
| 1103 | void (*clear_ocpstat)(struct rtsx_pcr *pcr); | |
| 67d16a46 WW |
1104 | }; |
| 1105 | ||
| 1106 | enum PDEV_STAT {PDEV_STAT_IDLE, PDEV_STAT_RUN}; | |
| 1107 | ||
| 8275b77a RF |
1108 | #define ASPM_L1_1_EN BIT(0) |
| 1109 | #define ASPM_L1_2_EN BIT(1) | |
| 1110 | #define PM_L1_1_EN BIT(2) | |
| 1111 | #define PM_L1_2_EN BIT(3) | |
| 1112 | #define LTR_L1SS_PWR_GATE_EN BIT(4) | |
| 1113 | #define L1_SNOOZE_TEST_EN BIT(5) | |
| 1114 | #define LTR_L1SS_PWR_GATE_CHECK_CARD_EN BIT(6) | |
| 1115 | ||
| 8275b77a RF |
1116 | /* |
| 1117 | * struct rtsx_cr_option - card reader option | |
| 1118 | * @dev_flags: device flags | |
| 1119 | * @force_clkreq_0: force clock request | |
| 1120 | * @ltr_en: enable ltr mode flag | |
| 1121 | * @ltr_enabled: ltr mode in configure space flag | |
| 1122 | * @ltr_active: ltr mode status | |
| 1123 | * @ltr_active_latency: ltr mode active latency | |
| 1124 | * @ltr_idle_latency: ltr mode idle latency | |
| 1125 | * @ltr_l1off_latency: ltr mode l1off latency | |
| 8275b77a RF |
1126 | * @l1_snooze_delay: l1 snooze delay |
| 1127 | * @ltr_l1off_sspwrgate: ltr l1off sspwrgate | |
| 1128 | * @ltr_l1off_snooze_sspwrgate: ltr l1off snooze sspwrgate | |
| 5da4e04a RF |
1129 | * @ocp_en: enable ocp flag |
| 1130 | * @sd_400mA_ocp_thd: 400mA ocp thd | |
| 1131 | * @sd_800mA_ocp_thd: 800mA ocp thd | |
| 8275b77a RF |
1132 | */ |
| 1133 | struct rtsx_cr_option { | |
| 1134 | u32 dev_flags; | |
| 1135 | bool force_clkreq_0; | |
| 1136 | bool ltr_en; | |
| 1137 | bool ltr_enabled; | |
| 1138 | bool ltr_active; | |
| 1139 | u32 ltr_active_latency; | |
| 1140 | u32 ltr_idle_latency; | |
| 1141 | u32 ltr_l1off_latency; | |
| 8275b77a RF |
1142 | u32 l1_snooze_delay; |
| 1143 | u8 ltr_l1off_sspwrgate; | |
| 1144 | u8 ltr_l1off_snooze_sspwrgate; | |
| 5da4e04a RF |
1145 | bool ocp_en; |
| 1146 | u8 sd_400mA_ocp_thd; | |
| 1147 | u8 sd_800mA_ocp_thd; | |
| 1148 | }; | |
| 1149 | ||
| 1150 | /* | |
| 1151 | * struct rtsx_hw_param - card reader hardware param | |
| 1152 | * @interrupt_en: indicate which interrutp enable | |
| 1153 | * @ocp_glitch: ocp glitch time | |
| 1154 | */ | |
| 1155 | struct rtsx_hw_param { | |
| 1156 | u32 interrupt_en; | |
| 1157 | u8 ocp_glitch; | |
| 8275b77a RF |
1158 | }; |
| 1159 | ||
| 1160 | #define rtsx_set_dev_flag(cr, flag) \ | |
| 1161 | ((cr)->option.dev_flags |= (flag)) | |
| 1162 | #define rtsx_clear_dev_flag(cr, flag) \ | |
| 1163 | ((cr)->option.dev_flags &= ~(flag)) | |
| 1164 | #define rtsx_check_dev_flag(cr, flag) \ | |
| 1165 | ((cr)->option.dev_flags & (flag)) | |
| 1166 | ||
| 67d16a46 WW |
1167 | struct rtsx_pcr { |
| 1168 | struct pci_dev *pci; | |
| 1169 | unsigned int id; | |
| 8275b77a | 1170 | struct rtsx_cr_option option; |
| 5da4e04a | 1171 | struct rtsx_hw_param hw_param; |
| 67d16a46 WW |
1172 | |
| 1173 | /* pci resources */ | |
| 1174 | unsigned long addr; | |
| 1175 | void __iomem *remap_addr; | |
| 1176 | int irq; | |
| 1177 | ||
| 1178 | /* host reserved buffer */ | |
| 1179 | void *rtsx_resv_buf; | |
| 1180 | dma_addr_t rtsx_resv_buf_addr; | |
| 1181 | ||
| 1182 | void *host_cmds_ptr; | |
| 1183 | dma_addr_t host_cmds_addr; | |
| 1184 | int ci; | |
| 1185 | ||
| 1186 | void *host_sg_tbl_ptr; | |
| 1187 | dma_addr_t host_sg_tbl_addr; | |
| 1188 | int sgi; | |
| 1189 | ||
| 1190 | u32 bier; | |
| 1191 | char trans_result; | |
| 1192 | ||
| 1193 | unsigned int card_inserted; | |
| 1194 | unsigned int card_removed; | |
| c3481955 | 1195 | unsigned int card_exist; |
| 67d16a46 WW |
1196 | |
| 1197 | struct delayed_work carddet_work; | |
| 1198 | struct delayed_work idle_work; | |
| 1199 | ||
| 1200 | spinlock_t lock; | |
| 1201 | struct mutex pcr_mutex; | |
| 1202 | struct completion *done; | |
| 1203 | struct completion *finish_me; | |
| 1204 | ||
| 1205 | unsigned int cur_clock; | |
| 67d16a46 WW |
1206 | bool remove_pci; |
| 1207 | bool msi_en; | |
| 1208 | ||
| 1209 | #define EXTRA_CAPS_SD_SDR50 (1 << 0) | |
| 1210 | #define EXTRA_CAPS_SD_SDR104 (1 << 1) | |
| 1211 | #define EXTRA_CAPS_SD_DDR50 (1 << 2) | |
| 1212 | #define EXTRA_CAPS_MMC_HSDDR (1 << 3) | |
| 1213 | #define EXTRA_CAPS_MMC_HS200 (1 << 4) | |
| 1214 | #define EXTRA_CAPS_MMC_8BIT (1 << 5) | |
| 849a9366 | 1215 | #define EXTRA_CAPS_NO_MMC (1 << 7) |
| 5afe8021 | 1216 | #define EXTRA_CAPS_SD_EXPRESS (1 << 8) |
| 67d16a46 WW |
1217 | u32 extra_caps; |
| 1218 | ||
| 1219 | #define IC_VER_A 0 | |
| 1220 | #define IC_VER_B 1 | |
| 1221 | #define IC_VER_C 2 | |
| 1222 | #define IC_VER_D 3 | |
| 1223 | u8 ic_version; | |
| 1224 | ||
| 773ccdfd WW |
1225 | u8 sd30_drive_sel_1v8; |
| 1226 | u8 sd30_drive_sel_3v3; | |
| 1227 | u8 card_drive_sel; | |
| 1228 | #define ASPM_L1_EN 0x02 | |
| 1229 | u8 aspm_en; | |
| 8275b77a | 1230 | bool aspm_enabled; |
| 773ccdfd WW |
1231 | |
| 1232 | #define PCR_MS_PMOS (1 << 0) | |
| 1233 | #define PCR_REVERSE_SOCKET (1 << 1) | |
| 1234 | u32 flags; | |
| 1235 | ||
| 84d72f9c WW |
1236 | u32 tx_initial_phase; |
| 1237 | u32 rx_initial_phase; | |
| 1238 | ||
| 67d16a46 WW |
1239 | const u32 *sd_pull_ctl_enable_tbl; |
| 1240 | const u32 *sd_pull_ctl_disable_tbl; | |
| 1241 | const u32 *ms_pull_ctl_enable_tbl; | |
| 1242 | const u32 *ms_pull_ctl_disable_tbl; | |
| 1243 | ||
| 1244 | const struct pcr_ops *ops; | |
| 1245 | enum PDEV_STAT state; | |
| 1246 | ||
| 663c425f MC |
1247 | u16 reg_pm_ctrl3; |
| 1248 | ||
| 67d16a46 WW |
1249 | int num_slots; |
| 1250 | struct rtsx_slot *slots; | |
| 87d28444 SF |
1251 | |
| 1252 | u8 dma_error_count; | |
| 5da4e04a RF |
1253 | u8 ocp_stat; |
| 1254 | u8 ocp_stat2; | |
| 849a9366 | 1255 | u8 rtd3_en; |
| 67d16a46 WW |
1256 | }; |
| 1257 | ||
| 8275b77a | 1258 | #define PID_524A 0x524A |
| 5da4e04a RF |
1259 | #define PID_5249 0x5249 |
| 1260 | #define PID_5250 0x5250 | |
| 8275b77a | 1261 | #define PID_525A 0x525A |
| 5da4e04a | 1262 | #define PID_5260 0x5260 |
| c0e5f4e7 | 1263 | #define PID_5261 0x5261 |
| 849a9366 | 1264 | #define PID_5228 0x5228 |
| 8275b77a | 1265 | |
| 67d16a46 WW |
1266 | #define CHK_PCI_PID(pcr, pid) ((pcr)->pci->device == (pid)) |
| 1267 | #define PCI_VID(pcr) ((pcr)->pci->vendor) | |
| 1268 | #define PCI_PID(pcr) ((pcr)->pci->device) | |
| 663c425f MC |
1269 | #define is_version(pcr, pid, ver) \ |
| 1270 | (CHK_PCI_PID(pcr, pid) && (pcr)->ic_version == (ver)) | |
| 1271 | #define pcr_dbg(pcr, fmt, arg...) \ | |
| 1272 | dev_dbg(&(pcr)->pci->dev, fmt, ##arg) | |
| 67d16a46 | 1273 | |
| 84d72f9c WW |
1274 | #define SDR104_PHASE(val) ((val) & 0xFF) |
| 1275 | #define SDR50_PHASE(val) (((val) >> 8) & 0xFF) | |
| 1276 | #define DDR50_PHASE(val) (((val) >> 16) & 0xFF) | |
| 1277 | #define SDR104_TX_PHASE(pcr) SDR104_PHASE((pcr)->tx_initial_phase) | |
| 1278 | #define SDR50_TX_PHASE(pcr) SDR50_PHASE((pcr)->tx_initial_phase) | |
| 1279 | #define DDR50_TX_PHASE(pcr) DDR50_PHASE((pcr)->tx_initial_phase) | |
| 1280 | #define SDR104_RX_PHASE(pcr) SDR104_PHASE((pcr)->rx_initial_phase) | |
| 1281 | #define SDR50_RX_PHASE(pcr) SDR50_PHASE((pcr)->rx_initial_phase) | |
| 1282 | #define DDR50_RX_PHASE(pcr) DDR50_PHASE((pcr)->rx_initial_phase) | |
| 1283 | #define SET_CLOCK_PHASE(sdr104, sdr50, ddr50) \ | |
| 1284 | (((ddr50) << 16) | ((sdr50) << 8) | (sdr104)) | |
| 1285 | ||
| 67d16a46 WW |
1286 | void rtsx_pci_start_run(struct rtsx_pcr *pcr); |
| 1287 | int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data); | |
| 1288 | int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data); | |
| 1289 | int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val); | |
| 1290 | int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val); | |
| 1291 | void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr); | |
| 1292 | void rtsx_pci_add_cmd(struct rtsx_pcr *pcr, | |
| 1293 | u8 cmd_type, u16 reg_addr, u8 mask, u8 data); | |
| 1294 | void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr); | |
| 1295 | int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout); | |
| 1296 | int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist, | |
| 1297 | int num_sg, bool read, int timeout); | |
| 8cd11830 MC |
1298 | int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist, |
| 1299 | int num_sg, bool read); | |
| 1300 | void rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist, | |
| 1301 | int num_sg, bool read); | |
| 1302 | int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist, | |
| 1303 | int count, bool read, int timeout); | |
| 67d16a46 WW |
1304 | int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len); |
| 1305 | int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len); | |
| 1306 | int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card); | |
| 1307 | int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card); | |
| 1308 | int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, | |
| 1309 | u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk); | |
| 1310 | int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card); | |
| 1311 | int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card); | |
| c3481955 | 1312 | int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card); |
| d817ac4e | 1313 | int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage); |
| 67d16a46 WW |
1314 | unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr); |
| 1315 | void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr); | |
| 1316 | ||
| 1317 | static inline u8 *rtsx_pci_get_cmd_data(struct rtsx_pcr *pcr) | |
| 1318 | { | |
| 1319 | return (u8 *)(pcr->host_cmds_ptr); | |
| 1320 | } | |
| 1321 | ||
| a3b63979 MC |
1322 | static inline void rtsx_pci_write_be32(struct rtsx_pcr *pcr, u16 reg, u32 val) |
| 1323 | { | |
| 1324 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg, 0xFF, val >> 24); | |
| 1325 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 1, 0xFF, val >> 16); | |
| 1326 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 2, 0xFF, val >> 8); | |
| 1327 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 3, 0xFF, val); | |
| 1328 | } | |
| 1329 | ||
| 663c425f MC |
1330 | static inline int rtsx_pci_update_phy(struct rtsx_pcr *pcr, u8 addr, |
| 1331 | u16 mask, u16 append) | |
| 1332 | { | |
| 1333 | int err; | |
| 1334 | u16 val; | |
| 1335 | ||
| 1336 | err = rtsx_pci_read_phy_register(pcr, addr, &val); | |
| 1337 | if (err < 0) | |
| 1338 | return err; | |
| 1339 | ||
| 1340 | return rtsx_pci_write_phy_register(pcr, addr, (val & mask) | append); | |
| 1341 | } | |
| 1342 | ||
| 67d16a46 | 1343 | #endif |