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e79f15a4 CY |
1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | #ifndef _RESCTRL_H | |
3 | #define _RESCTRL_H | |
4 | ||
63c8b123 JM |
5 | #include <linux/kernel.h> |
6 | #include <linux/list.h> | |
a21a4391 JM |
7 | #include <linux/pid.h> |
8 | ||
40fc735b JM |
9 | /* CLOSID, RMID value used by the default control group */ |
10 | #define RESCTRL_RESERVED_CLOSID 0 | |
11 | #define RESCTRL_RESERVED_RMID 0 | |
12 | ||
978fcca9 JM |
13 | #define RESCTRL_PICK_ANY_CPU -1 |
14 | ||
e79f15a4 CY |
15 | #ifdef CONFIG_PROC_CPU_RESCTRL |
16 | ||
17 | int proc_resctrl_show(struct seq_file *m, | |
18 | struct pid_namespace *ns, | |
19 | struct pid *pid, | |
20 | struct task_struct *tsk); | |
21 | ||
22 | #endif | |
23 | ||
781096d9 JM |
24 | /* max value for struct rdt_domain's mbps_val */ |
25 | #define MBA_MAX_MBPS U32_MAX | |
26 | ||
208ab168 JM |
27 | /** |
28 | * enum resctrl_conf_type - The type of configuration. | |
29 | * @CDP_NONE: No prioritisation, both code and data are controlled or monitored. | |
30 | * @CDP_CODE: Configuration applies to instruction fetches. | |
31 | * @CDP_DATA: Configuration applies to reads and writes. | |
32 | */ | |
33 | enum resctrl_conf_type { | |
34 | CDP_NONE, | |
35 | CDP_CODE, | |
36 | CDP_DATA, | |
37 | }; | |
38 | ||
75408e43 JM |
39 | #define CDP_NUM_TYPES (CDP_DATA + 1) |
40 | ||
fea62d37 JM |
41 | /* |
42 | * Event IDs, the values match those used to program IA32_QM_EVTSEL before | |
43 | * reading IA32_QM_CTR on RDT systems. | |
44 | */ | |
45 | enum resctrl_event_id { | |
46 | QOS_L3_OCCUP_EVENT_ID = 0x01, | |
47 | QOS_L3_MBM_TOTAL_EVENT_ID = 0x02, | |
48 | QOS_L3_MBM_LOCAL_EVENT_ID = 0x03, | |
49 | }; | |
50 | ||
e8f72825 JM |
51 | /** |
52 | * struct resctrl_staged_config - parsed configuration to be applied | |
53 | * @new_ctrl: new ctrl value to be loaded | |
54 | * @have_new_ctrl: whether the user provided new_ctrl is valid | |
55 | */ | |
56 | struct resctrl_staged_config { | |
57 | u32 new_ctrl; | |
58 | bool have_new_ctrl; | |
59 | }; | |
60 | ||
792e0f6f JM |
61 | /** |
62 | * struct rdt_domain - group of CPUs sharing a resctrl resource | |
63 | * @list: all instances of this resource | |
64 | * @id: unique id for this instance | |
65 | * @cpu_mask: which CPUs share this resource | |
792e0f6f JM |
66 | * @rmid_busy_llc: bitmap of which limbo RMIDs are above threshold |
67 | * @mbm_total: saved state for MBM total bandwidth | |
68 | * @mbm_local: saved state for MBM local bandwidth | |
69 | * @mbm_over: worker to periodically read MBM h/w counters | |
70 | * @cqm_limbo: worker to periodically read CQM h/w counters | |
71 | * @mbm_work_cpu: worker CPU for MBM h/w counters | |
72 | * @cqm_work_cpu: worker CPU for CQM h/w counters | |
73 | * @plr: pseudo-locked region (if any) associated with domain | |
e8f72825 | 74 | * @staged_config: parsed configuration to be applied |
781096d9 JM |
75 | * @mbps_val: When mba_sc is enabled, this holds the array of user |
76 | * specified control values for mba_sc in MBps, indexed | |
77 | * by closid | |
792e0f6f JM |
78 | */ |
79 | struct rdt_domain { | |
80 | struct list_head list; | |
81 | int id; | |
82 | struct cpumask cpu_mask; | |
792e0f6f JM |
83 | unsigned long *rmid_busy_llc; |
84 | struct mbm_state *mbm_total; | |
85 | struct mbm_state *mbm_local; | |
86 | struct delayed_work mbm_over; | |
87 | struct delayed_work cqm_limbo; | |
88 | int mbm_work_cpu; | |
89 | int cqm_work_cpu; | |
90 | struct pseudo_lock_region *plr; | |
75408e43 | 91 | struct resctrl_staged_config staged_config[CDP_NUM_TYPES]; |
781096d9 | 92 | u32 *mbps_val; |
792e0f6f | 93 | }; |
63c8b123 JM |
94 | |
95 | /** | |
96 | * struct resctrl_cache - Cache allocation related data | |
97 | * @cbm_len: Length of the cache bit mask | |
2d4daa54 BM |
98 | * @min_cbm_bits: Minimum number of consecutive bits to be set. |
99 | * The value 0 means the architecture can support | |
100 | * zero CBM. | |
63c8b123 JM |
101 | * @shareable_bits: Bitmask of shareable resource with other |
102 | * executing entities | |
39c6eed1 | 103 | * @arch_has_sparse_bitmasks: True if a bitmask like f00f is valid. |
63c8b123 JM |
104 | * @arch_has_per_cpu_cfg: True if QOS_CFG register for this cache |
105 | * level has CPU scope. | |
106 | */ | |
107 | struct resctrl_cache { | |
108 | unsigned int cbm_len; | |
109 | unsigned int min_cbm_bits; | |
63c8b123 | 110 | unsigned int shareable_bits; |
39c6eed1 | 111 | bool arch_has_sparse_bitmasks; |
63c8b123 JM |
112 | bool arch_has_per_cpu_cfg; |
113 | }; | |
114 | ||
115 | /** | |
116 | * enum membw_throttle_mode - System's memory bandwidth throttling mode | |
117 | * @THREAD_THROTTLE_UNDEFINED: Not relevant to the system | |
118 | * @THREAD_THROTTLE_MAX: Memory bandwidth is throttled at the core | |
119 | * always using smallest bandwidth percentage | |
120 | * assigned to threads, aka "max throttling" | |
121 | * @THREAD_THROTTLE_PER_THREAD: Memory bandwidth is throttled at the thread | |
122 | */ | |
123 | enum membw_throttle_mode { | |
124 | THREAD_THROTTLE_UNDEFINED = 0, | |
125 | THREAD_THROTTLE_MAX, | |
126 | THREAD_THROTTLE_PER_THREAD, | |
127 | }; | |
128 | ||
129 | /** | |
130 | * struct resctrl_membw - Memory bandwidth allocation related data | |
131 | * @min_bw: Minimum memory bandwidth percentage user can request | |
132 | * @bw_gran: Granularity at which the memory bandwidth is allocated | |
133 | * @delay_linear: True if memory B/W delay is in linear scale | |
134 | * @arch_needs_linear: True if we can't configure non-linear resources | |
135 | * @throttle_mode: Bandwidth throttling mode when threads request | |
136 | * different memory bandwidths | |
137 | * @mba_sc: True if MBA software controller(mba_sc) is enabled | |
138 | * @mb_map: Mapping of memory B/W percentage to memory B/W delay | |
139 | */ | |
140 | struct resctrl_membw { | |
141 | u32 min_bw; | |
142 | u32 bw_gran; | |
143 | u32 delay_linear; | |
144 | bool arch_needs_linear; | |
145 | enum membw_throttle_mode throttle_mode; | |
146 | bool mba_sc; | |
147 | u32 *mb_map; | |
148 | }; | |
149 | ||
150 | struct rdt_parse_data; | |
1c290682 | 151 | struct resctrl_schema; |
63c8b123 JM |
152 | |
153 | /** | |
154 | * struct rdt_resource - attributes of a resctrl resource | |
155 | * @rid: The index of the resource | |
63c8b123 JM |
156 | * @alloc_capable: Is allocation available on this machine |
157 | * @mon_capable: Is monitor feature available on this machine | |
158 | * @num_rmid: Number of RMIDs available | |
159 | * @cache_level: Which cache level defines scope of this resource | |
160 | * @cache: Cache allocation related data | |
161 | * @membw: If the component has bandwidth controls, their properties. | |
fb700810 | 162 | * @domains: RCU list of all domains for this resource |
63c8b123 JM |
163 | * @name: Name to use in "schemata" file. |
164 | * @data_width: Character width of data when displaying | |
165 | * @default_ctrl: Specifies default cache cbm or memory B/W percent. | |
166 | * @format_str: Per resource format string to show domain value | |
167 | * @parse_ctrlval: Per resource function pointer to parse control values | |
168 | * @evt_list: List of monitoring events | |
169 | * @fflags: flags to choose base and info files | |
c091e907 | 170 | * @cdp_capable: Is the CDP feature available on this resource |
63c8b123 JM |
171 | */ |
172 | struct rdt_resource { | |
173 | int rid; | |
63c8b123 JM |
174 | bool alloc_capable; |
175 | bool mon_capable; | |
176 | int num_rmid; | |
177 | int cache_level; | |
178 | struct resctrl_cache cache; | |
179 | struct resctrl_membw membw; | |
180 | struct list_head domains; | |
181 | char *name; | |
182 | int data_width; | |
183 | u32 default_ctrl; | |
184 | const char *format_str; | |
185 | int (*parse_ctrlval)(struct rdt_parse_data *data, | |
1c290682 | 186 | struct resctrl_schema *s, |
63c8b123 JM |
187 | struct rdt_domain *d); |
188 | struct list_head evt_list; | |
189 | unsigned long fflags; | |
c091e907 | 190 | bool cdp_capable; |
63c8b123 JM |
191 | }; |
192 | ||
cdb9ebc9 JM |
193 | /** |
194 | * struct resctrl_schema - configuration abilities of a resource presented to | |
195 | * user-space | |
196 | * @list: Member of resctrl_schema_all. | |
e198fde3 | 197 | * @name: The name to use in the "schemata" file. |
208ab168 | 198 | * @conf_type: Whether this schema is specific to code/data. |
cdb9ebc9 JM |
199 | * @res: The resource structure exported by the architecture to describe |
200 | * the hardware that is configured by this schema. | |
3183e87c JM |
201 | * @num_closid: The number of closid that can be used with this schema. When |
202 | * features like CDP are enabled, this will be lower than the | |
203 | * hardware supports for the resource. | |
cdb9ebc9 JM |
204 | */ |
205 | struct resctrl_schema { | |
206 | struct list_head list; | |
e198fde3 | 207 | char name[8]; |
208ab168 | 208 | enum resctrl_conf_type conf_type; |
cdb9ebc9 | 209 | struct rdt_resource *res; |
eb6f3187 | 210 | u32 num_closid; |
cdb9ebc9 | 211 | }; |
eb6f3187 JM |
212 | |
213 | /* The number of closid supported by this resource regardless of CDP */ | |
214 | u32 resctrl_arch_get_num_closid(struct rdt_resource *r); | |
2e667819 | 215 | int resctrl_arch_update_domains(struct rdt_resource *r, u32 closid); |
ff6357bb JM |
216 | |
217 | /* | |
218 | * Update the ctrl_val and apply this config right now. | |
219 | * Must be called on one of the domain's CPUs. | |
220 | */ | |
221 | int resctrl_arch_update_one(struct rdt_resource *r, struct rdt_domain *d, | |
222 | u32 closid, enum resctrl_conf_type t, u32 cfg_val); | |
223 | ||
111136e6 JM |
224 | u32 resctrl_arch_get_config(struct rdt_resource *r, struct rdt_domain *d, |
225 | u32 closid, enum resctrl_conf_type type); | |
3a7232cd | 226 | int resctrl_online_domain(struct rdt_resource *r, struct rdt_domain *d); |
798fd4b9 | 227 | void resctrl_offline_domain(struct rdt_resource *r, struct rdt_domain *d); |
1b3e50ce | 228 | void resctrl_online_cpu(unsigned int cpu); |
258c91e8 | 229 | void resctrl_offline_cpu(unsigned int cpu); |
8286618a JM |
230 | |
231 | /** | |
232 | * resctrl_arch_rmid_read() - Read the eventid counter corresponding to rmid | |
233 | * for this resource and domain. | |
234 | * @r: resource that the counter should be read from. | |
235 | * @d: domain that the counter should be read from. | |
40fc735b JM |
236 | * @closid: closid that matches the rmid. Depending on the architecture, the |
237 | * counter may match traffic of both @closid and @rmid, or @rmid | |
238 | * only. | |
8286618a JM |
239 | * @rmid: rmid of the counter to read. |
240 | * @eventid: eventid to read, e.g. L3 occupancy. | |
f7b1843e | 241 | * @val: result of the counter read in bytes. |
e557999f JM |
242 | * @arch_mon_ctx: An architecture specific value from |
243 | * resctrl_arch_mon_ctx_alloc(), for MPAM this identifies | |
244 | * the hardware monitor allocated for this read request. | |
8286618a | 245 | * |
6fde1424 JM |
246 | * Some architectures need to sleep when first programming some of the counters. |
247 | * (specifically: arm64's MPAM cache occupancy counters can return 'not ready' | |
248 | * for a short period of time). Call from a non-migrateable process context on | |
249 | * a CPU that belongs to domain @d. e.g. use smp_call_on_cpu() or | |
250 | * schedule_work_on(). This function can be called with interrupts masked, | |
251 | * e.g. using smp_call_function_any(), but may consistently return an error. | |
8286618a JM |
252 | * |
253 | * Return: | |
254 | * 0 on success, or -EIO, -EINVAL etc on error. | |
255 | */ | |
256 | int resctrl_arch_rmid_read(struct rdt_resource *r, struct rdt_domain *d, | |
40fc735b | 257 | u32 closid, u32 rmid, enum resctrl_event_id eventid, |
e557999f | 258 | u64 *val, void *arch_mon_ctx); |
40fc735b | 259 | |
6fde1424 JM |
260 | /** |
261 | * resctrl_arch_rmid_read_context_check() - warn about invalid contexts | |
262 | * | |
263 | * When built with CONFIG_DEBUG_ATOMIC_SLEEP generate a warning when | |
264 | * resctrl_arch_rmid_read() is called with preemption disabled. | |
265 | * | |
266 | * The contract with resctrl_arch_rmid_read() is that if interrupts | |
267 | * are unmasked, it can sleep. This allows NOHZ_FULL systems to use an | |
268 | * IPI, (and fail if the call needed to sleep), while most of the time | |
269 | * the work is scheduled, allowing the call to sleep. | |
270 | */ | |
271 | static inline void resctrl_arch_rmid_read_context_check(void) | |
272 | { | |
273 | if (!irqs_disabled()) | |
274 | might_sleep(); | |
275 | } | |
eb6f3187 | 276 | |
fea62d37 JM |
277 | /** |
278 | * resctrl_arch_reset_rmid() - Reset any private state associated with rmid | |
279 | * and eventid. | |
280 | * @r: The domain's resource. | |
281 | * @d: The rmid's domain. | |
40fc735b JM |
282 | * @closid: closid that matches the rmid. Depending on the architecture, the |
283 | * counter may match traffic of both @closid and @rmid, or @rmid only. | |
fea62d37 JM |
284 | * @rmid: The rmid whose counter values should be reset. |
285 | * @eventid: The eventid whose counter values should be reset. | |
286 | * | |
287 | * This can be called from any CPU. | |
288 | */ | |
289 | void resctrl_arch_reset_rmid(struct rdt_resource *r, struct rdt_domain *d, | |
40fc735b JM |
290 | u32 closid, u32 rmid, |
291 | enum resctrl_event_id eventid); | |
fea62d37 | 292 | |
92bd5a13 BM |
293 | /** |
294 | * resctrl_arch_reset_rmid_all() - Reset all private state associated with | |
295 | * all rmids and eventids. | |
296 | * @r: The resctrl resource. | |
297 | * @d: The domain for which all architectural counter state will | |
298 | * be cleared. | |
299 | * | |
300 | * This can be called from any CPU. | |
301 | */ | |
302 | void resctrl_arch_reset_rmid_all(struct rdt_resource *r, struct rdt_domain *d); | |
303 | ||
ae2328b5 | 304 | extern unsigned int resctrl_rmid_realloc_threshold; |
d80975e2 | 305 | extern unsigned int resctrl_rmid_realloc_limit; |
ae2328b5 | 306 | |
e79f15a4 | 307 | #endif /* _RESCTRL_H */ |