[linux-block.git] / include / linux / regulator / pca9450.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/* Copyright 2020 NXP. */

#ifndef __LINUX_REG_PCA9450_H__
#define __LINUX_REG_PCA9450_H__

#include <linux/regmap.h>

enum pca9450_chip_type {
	PCA9450_TYPE_PCA9450A = 0,
	PCA9450_TYPE_PCA9450BC,
	PCA9450_TYPE_PCA9451A,
	PCA9450_TYPE_AMOUNT,
};

enum {
	PCA9450_BUCK1 = 0,
	PCA9450_BUCK2,
	PCA9450_BUCK3,
	PCA9450_BUCK4,
	PCA9450_BUCK5,
	PCA9450_BUCK6,
	PCA9450_LDO1,
	PCA9450_LDO2,
	PCA9450_LDO3,
	PCA9450_LDO4,
	PCA9450_LDO5,
	PCA9450_REGULATOR_CNT,
};

enum {
	PCA9450_DVS_LEVEL_RUN = 0,
	PCA9450_DVS_LEVEL_STANDBY,
	PCA9450_DVS_LEVEL_MAX,
};

#define PCA9450_BUCK1_VOLTAGE_NUM	0x80
#define PCA9450_BUCK2_VOLTAGE_NUM	0x80
#define PCA9450_BUCK3_VOLTAGE_NUM	0x80
#define PCA9450_BUCK4_VOLTAGE_NUM	0x80

#define PCA9450_BUCK5_VOLTAGE_NUM	0x80
#define PCA9450_BUCK6_VOLTAGE_NUM	0x80

#define PCA9450_LDO1_VOLTAGE_NUM	0x08
#define PCA9450_LDO2_VOLTAGE_NUM	0x08
#define PCA9450_LDO3_VOLTAGE_NUM	0x20
#define PCA9450_LDO4_VOLTAGE_NUM	0x20
#define PCA9450_LDO5_VOLTAGE_NUM	0x10

enum {
	PCA9450_REG_DEV_ID	    = 0x00,
	PCA9450_REG_INT1	    = 0x01,
	PCA9450_REG_INT1_MSK	    = 0x02,
	PCA9450_REG_STATUS1	    = 0x03,
	PCA9450_REG_STATUS2	    = 0x04,
	PCA9450_REG_PWRON_STAT	    = 0x05,
	PCA9450_REG_SWRST	    = 0x06,
	PCA9450_REG_PWRCTRL         = 0x07,
	PCA9450_REG_RESET_CTRL      = 0x08,
	PCA9450_REG_CONFIG1         = 0x09,
	PCA9450_REG_CONFIG2         = 0x0A,
	PCA9450_REG_BUCK123_DVS     = 0x0C,
	PCA9450_REG_BUCK1OUT_LIMIT  = 0x0D,
	PCA9450_REG_BUCK2OUT_LIMIT  = 0x0E,
	PCA9450_REG_BUCK3OUT_LIMIT  = 0x0F,
	PCA9450_REG_BUCK1CTRL       = 0x10,
	PCA9450_REG_BUCK1OUT_DVS0   = 0x11,
	PCA9450_REG_BUCK1OUT_DVS1   = 0x12,
	PCA9450_REG_BUCK2CTRL       = 0x13,
	PCA9450_REG_BUCK2OUT_DVS0   = 0x14,
	PCA9450_REG_BUCK2OUT_DVS1   = 0x15,
	PCA9450_REG_BUCK3CTRL       = 0x16,
	PCA9450_REG_BUCK3OUT_DVS0   = 0x17,
	PCA9450_REG_BUCK3OUT_DVS1   = 0x18,
	PCA9450_REG_BUCK4CTRL       = 0x19,
	PCA9450_REG_BUCK4OUT        = 0x1A,
	PCA9450_REG_BUCK5CTRL       = 0x1B,
	PCA9450_REG_BUCK5OUT        = 0x1C,
	PCA9450_REG_BUCK6CTRL       = 0x1D,
	PCA9450_REG_BUCK6OUT        = 0x1E,
	PCA9450_REG_LDO_AD_CTRL     = 0x20,
	PCA9450_REG_LDO1CTRL        = 0x21,
	PCA9450_REG_LDO2CTRL        = 0x22,
	PCA9450_REG_LDO3CTRL        = 0x23,
	PCA9450_REG_LDO4CTRL        = 0x24,
	PCA9450_REG_LDO5CTRL_L      = 0x25,
	PCA9450_REG_LDO5CTRL_H      = 0x26,
	PCA9450_REG_LOADSW_CTRL     = 0x2A,
	PCA9450_REG_VRFLT1_STS      = 0x2B,
	PCA9450_REG_VRFLT2_STS      = 0x2C,
	PCA9450_REG_VRFLT1_MASK     = 0x2D,
	PCA9450_REG_VRFLT2_MASK     = 0x2E,
	PCA9450_MAX_REGISTER	    = 0x2F,
};

/* PCA9450 BUCK ENMODE bits */
#define BUCK_ENMODE_OFF			0x00
#define BUCK_ENMODE_ONREQ		0x01
#define BUCK_ENMODE_ONREQ_STBYREQ	0x02
#define BUCK_ENMODE_ON			0x03

/* PCA9450_REG_BUCK1_CTRL bits */
#define BUCK1_RAMP_MASK			0xC0
#define BUCK1_RAMP_25MV			0x0
#define BUCK1_RAMP_12P5MV		0x1
#define BUCK1_RAMP_6P25MV		0x2
#define BUCK1_RAMP_3P125MV		0x3
#define BUCK1_DVS_CTRL			0x10
#define BUCK1_AD			0x08
#define BUCK1_FPWM			0x04
#define BUCK1_ENMODE_MASK		0x03

/* PCA9450_REG_BUCK2_CTRL bits */
#define BUCK2_RAMP_MASK			0xC0
#define BUCK2_RAMP_25MV			0x0
#define BUCK2_RAMP_12P5MV		0x1
#define BUCK2_RAMP_6P25MV		0x2
#define BUCK2_RAMP_3P125MV		0x3
#define BUCK2_DVS_CTRL			0x10
#define BUCK2_AD			0x08
#define BUCK2_FPWM			0x04
#define BUCK2_ENMODE_MASK		0x03

/* PCA9450_REG_BUCK3_CTRL bits */
#define BUCK3_RAMP_MASK			0xC0
#define BUCK3_RAMP_25MV			0x0
#define BUCK3_RAMP_12P5MV		0x1
#define BUCK3_RAMP_6P25MV		0x2
#define BUCK3_RAMP_3P125MV		0x3
#define BUCK3_DVS_CTRL			0x10
#define BUCK3_AD			0x08
#define BUCK3_FPWM			0x04
#define BUCK3_ENMODE_MASK		0x03

/* PCA9450_REG_BUCK4_CTRL bits */
#define BUCK4_AD			0x08
#define BUCK4_FPWM			0x04
#define BUCK4_ENMODE_MASK		0x03

/* PCA9450_REG_BUCK5_CTRL bits */
#define BUCK5_AD			0x08
#define BUCK5_FPWM			0x04
#define BUCK5_ENMODE_MASK		0x03

/* PCA9450_REG_BUCK6_CTRL bits */
#define BUCK6_AD			0x08
#define BUCK6_FPWM			0x04
#define BUCK6_ENMODE_MASK		0x03

/* PCA9450_REG_BUCK123_PRESET_EN bit */
#define BUCK123_PRESET_EN		0x80

/* PCA9450_BUCK1OUT_DVS0 bits */
#define BUCK1OUT_DVS0_MASK		0x7F
#define BUCK1OUT_DVS0_DEFAULT		0x14

/* PCA9450_BUCK1OUT_DVS1 bits */
#define BUCK1OUT_DVS1_MASK		0x7F
#define BUCK1OUT_DVS1_DEFAULT		0x14

/* PCA9450_BUCK2OUT_DVS0 bits */
#define BUCK2OUT_DVS0_MASK		0x7F
#define BUCK2OUT_DVS0_DEFAULT		0x14

/* PCA9450_BUCK2OUT_DVS1 bits */
#define BUCK2OUT_DVS1_MASK		0x7F
#define BUCK2OUT_DVS1_DEFAULT		0x14

/* PCA9450_BUCK3OUT_DVS0 bits */
#define BUCK3OUT_DVS0_MASK		0x7F
#define BUCK3OUT_DVS0_DEFAULT		0x14

/* PCA9450_BUCK3OUT_DVS1 bits */
#define BUCK3OUT_DVS1_MASK		0x7F
#define BUCK3OUT_DVS1_DEFAULT		0x14

/* PCA9450_REG_BUCK4OUT bits */
#define BUCK4OUT_MASK			0x7F
#define BUCK4OUT_DEFAULT		0x6C

/* PCA9450_REG_BUCK5OUT bits */
#define BUCK5OUT_MASK			0x7F
#define BUCK5OUT_DEFAULT		0x30

/* PCA9450_REG_BUCK6OUT bits */
#define BUCK6OUT_MASK			0x7F
#define BUCK6OUT_DEFAULT		0x14

/* PCA9450_REG_LDO1_VOLT bits */
#define LDO1_EN_MASK			0xC0
#define LDO1OUT_MASK			0x07

/* PCA9450_REG_LDO2_VOLT bits */
#define LDO2_EN_MASK			0xC0
#define LDO2OUT_MASK			0x07

/* PCA9450_REG_LDO3_VOLT bits */
#define LDO3_EN_MASK			0xC0
#define LDO3OUT_MASK			0x1F

/* PCA9450_REG_LDO4_VOLT bits */
#define LDO4_EN_MASK			0xC0
#define LDO4OUT_MASK			0x1F

/* PCA9450_REG_LDO5_VOLT bits */
#define LDO5L_EN_MASK			0xC0
#define LDO5LOUT_MASK			0x0F

#define LDO5H_EN_MASK			0xC0
#define LDO5HOUT_MASK			0x0F

/* PCA9450_REG_IRQ bits */
#define IRQ_PWRON			0x80
#define IRQ_WDOGB			0x40
#define IRQ_RSVD			0x20
#define IRQ_VR_FLT1			0x10
#define IRQ_VR_FLT2			0x08
#define IRQ_LOWVSYS			0x04
#define IRQ_THERM_105			0x02
#define IRQ_THERM_125			0x01

/* PCA9450_REG_RESET_CTRL bits */
#define WDOG_B_CFG_MASK			0xC0
#define WDOG_B_CFG_NONE			0x00
#define WDOG_B_CFG_WARM			0x40
#define WDOG_B_CFG_COLD_LDO12		0x80
#define WDOG_B_CFG_COLD			0xC0

/* PCA9450_REG_CONFIG2 bits */
#define I2C_LT_MASK			0x03
#define I2C_LT_FORCE_DISABLE		0x00
#define I2C_LT_ON_STANDBY_RUN		0x01
#define I2C_LT_ON_RUN			0x02
#define I2C_LT_FORCE_ENABLE		0x03

#endif /* __LINUX_REG_PCA9450_H__ */
Commit	Line	Data
0935ff5f RG	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
	2	/* Copyright 2020 NXP. */
	3
	4	#ifndef __LINUX_REG_PCA9450_H__
	5	#define __LINUX_REG_PCA9450_H__
	6
	7	#include <linux/regmap.h>
	8
	9	enum pca9450_chip_type {
	10	PCA9450_TYPE_PCA9450A = 0,
	11	PCA9450_TYPE_PCA9450BC,
5edeb7d3	12	PCA9450_TYPE_PCA9451A,
0935ff5f RG	13	PCA9450_TYPE_AMOUNT,
	14	};
	15
	16	enum {
	17	PCA9450_BUCK1 = 0,
	18	PCA9450_BUCK2,
	19	PCA9450_BUCK3,
	20	PCA9450_BUCK4,
	21	PCA9450_BUCK5,
	22	PCA9450_BUCK6,
	23	PCA9450_LDO1,
	24	PCA9450_LDO2,
	25	PCA9450_LDO3,
	26	PCA9450_LDO4,
	27	PCA9450_LDO5,
	28	PCA9450_REGULATOR_CNT,
	29	};
	30
	31	enum {
	32	PCA9450_DVS_LEVEL_RUN = 0,
	33	PCA9450_DVS_LEVEL_STANDBY,
	34	PCA9450_DVS_LEVEL_MAX,
	35	};
	36
	37	#define PCA9450_BUCK1_VOLTAGE_NUM 0x80
	38	#define PCA9450_BUCK2_VOLTAGE_NUM 0x80
	39	#define PCA9450_BUCK3_VOLTAGE_NUM 0x80
	40	#define PCA9450_BUCK4_VOLTAGE_NUM 0x80
	41
	42	#define PCA9450_BUCK5_VOLTAGE_NUM 0x80
	43	#define PCA9450_BUCK6_VOLTAGE_NUM 0x80
	44
	45	#define PCA9450_LDO1_VOLTAGE_NUM 0x08
	46	#define PCA9450_LDO2_VOLTAGE_NUM 0x08
	47	#define PCA9450_LDO3_VOLTAGE_NUM 0x20
	48	#define PCA9450_LDO4_VOLTAGE_NUM 0x20
	49	#define PCA9450_LDO5_VOLTAGE_NUM 0x10
	50
	51	enum {
	52	PCA9450_REG_DEV_ID = 0x00,
	53	PCA9450_REG_INT1 = 0x01,
	54	PCA9450_REG_INT1_MSK = 0x02,
	55	PCA9450_REG_STATUS1 = 0x03,
	56	PCA9450_REG_STATUS2 = 0x04,
	57	PCA9450_REG_PWRON_STAT = 0x05,
	58	PCA9450_REG_SWRST = 0x06,
	59	PCA9450_REG_PWRCTRL = 0x07,
	60	PCA9450_REG_RESET_CTRL = 0x08,
	61	PCA9450_REG_CONFIG1 = 0x09,
	62	PCA9450_REG_CONFIG2 = 0x0A,
	63	PCA9450_REG_BUCK123_DVS = 0x0C,
	64	PCA9450_REG_BUCK1OUT_LIMIT = 0x0D,
	65	PCA9450_REG_BUCK2OUT_LIMIT = 0x0E,
	66	PCA9450_REG_BUCK3OUT_LIMIT = 0x0F,
	67	PCA9450_REG_BUCK1CTRL = 0x10,
	68	PCA9450_REG_BUCK1OUT_DVS0 = 0x11,
	69	PCA9450_REG_BUCK1OUT_DVS1 = 0x12,
	70	PCA9450_REG_BUCK2CTRL = 0x13,
	71	PCA9450_REG_BUCK2OUT_DVS0 = 0x14,
	72	PCA9450_REG_BUCK2OUT_DVS1 = 0x15,
	73	PCA9450_REG_BUCK3CTRL = 0x16,
	74	PCA9450_REG_BUCK3OUT_DVS0 = 0x17,
	75	PCA9450_REG_BUCK3OUT_DVS1 = 0x18,
	76	PCA9450_REG_BUCK4CTRL = 0x19,
77	PCA9450_REG_BUCK4OUT = 0x1A,
78	PCA9450_REG_BUCK5CTRL = 0x1B,
79	PCA9450_REG_BUCK5OUT = 0x1C,
80	PCA9450_REG_BUCK6CTRL = 0x1D,
81	PCA9450_REG_BUCK6OUT = 0x1E,
82	PCA9450_REG_LDO_AD_CTRL = 0x20,
83	PCA9450_REG_LDO1CTRL = 0x21,
84	PCA9450_REG_LDO2CTRL = 0x22,
85	PCA9450_REG_LDO3CTRL = 0x23,
86	PCA9450_REG_LDO4CTRL = 0x24,
87	PCA9450_REG_LDO5CTRL_L = 0x25,
88	PCA9450_REG_LDO5CTRL_H = 0x26,
89	PCA9450_REG_LOADSW_CTRL = 0x2A,
90	PCA9450_REG_VRFLT1_STS = 0x2B,
91	PCA9450_REG_VRFLT2_STS = 0x2C,
92	PCA9450_REG_VRFLT1_MASK = 0x2D,
93	PCA9450_REG_VRFLT2_MASK = 0x2E,
94	PCA9450_MAX_REGISTER = 0x2F,
95	};
96
97	/* PCA9450 BUCK ENMODE bits */
98	#define BUCK_ENMODE_OFF 0x00
99	#define BUCK_ENMODE_ONREQ 0x01
100	#define BUCK_ENMODE_ONREQ_STBYREQ 0x02
101	#define BUCK_ENMODE_ON 0x03
102
103	/* PCA9450_REG_BUCK1_CTRL bits */
104	#define BUCK1_RAMP_MASK 0xC0
105	#define BUCK1_RAMP_25MV 0x0
106	#define BUCK1_RAMP_12P5MV 0x1
107	#define BUCK1_RAMP_6P25MV 0x2
108	#define BUCK1_RAMP_3P125MV 0x3
109	#define BUCK1_DVS_CTRL 0x10
110	#define BUCK1_AD 0x08
111	#define BUCK1_FPWM 0x04
112	#define BUCK1_ENMODE_MASK 0x03
113
114	/* PCA9450_REG_BUCK2_CTRL bits */
115	#define BUCK2_RAMP_MASK 0xC0
116	#define BUCK2_RAMP_25MV 0x0
117	#define BUCK2_RAMP_12P5MV 0x1
118	#define BUCK2_RAMP_6P25MV 0x2
119	#define BUCK2_RAMP_3P125MV 0x3
120	#define BUCK2_DVS_CTRL 0x10
121	#define BUCK2_AD 0x08
122	#define BUCK2_FPWM 0x04
123	#define BUCK2_ENMODE_MASK 0x03
124
125	/* PCA9450_REG_BUCK3_CTRL bits */
126	#define BUCK3_RAMP_MASK 0xC0
127	#define BUCK3_RAMP_25MV 0x0
128	#define BUCK3_RAMP_12P5MV 0x1
129	#define BUCK3_RAMP_6P25MV 0x2
130	#define BUCK3_RAMP_3P125MV 0x3
131	#define BUCK3_DVS_CTRL 0x10
132	#define BUCK3_AD 0x08
133	#define BUCK3_FPWM 0x04
134	#define BUCK3_ENMODE_MASK 0x03
135
136	/* PCA9450_REG_BUCK4_CTRL bits */
137	#define BUCK4_AD 0x08
138	#define BUCK4_FPWM 0x04
139	#define BUCK4_ENMODE_MASK 0x03
140
141	/* PCA9450_REG_BUCK5_CTRL bits */
142	#define BUCK5_AD 0x08
143	#define BUCK5_FPWM 0x04
144	#define BUCK5_ENMODE_MASK 0x03
145
146	/* PCA9450_REG_BUCK6_CTRL bits */
147	#define BUCK6_AD 0x08
148	#define BUCK6_FPWM 0x04
149	#define BUCK6_ENMODE_MASK 0x03
150
98b94b6e FS	151	/* PCA9450_REG_BUCK123_PRESET_EN bit */
	152	#define BUCK123_PRESET_EN 0x80
	153
0935ff5f RG	154	/* PCA9450_BUCK1OUT_DVS0 bits */
	155	#define BUCK1OUT_DVS0_MASK 0x7F
	156	#define BUCK1OUT_DVS0_DEFAULT 0x14
	157
	158	/* PCA9450_BUCK1OUT_DVS1 bits */
	159	#define BUCK1OUT_DVS1_MASK 0x7F
	160	#define BUCK1OUT_DVS1_DEFAULT 0x14
	161
	162	/* PCA9450_BUCK2OUT_DVS0 bits */
	163	#define BUCK2OUT_DVS0_MASK 0x7F
	164	#define BUCK2OUT_DVS0_DEFAULT 0x14
	165
	166	/* PCA9450_BUCK2OUT_DVS1 bits */
	167	#define BUCK2OUT_DVS1_MASK 0x7F
	168	#define BUCK2OUT_DVS1_DEFAULT 0x14
	169
	170	/* PCA9450_BUCK3OUT_DVS0 bits */
	171	#define BUCK3OUT_DVS0_MASK 0x7F
	172	#define BUCK3OUT_DVS0_DEFAULT 0x14
	173
	174	/* PCA9450_BUCK3OUT_DVS1 bits */
	175	#define BUCK3OUT_DVS1_MASK 0x7F
	176	#define BUCK3OUT_DVS1_DEFAULT 0x14
	177
	178	/* PCA9450_REG_BUCK4OUT bits */
	179	#define BUCK4OUT_MASK 0x7F
	180	#define BUCK4OUT_DEFAULT 0x6C
	181
	182	/* PCA9450_REG_BUCK5OUT bits */
	183	#define BUCK5OUT_MASK 0x7F
	184	#define BUCK5OUT_DEFAULT 0x30
	185
	186	/* PCA9450_REG_BUCK6OUT bits */
	187	#define BUCK6OUT_MASK 0x7F
	188	#define BUCK6OUT_DEFAULT 0x14
	189
	190	/* PCA9450_REG_LDO1_VOLT bits */
	191	#define LDO1_EN_MASK 0xC0
	192	#define LDO1OUT_MASK 0x07
	193
	194	/* PCA9450_REG_LDO2_VOLT bits */
	195	#define LDO2_EN_MASK 0xC0
	196	#define LDO2OUT_MASK 0x07
	197
	198	/* PCA9450_REG_LDO3_VOLT bits */
	199	#define LDO3_EN_MASK 0xC0
7257d930	200	#define LDO3OUT_MASK 0x1F
0935ff5f RG	201
	202	/* PCA9450_REG_LDO4_VOLT bits */
	203	#define LDO4_EN_MASK 0xC0
7257d930	204	#define LDO4OUT_MASK 0x1F
0935ff5f RG	205
	206	/* PCA9450_REG_LDO5_VOLT bits */
	207	#define LDO5L_EN_MASK 0xC0
	208	#define LDO5LOUT_MASK 0x0F
	209
	210	#define LDO5H_EN_MASK 0xC0
	211	#define LDO5HOUT_MASK 0x0F
	212
	213	/* PCA9450_REG_IRQ bits */
	214	#define IRQ_PWRON 0x80
	215	#define IRQ_WDOGB 0x40
	216	#define IRQ_RSVD 0x20
	217	#define IRQ_VR_FLT1 0x10
	218	#define IRQ_VR_FLT2 0x08
	219	#define IRQ_LOWVSYS 0x04
	220	#define IRQ_THERM_105 0x02
	221	#define IRQ_THERM_125 0x01
	222
f7684f5a FS	223	/* PCA9450_REG_RESET_CTRL bits */
	224	#define WDOG_B_CFG_MASK 0xC0
	225	#define WDOG_B_CFG_NONE 0x00
	226	#define WDOG_B_CFG_WARM 0x40
	227	#define WDOG_B_CFG_COLD_LDO12 0x80
	228	#define WDOG_B_CFG_COLD 0xC0
	229
62139f52 PDO	230	/* PCA9450_REG_CONFIG2 bits */
	231	#define I2C_LT_MASK 0x03
	232	#define I2C_LT_FORCE_DISABLE 0x00
	233	#define I2C_LT_ON_STANDBY_RUN 0x01
	234	#define I2C_LT_ON_RUN 0x02
	235	#define I2C_LT_FORCE_ENABLE 0x03
	236
0935ff5f	237	#endif /* __LINUX_REG_PCA9450_H__ */