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[linux-2.6-block.git] / include / linux / qed / qed_if.h
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fe56b9e6
YM		 1/* QLogic qed NIC Driver
2 *
3 * Copyright (c) 2015 QLogic Corporation
4 *
5 * This software is available under the terms of the GNU General Public License
6 * (GPL) Version 2, available from the file COPYING in the main directory of
7 * this source tree.
8 */
9
10#ifndef _QED_IF_H
11#define _QED_IF_H
12
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/netdevice.h>
16#include <linux/pci.h>
17#include <linux/skbuff.h>
18#include <linux/types.h>
19#include <asm/byteorder.h>
20#include <linux/io.h>
21#include <linux/compiler.h>
22#include <linux/kernel.h>
23#include <linux/list.h>
24#include <linux/slab.h>
25#include <linux/qed/common_hsi.h>
26#include <linux/qed/qed_chain.h>
27
39651abd
SRK		 28enum dcbx_protocol_type {
29 DCBX_PROTOCOL_ISCSI,
30 DCBX_PROTOCOL_FCOE,
31 DCBX_PROTOCOL_ROCE,
32 DCBX_PROTOCOL_ROCE_V2,
33 DCBX_PROTOCOL_ETH,
34 DCBX_MAX_PROTOCOL_TYPE
35};
36
51ff1725
RA		 37#define QED_ROCE_PROTOCOL_INDEX (3)
38
6ad8c632
SRK		 39#ifdef CONFIG_DCB
40#define QED_LLDP_CHASSIS_ID_STAT_LEN 4
41#define QED_LLDP_PORT_ID_STAT_LEN 4
42#define QED_DCBX_MAX_APP_PROTOCOL 32
43#define QED_MAX_PFC_PRIORITIES 8
44#define QED_DCBX_DSCP_SIZE 64
45
46struct qed_dcbx_lldp_remote {
47 u32 peer_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
48 u32 peer_port_id[QED_LLDP_PORT_ID_STAT_LEN];
49 bool enable_rx;
50 bool enable_tx;
51 u32 tx_interval;
52 u32 max_credit;
53};
54
55struct qed_dcbx_lldp_local {
56 u32 local_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
57 u32 local_port_id[QED_LLDP_PORT_ID_STAT_LEN];
58};
59
60struct qed_dcbx_app_prio {
61 u8 roce;
62 u8 roce_v2;
63 u8 fcoe;
64 u8 iscsi;
65 u8 eth;
66};
67
68struct qed_dbcx_pfc_params {
69 bool willing;
70 bool enabled;
71 u8 prio[QED_MAX_PFC_PRIORITIES];
72 u8 max_tc;
73};
74
59bcb797
SRK		 75enum qed_dcbx_sf_ieee_type {
76 QED_DCBX_SF_IEEE_ETHTYPE,
77 QED_DCBX_SF_IEEE_TCP_PORT,
78 QED_DCBX_SF_IEEE_UDP_PORT,
79 QED_DCBX_SF_IEEE_TCP_UDP_PORT
80};
81
6ad8c632
SRK		 82struct qed_app_entry {
83 bool ethtype;
59bcb797 84 enum qed_dcbx_sf_ieee_type sf_ieee;
6ad8c632
SRK		 85 bool enabled;
86 u8 prio;
87 u16 proto_id;
88 enum dcbx_protocol_type proto_type;
89};
90
91struct qed_dcbx_params {
92 struct qed_app_entry app_entry[QED_DCBX_MAX_APP_PROTOCOL];
93 u16 num_app_entries;
94 bool app_willing;
95 bool app_valid;
96 bool app_error;
97 bool ets_willing;
98 bool ets_enabled;
99 bool ets_cbs;
100 bool valid;
101 u8 ets_pri_tc_tbl[QED_MAX_PFC_PRIORITIES];
102 u8 ets_tc_bw_tbl[QED_MAX_PFC_PRIORITIES];
103 u8 ets_tc_tsa_tbl[QED_MAX_PFC_PRIORITIES];
104 struct qed_dbcx_pfc_params pfc;
105 u8 max_ets_tc;
106};
107
108struct qed_dcbx_admin_params {
109 struct qed_dcbx_params params;
110 bool valid;
111};
112
113struct qed_dcbx_remote_params {
114 struct qed_dcbx_params params;
115 bool valid;
116};
117
118struct qed_dcbx_operational_params {
119 struct qed_dcbx_app_prio app_prio;
120 struct qed_dcbx_params params;
121 bool valid;
122 bool enabled;
123 bool ieee;
124 bool cee;
125 u32 err;
126};
127
128struct qed_dcbx_get {
129 struct qed_dcbx_operational_params operational;
130 struct qed_dcbx_lldp_remote lldp_remote;
131 struct qed_dcbx_lldp_local lldp_local;
132 struct qed_dcbx_remote_params remote;
133 struct qed_dcbx_admin_params local;
134};
135#endif
136
91420b83
SK		 137enum qed_led_mode {
138 QED_LED_MODE_OFF,
139 QED_LED_MODE_ON,
140 QED_LED_MODE_RESTORE
141};
142
fe56b9e6
YM		 143#define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \
144 (void __iomem *)(reg_addr))
145
146#define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr))
147
148#define QED_COALESCE_MAX 0xFF
0e191827 149#define QED_DEFAULT_RX_USECS 12
fe56b9e6
YM		 150
151/* forward */
152struct qed_dev;
153
154struct qed_eth_pf_params {
155 /* The following parameters are used during HW-init
156 * and these parameters need to be passed as arguments
157 * to update_pf_params routine invoked before slowpath start
158 */
159 u16 num_cons;
160};
161
c5ac9319
YM		 162/* Most of the the parameters below are described in the FW iSCSI / TCP HSI */
163struct qed_iscsi_pf_params {
164 u64 glbl_q_params_addr;
165 u64 bdq_pbl_base_addr[2];
166 u32 max_cwnd;
167 u16 cq_num_entries;
168 u16 cmdq_num_entries;
169 u16 dup_ack_threshold;
170 u16 tx_sws_timer;
171 u16 min_rto;
172 u16 min_rto_rt;
173 u16 max_rto;
174
175 /* The following parameters are used during HW-init
176 * and these parameters need to be passed as arguments
177 * to update_pf_params routine invoked before slowpath start
178 */
179 u16 num_cons;
180 u16 num_tasks;
181
182 /* The following parameters are used during protocol-init */
183 u16 half_way_close_timeout;
184 u16 bdq_xoff_threshold[2];
185 u16 bdq_xon_threshold[2];
186 u16 cmdq_xoff_threshold;
187 u16 cmdq_xon_threshold;
188 u16 rq_buffer_size;
189
190 u8 num_sq_pages_in_ring;
191 u8 num_r2tq_pages_in_ring;
192 u8 num_uhq_pages_in_ring;
193 u8 num_queues;
194 u8 log_page_size;
195 u8 rqe_log_size;
196 u8 max_fin_rt;
197 u8 gl_rq_pi;
198 u8 gl_cmd_pi;
199 u8 debug_mode;
200 u8 ll2_ooo_queue_id;
201 u8 ooo_enable;
202
203 u8 is_target;
204 u8 bdq_pbl_num_entries[2];
205};
206
207struct qed_rdma_pf_params {
208 /* Supplied to QED during resource allocation (may affect the ILT and
209 * the doorbell BAR).
210 */
211 u32 min_dpis; /* number of requested DPIs */
212 u32 num_mrs; /* number of requested memory regions */
213 u32 num_qps; /* number of requested Queue Pairs */
214 u32 num_srqs; /* number of requested SRQ */
215 u8 roce_edpm_mode; /* see QED_ROCE_EDPM_MODE_ENABLE */
216 u8 gl_pi; /* protocol index */
217
218 /* Will allocate rate limiters to be used with QPs */
219 u8 enable_dcqcn;
220};
221
fe56b9e6
YM		 222struct qed_pf_params {
223 struct qed_eth_pf_params eth_pf_params;
c5ac9319
YM		 224 struct qed_iscsi_pf_params iscsi_pf_params;
225 struct qed_rdma_pf_params rdma_pf_params;
fe56b9e6
YM		 226};
227
228enum qed_int_mode {
229 QED_INT_MODE_INTA,
230 QED_INT_MODE_MSIX,
231 QED_INT_MODE_MSI,
232 QED_INT_MODE_POLL,
233};
234
235struct qed_sb_info {
236 struct status_block *sb_virt;
237 dma_addr_t sb_phys;
238 u32 sb_ack; /* Last given ack */
239 u16 igu_sb_id;
240 void __iomem *igu_addr;
241 u8 flags;
242#define QED_SB_INFO_INIT 0x1
243#define QED_SB_INFO_SETUP 0x2
244
245 struct qed_dev *cdev;
246};
247
248struct qed_dev_info {
249 unsigned long pci_mem_start;
250 unsigned long pci_mem_end;
251 unsigned int pci_irq;
252 u8 num_hwfns;
253
254 u8 hw_mac[ETH_ALEN];
fc48b7a6 255 bool is_mf_default;
fe56b9e6
YM		 256
257 /* FW version */
258 u16 fw_major;
259 u16 fw_minor;
260 u16 fw_rev;
261 u16 fw_eng;
262
263 /* MFW version */
264 u32 mfw_rev;
265
266 u32 flash_size;
267 u8 mf_mode;
831bfb0e 268 bool tx_switching;
cee9fbd8 269 bool rdma_supported;
0fefbfba 270 u16 mtu;
14d39648
MY		 271
272 bool wol_support;
fe56b9e6
YM		 273};
274
275enum qed_sb_type {
276 QED_SB_TYPE_L2_QUEUE,
51ff1725 277 QED_SB_TYPE_CNQ,
fe56b9e6
YM		 278};
279
280enum qed_protocol {
281 QED_PROTOCOL_ETH,
c5ac9319 282 QED_PROTOCOL_ISCSI,
fe56b9e6
YM		 283};
284
054c67d1
SRK		 285enum qed_link_mode_bits {
286 QED_LM_FIBRE_BIT = BIT(0),
287 QED_LM_Autoneg_BIT = BIT(1),
288 QED_LM_Asym_Pause_BIT = BIT(2),
289 QED_LM_Pause_BIT = BIT(3),
290 QED_LM_1000baseT_Half_BIT = BIT(4),
291 QED_LM_1000baseT_Full_BIT = BIT(5),
292 QED_LM_10000baseKR_Full_BIT = BIT(6),
293 QED_LM_25000baseKR_Full_BIT = BIT(7),
294 QED_LM_40000baseLR4_Full_BIT = BIT(8),
295 QED_LM_50000baseKR2_Full_BIT = BIT(9),
296 QED_LM_100000baseKR4_Full_BIT = BIT(10),
297 QED_LM_COUNT = 11
298};
299
fe56b9e6
YM		 300struct qed_link_params {
301 bool link_up;
302
303#define QED_LINK_OVERRIDE_SPEED_AUTONEG BIT(0)
304#define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS BIT(1)
305#define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED BIT(2)
306#define QED_LINK_OVERRIDE_PAUSE_CONFIG BIT(3)
03dc76ca 307#define QED_LINK_OVERRIDE_LOOPBACK_MODE BIT(4)
fe56b9e6
YM		 308 u32 override_flags;
309 bool autoneg;
310 u32 adv_speeds;
311 u32 forced_speed;
312#define QED_LINK_PAUSE_AUTONEG_ENABLE BIT(0)
313#define QED_LINK_PAUSE_RX_ENABLE BIT(1)
314#define QED_LINK_PAUSE_TX_ENABLE BIT(2)
315 u32 pause_config;
03dc76ca
SRK		 316#define QED_LINK_LOOPBACK_NONE BIT(0)
317#define QED_LINK_LOOPBACK_INT_PHY BIT(1)
318#define QED_LINK_LOOPBACK_EXT_PHY BIT(2)
319#define QED_LINK_LOOPBACK_EXT BIT(3)
320#define QED_LINK_LOOPBACK_MAC BIT(4)
321 u32 loopback_mode;
fe56b9e6
YM		 322};
323
324struct qed_link_output {
325 bool link_up;
326
d194fd26
YM		 327 /* In QED_LM_* defs */
328 u32 supported_caps;
329 u32 advertised_caps;
330 u32 lp_caps;
331
fe56b9e6
YM		 332 u32 speed; /* In Mb/s */
333 u8 duplex; /* In DUPLEX defs */
334 u8 port; /* In PORT defs */
335 bool autoneg;
336 u32 pause_config;
337};
338
1408cc1f
YM		 339struct qed_probe_params {
340 enum qed_protocol protocol;
341 u32 dp_module;
342 u8 dp_level;
343 bool is_vf;
344};
345
fe56b9e6
YM		 346#define QED_DRV_VER_STR_SIZE 12
347struct qed_slowpath_params {
348 u32 int_mode;
349 u8 drv_major;
350 u8 drv_minor;
351 u8 drv_rev;
352 u8 drv_eng;
353 u8 name[QED_DRV_VER_STR_SIZE];
354};
355
356#define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */
357
358struct qed_int_info {
359 struct msix_entry *msix;
360 u8 msix_cnt;
361
362 /* This should be updated by the protocol driver */
363 u8 used_cnt;
364};
365
366struct qed_common_cb_ops {
367 void (*link_update)(void *dev,
368 struct qed_link_output *link);
369};
370
03dc76ca
SRK		 371struct qed_selftest_ops {
372/**
373 * @brief selftest_interrupt - Perform interrupt test
374 *
375 * @param cdev
376 *
377 * @return 0 on success, error otherwise.
378 */
379 int (*selftest_interrupt)(struct qed_dev *cdev);
380
381/**
382 * @brief selftest_memory - Perform memory test
383 *
384 * @param cdev
385 *
386 * @return 0 on success, error otherwise.
387 */
388 int (*selftest_memory)(struct qed_dev *cdev);
389
390/**
391 * @brief selftest_register - Perform register test
392 *
393 * @param cdev
394 *
395 * @return 0 on success, error otherwise.
396 */
397 int (*selftest_register)(struct qed_dev *cdev);
398
399/**
400 * @brief selftest_clock - Perform clock test
401 *
402 * @param cdev
403 *
404 * @return 0 on success, error otherwise.
405 */
406 int (*selftest_clock)(struct qed_dev *cdev);
7a4b21b7
MY		 407
408/**
409 * @brief selftest_nvram - Perform nvram test
410 *
411 * @param cdev
412 *
413 * @return 0 on success, error otherwise.
414 */
415 int (*selftest_nvram) (struct qed_dev *cdev);
03dc76ca
SRK		 416};
417
fe56b9e6 418struct qed_common_ops {
03dc76ca
SRK		 419 struct qed_selftest_ops *selftest;
420
fe56b9e6 421 struct qed_dev* (*probe)(struct pci_dev *dev,
1408cc1f 422 struct qed_probe_params *params);
fe56b9e6
YM		 423
424 void (*remove)(struct qed_dev *cdev);
425
426 int (*set_power_state)(struct qed_dev *cdev,
427 pci_power_t state);
428
429 void (*set_id)(struct qed_dev *cdev,
430 char name[],
431 char ver_str[]);
432
433 /* Client drivers need to make this call before slowpath_start.
434 * PF params required for the call before slowpath_start is
435 * documented within the qed_pf_params structure definition.
436 */
437 void (*update_pf_params)(struct qed_dev *cdev,
438 struct qed_pf_params *params);
439 int (*slowpath_start)(struct qed_dev *cdev,
440 struct qed_slowpath_params *params);
441
442 int (*slowpath_stop)(struct qed_dev *cdev);
443
444 /* Requests to use `cnt' interrupts for fastpath.
445 * upon success, returns number of interrupts allocated for fastpath.
446 */
447 int (*set_fp_int)(struct qed_dev *cdev,
448 u16 cnt);
449
450 /* Fills `info' with pointers required for utilizing interrupts */
451 int (*get_fp_int)(struct qed_dev *cdev,
452 struct qed_int_info *info);
453
454 u32 (*sb_init)(struct qed_dev *cdev,
455 struct qed_sb_info *sb_info,
456 void *sb_virt_addr,
457 dma_addr_t sb_phy_addr,
458 u16 sb_id,
459 enum qed_sb_type type);
460
461 u32 (*sb_release)(struct qed_dev *cdev,
462 struct qed_sb_info *sb_info,
463 u16 sb_id);
464
465 void (*simd_handler_config)(struct qed_dev *cdev,
466 void *token,
467 int index,
468 void (*handler)(void *));
469
470 void (*simd_handler_clean)(struct qed_dev *cdev,
471 int index);
fe7cd2bf 472
e0971c83
TT		 473 int (*dbg_all_data) (struct qed_dev *cdev, void *buffer);
474
475 int (*dbg_all_data_size) (struct qed_dev *cdev);
476
fe7cd2bf
YM		 477/**
478 * @brief can_link_change - can the instance change the link or not
479 *
480 * @param cdev
481 *
482 * @return true if link-change is allowed, false otherwise.
483 */
484 bool (*can_link_change)(struct qed_dev *cdev);
485
fe56b9e6
YM		 486/**
487 * @brief set_link - set links according to params
488 *
489 * @param cdev
490 * @param params - values used to override the default link configuration
491 *
492 * @return 0 on success, error otherwise.
493 */
494 int (*set_link)(struct qed_dev *cdev,
495 struct qed_link_params *params);
496
497/**
498 * @brief get_link - returns the current link state.
499 *
500 * @param cdev
501 * @param if_link - structure to be filled with current link configuration.
502 */
503 void (*get_link)(struct qed_dev *cdev,
504 struct qed_link_output *if_link);
505
506/**
507 * @brief - drains chip in case Tx completions fail to arrive due to pause.
508 *
509 * @param cdev
510 */
511 int (*drain)(struct qed_dev *cdev);
512
513/**
514 * @brief update_msglvl - update module debug level
515 *
516 * @param cdev
517 * @param dp_module
518 * @param dp_level
519 */
520 void (*update_msglvl)(struct qed_dev *cdev,
521 u32 dp_module,
522 u8 dp_level);
523
524 int (*chain_alloc)(struct qed_dev *cdev,
525 enum qed_chain_use_mode intended_use,
526 enum qed_chain_mode mode,
a91eb52a
YM		 527 enum qed_chain_cnt_type cnt_type,
528 u32 num_elems,
fe56b9e6
YM		 529 size_t elem_size,
530 struct qed_chain *p_chain);
531
532 void (*chain_free)(struct qed_dev *cdev,
533 struct qed_chain *p_chain);
91420b83 534
722003ac
SRK		 535/**
536 * @brief get_coalesce - Get coalesce parameters in usec
537 *
538 * @param cdev
539 * @param rx_coal - Rx coalesce value in usec
540 * @param tx_coal - Tx coalesce value in usec
541 *
542 */
543 void (*get_coalesce)(struct qed_dev *cdev, u16 *rx_coal, u16 *tx_coal);
544
545/**
546 * @brief set_coalesce - Configure Rx coalesce value in usec
547 *
548 * @param cdev
549 * @param rx_coal - Rx coalesce value in usec
550 * @param tx_coal - Tx coalesce value in usec
551 * @param qid - Queue index
552 * @param sb_id - Status Block Id
553 *
554 * @return 0 on success, error otherwise.
555 */
556 int (*set_coalesce)(struct qed_dev *cdev, u16 rx_coal, u16 tx_coal,
557 u8 qid, u16 sb_id);
558
91420b83
SK		 559/**
560 * @brief set_led - Configure LED mode
561 *
562 * @param cdev
563 * @param mode - LED mode
564 *
565 * @return 0 on success, error otherwise.
566 */
567 int (*set_led)(struct qed_dev *cdev,
568 enum qed_led_mode mode);
0fefbfba
SK		 569
570/**
571 * @brief update_drv_state - API to inform the change in the driver state.
572 *
573 * @param cdev
574 * @param active
575 *
576 */
577 int (*update_drv_state)(struct qed_dev *cdev, bool active);
578
579/**
580 * @brief update_mac - API to inform the change in the mac address
581 *
582 * @param cdev
583 * @param mac
584 *
585 */
586 int (*update_mac)(struct qed_dev *cdev, u8 *mac);
587
588/**
589 * @brief update_mtu - API to inform the change in the mtu
590 *
591 * @param cdev
592 * @param mtu
593 *
594 */
595 int (*update_mtu)(struct qed_dev *cdev, u16 mtu);
14d39648
MY		 596
597/**
598 * @brief update_wol - update of changes in the WoL configuration
599 *
600 * @param cdev
601 * @param enabled - true iff WoL should be enabled.
602 */
603 int (*update_wol) (struct qed_dev *cdev, bool enabled);
fe56b9e6
YM		 604};
605
fe56b9e6
YM		 606#define MASK_FIELD(_name, _value) \
607 ((_value) &= (_name ## _MASK))
608
609#define FIELD_VALUE(_name, _value) \
610 ((_value & _name ## _MASK) << _name ## _SHIFT)
611
612#define SET_FIELD(value, name, flag) \
613 do { \
614 (value) &= ~(name ## _MASK << name ## _SHIFT); \
615 (value) |= (((u64)flag) << (name ## _SHIFT)); \
616 } while (0)
617
618#define GET_FIELD(value, name) \
619 (((value) >> (name ## _SHIFT)) & name ## _MASK)
620
621/* Debug print definitions */
622#define DP_ERR(cdev, fmt, ...) \
623 pr_err("[%s:%d(%s)]" fmt, \
624 __func__, __LINE__, \
625 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
626 ## __VA_ARGS__) \
627
628#define DP_NOTICE(cdev, fmt, ...) \
629 do { \
630 if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \
631 pr_notice("[%s:%d(%s)]" fmt, \
632 __func__, __LINE__, \
633 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
634 ## __VA_ARGS__); \
635 \
636 } \
637 } while (0)
638
639#define DP_INFO(cdev, fmt, ...) \
640 do { \
641 if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) { \
642 pr_notice("[%s:%d(%s)]" fmt, \
643 __func__, __LINE__, \
644 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
645 ## __VA_ARGS__); \
646 } \
647 } while (0)
648
649#define DP_VERBOSE(cdev, module, fmt, ...) \
650 do { \
651 if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) && \
652 ((cdev)->dp_module & module))) { \
653 pr_notice("[%s:%d(%s)]" fmt, \
654 __func__, __LINE__, \
655 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
656 ## __VA_ARGS__); \
657 } \
658 } while (0)
659
660enum DP_LEVEL {
661 QED_LEVEL_VERBOSE = 0x0,
662 QED_LEVEL_INFO = 0x1,
663 QED_LEVEL_NOTICE = 0x2,
664 QED_LEVEL_ERR = 0x3,
665};
666
667#define QED_LOG_LEVEL_SHIFT (30)
668#define QED_LOG_VERBOSE_MASK (0x3fffffff)
669#define QED_LOG_INFO_MASK (0x40000000)
670#define QED_LOG_NOTICE_MASK (0x80000000)
671
672enum DP_MODULE {
673 QED_MSG_SPQ = 0x10000,
674 QED_MSG_STATS = 0x20000,
675 QED_MSG_DCB = 0x40000,
676 QED_MSG_IOV = 0x80000,
677 QED_MSG_SP = 0x100000,
678 QED_MSG_STORAGE = 0x200000,
679 QED_MSG_CXT = 0x800000,
0a7fb11c 680 QED_MSG_LL2 = 0x1000000,
fe56b9e6 681 QED_MSG_ILT = 0x2000000,
51ff1725 682 QED_MSG_RDMA = 0x4000000,
fe56b9e6
YM		 683 QED_MSG_DEBUG = 0x8000000,
684 /* to be added...up to 0x8000000 */
685};
686
fc48b7a6
YM		 687enum qed_mf_mode {
688 QED_MF_DEFAULT,
689 QED_MF_OVLAN,
690 QED_MF_NPAR,
691};
692
fe56b9e6
YM		 693struct qed_eth_stats {
694 u64 no_buff_discards;
695 u64 packet_too_big_discard;
696 u64 ttl0_discard;
697 u64 rx_ucast_bytes;
698 u64 rx_mcast_bytes;
699 u64 rx_bcast_bytes;
700 u64 rx_ucast_pkts;
701 u64 rx_mcast_pkts;
702 u64 rx_bcast_pkts;
703 u64 mftag_filter_discards;
704 u64 mac_filter_discards;
705 u64 tx_ucast_bytes;
706 u64 tx_mcast_bytes;
707 u64 tx_bcast_bytes;
708 u64 tx_ucast_pkts;
709 u64 tx_mcast_pkts;
710 u64 tx_bcast_pkts;
711 u64 tx_err_drop_pkts;
712 u64 tpa_coalesced_pkts;
713 u64 tpa_coalesced_events;
714 u64 tpa_aborts_num;
715 u64 tpa_not_coalesced_pkts;
716 u64 tpa_coalesced_bytes;
717
718 /* port */
719 u64 rx_64_byte_packets;
d4967cf3
YM		 720 u64 rx_65_to_127_byte_packets;
721 u64 rx_128_to_255_byte_packets;
722 u64 rx_256_to_511_byte_packets;
723 u64 rx_512_to_1023_byte_packets;
724 u64 rx_1024_to_1518_byte_packets;
725 u64 rx_1519_to_1522_byte_packets;
726 u64 rx_1519_to_2047_byte_packets;
727 u64 rx_2048_to_4095_byte_packets;
728 u64 rx_4096_to_9216_byte_packets;
729 u64 rx_9217_to_16383_byte_packets;
fe56b9e6
YM		 730 u64 rx_crc_errors;
731 u64 rx_mac_crtl_frames;
732 u64 rx_pause_frames;
733 u64 rx_pfc_frames;
734 u64 rx_align_errors;
735 u64 rx_carrier_errors;
736 u64 rx_oversize_packets;
737 u64 rx_jabbers;
738 u64 rx_undersize_packets;
739 u64 rx_fragments;
740 u64 tx_64_byte_packets;
741 u64 tx_65_to_127_byte_packets;
742 u64 tx_128_to_255_byte_packets;
743 u64 tx_256_to_511_byte_packets;
744 u64 tx_512_to_1023_byte_packets;
745 u64 tx_1024_to_1518_byte_packets;
746 u64 tx_1519_to_2047_byte_packets;
747 u64 tx_2048_to_4095_byte_packets;
748 u64 tx_4096_to_9216_byte_packets;
749 u64 tx_9217_to_16383_byte_packets;
750 u64 tx_pause_frames;
751 u64 tx_pfc_frames;
752 u64 tx_lpi_entry_count;
753 u64 tx_total_collisions;
754 u64 brb_truncates;
755 u64 brb_discards;
756 u64 rx_mac_bytes;
757 u64 rx_mac_uc_packets;
758 u64 rx_mac_mc_packets;
759 u64 rx_mac_bc_packets;
760 u64 rx_mac_frames_ok;
761 u64 tx_mac_bytes;
762 u64 tx_mac_uc_packets;
763 u64 tx_mac_mc_packets;
764 u64 tx_mac_bc_packets;
765 u64 tx_mac_ctrl_frames;
766};
767
768#define QED_SB_IDX 0x0002
769
770#define RX_PI 0
771#define TX_PI(tc) (RX_PI + 1 + tc)
772
4ac801b7
YM		 773struct qed_sb_cnt_info {
774 int sb_cnt;
775 int sb_iov_cnt;
776 int sb_free_blk;
777};
778
fe56b9e6
YM		 779static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info)
780{
781 u32 prod = 0;
782 u16 rc = 0;
783
784 prod = le32_to_cpu(sb_info->sb_virt->prod_index) &
785 STATUS_BLOCK_PROD_INDEX_MASK;
786 if (sb_info->sb_ack != prod) {
787 sb_info->sb_ack = prod;
788 rc |= QED_SB_IDX;
789 }
790
791 /* Let SB update */
792 mmiowb();
793 return rc;
794}
795
796/**
797 *
798 * @brief This function creates an update command for interrupts that is
799 * written to the IGU.
800 *
801 * @param sb_info - This is the structure allocated and
802 * initialized per status block. Assumption is
803 * that it was initialized using qed_sb_init
804 * @param int_cmd - Enable/Disable/Nop
805 * @param upd_flg - whether igu consumer should be
806 * updated.
807 *
808 * @return inline void
809 */
810static inline void qed_sb_ack(struct qed_sb_info *sb_info,
811 enum igu_int_cmd int_cmd,
812 u8 upd_flg)
813{
814 struct igu_prod_cons_update igu_ack = { 0 };
815
816 igu_ack.sb_id_and_flags =
817 ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
818 (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
819 (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
820 (IGU_SEG_ACCESS_REG <<
821 IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
822
823 DIRECT_REG_WR(sb_info->igu_addr, igu_ack.sb_id_and_flags);
824
825 /* Both segments (interrupts & acks) are written to same place address;
826 * Need to guarantee all commands will be received (in-order) by HW.
827 */
828 mmiowb();
829 barrier();
830}
831
832static inline void __internal_ram_wr(void *p_hwfn,
833 void __iomem *addr,
834 int size,
835 u32 *data)
836
837{
838 unsigned int i;
839
840 for (i = 0; i < size / sizeof(*data); i++)
841 DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]);
842}
843
844static inline void internal_ram_wr(void __iomem *addr,
845 int size,
846 u32 *data)
847{
848 __internal_ram_wr(NULL, addr, size, data);
849}
850
8c5ebd0c
SRK		 851enum qed_rss_caps {
852 QED_RSS_IPV4 = 0x1,
853 QED_RSS_IPV6 = 0x2,
854 QED_RSS_IPV4_TCP = 0x4,
855 QED_RSS_IPV6_TCP = 0x8,
856 QED_RSS_IPV4_UDP = 0x10,
857 QED_RSS_IPV6_UDP = 0x20,
858};
859
860#define QED_RSS_IND_TABLE_SIZE 128
861#define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */
fe56b9e6 862#endif
Linux 6.x block layer and io_uring tree(s)