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qed: Add nvram selftest
[linux-2.6-block.git] / include / linux / qed / qed_if.h
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fe56b9e6
YM		 1/* QLogic qed NIC Driver
2 *
3 * Copyright (c) 2015 QLogic Corporation
4 *
5 * This software is available under the terms of the GNU General Public License
6 * (GPL) Version 2, available from the file COPYING in the main directory of
7 * this source tree.
8 */
9
10#ifndef _QED_IF_H
11#define _QED_IF_H
12
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/netdevice.h>
16#include <linux/pci.h>
17#include <linux/skbuff.h>
18#include <linux/types.h>
19#include <asm/byteorder.h>
20#include <linux/io.h>
21#include <linux/compiler.h>
22#include <linux/kernel.h>
23#include <linux/list.h>
24#include <linux/slab.h>
25#include <linux/qed/common_hsi.h>
26#include <linux/qed/qed_chain.h>
27
39651abd
SRK		 28enum dcbx_protocol_type {
29 DCBX_PROTOCOL_ISCSI,
30 DCBX_PROTOCOL_FCOE,
31 DCBX_PROTOCOL_ROCE,
32 DCBX_PROTOCOL_ROCE_V2,
33 DCBX_PROTOCOL_ETH,
34 DCBX_MAX_PROTOCOL_TYPE
35};
36
51ff1725
RA		 37#define QED_ROCE_PROTOCOL_INDEX (3)
38
6ad8c632
SRK		 39#ifdef CONFIG_DCB
40#define QED_LLDP_CHASSIS_ID_STAT_LEN 4
41#define QED_LLDP_PORT_ID_STAT_LEN 4
42#define QED_DCBX_MAX_APP_PROTOCOL 32
43#define QED_MAX_PFC_PRIORITIES 8
44#define QED_DCBX_DSCP_SIZE 64
45
46struct qed_dcbx_lldp_remote {
47 u32 peer_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
48 u32 peer_port_id[QED_LLDP_PORT_ID_STAT_LEN];
49 bool enable_rx;
50 bool enable_tx;
51 u32 tx_interval;
52 u32 max_credit;
53};
54
55struct qed_dcbx_lldp_local {
56 u32 local_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
57 u32 local_port_id[QED_LLDP_PORT_ID_STAT_LEN];
58};
59
60struct qed_dcbx_app_prio {
61 u8 roce;
62 u8 roce_v2;
63 u8 fcoe;
64 u8 iscsi;
65 u8 eth;
66};
67
68struct qed_dbcx_pfc_params {
69 bool willing;
70 bool enabled;
71 u8 prio[QED_MAX_PFC_PRIORITIES];
72 u8 max_tc;
73};
74
59bcb797
SRK		 75enum qed_dcbx_sf_ieee_type {
76 QED_DCBX_SF_IEEE_ETHTYPE,
77 QED_DCBX_SF_IEEE_TCP_PORT,
78 QED_DCBX_SF_IEEE_UDP_PORT,
79 QED_DCBX_SF_IEEE_TCP_UDP_PORT
80};
81
6ad8c632
SRK		 82struct qed_app_entry {
83 bool ethtype;
59bcb797 84 enum qed_dcbx_sf_ieee_type sf_ieee;
6ad8c632
SRK		 85 bool enabled;
86 u8 prio;
87 u16 proto_id;
88 enum dcbx_protocol_type proto_type;
89};
90
91struct qed_dcbx_params {
92 struct qed_app_entry app_entry[QED_DCBX_MAX_APP_PROTOCOL];
93 u16 num_app_entries;
94 bool app_willing;
95 bool app_valid;
96 bool app_error;
97 bool ets_willing;
98 bool ets_enabled;
99 bool ets_cbs;
100 bool valid;
101 u8 ets_pri_tc_tbl[QED_MAX_PFC_PRIORITIES];
102 u8 ets_tc_bw_tbl[QED_MAX_PFC_PRIORITIES];
103 u8 ets_tc_tsa_tbl[QED_MAX_PFC_PRIORITIES];
104 struct qed_dbcx_pfc_params pfc;
105 u8 max_ets_tc;
106};
107
108struct qed_dcbx_admin_params {
109 struct qed_dcbx_params params;
110 bool valid;
111};
112
113struct qed_dcbx_remote_params {
114 struct qed_dcbx_params params;
115 bool valid;
116};
117
118struct qed_dcbx_operational_params {
119 struct qed_dcbx_app_prio app_prio;
120 struct qed_dcbx_params params;
121 bool valid;
122 bool enabled;
123 bool ieee;
124 bool cee;
125 u32 err;
126};
127
128struct qed_dcbx_get {
129 struct qed_dcbx_operational_params operational;
130 struct qed_dcbx_lldp_remote lldp_remote;
131 struct qed_dcbx_lldp_local lldp_local;
132 struct qed_dcbx_remote_params remote;
133 struct qed_dcbx_admin_params local;
134};
135#endif
136
91420b83
SK		 137enum qed_led_mode {
138 QED_LED_MODE_OFF,
139 QED_LED_MODE_ON,
140 QED_LED_MODE_RESTORE
141};
142
fe56b9e6
YM		 143#define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \
144 (void __iomem *)(reg_addr))
145
146#define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr))
147
148#define QED_COALESCE_MAX 0xFF
0e191827 149#define QED_DEFAULT_RX_USECS 12
fe56b9e6
YM		 150
151/* forward */
152struct qed_dev;
153
154struct qed_eth_pf_params {
155 /* The following parameters are used during HW-init
156 * and these parameters need to be passed as arguments
157 * to update_pf_params routine invoked before slowpath start
158 */
159 u16 num_cons;
160};
161
c5ac9319
YM		 162/* Most of the the parameters below are described in the FW iSCSI / TCP HSI */
163struct qed_iscsi_pf_params {
164 u64 glbl_q_params_addr;
165 u64 bdq_pbl_base_addr[2];
166 u32 max_cwnd;
167 u16 cq_num_entries;
168 u16 cmdq_num_entries;
169 u16 dup_ack_threshold;
170 u16 tx_sws_timer;
171 u16 min_rto;
172 u16 min_rto_rt;
173 u16 max_rto;
174
175 /* The following parameters are used during HW-init
176 * and these parameters need to be passed as arguments
177 * to update_pf_params routine invoked before slowpath start
178 */
179 u16 num_cons;
180 u16 num_tasks;
181
182 /* The following parameters are used during protocol-init */
183 u16 half_way_close_timeout;
184 u16 bdq_xoff_threshold[2];
185 u16 bdq_xon_threshold[2];
186 u16 cmdq_xoff_threshold;
187 u16 cmdq_xon_threshold;
188 u16 rq_buffer_size;
189
190 u8 num_sq_pages_in_ring;
191 u8 num_r2tq_pages_in_ring;
192 u8 num_uhq_pages_in_ring;
193 u8 num_queues;
194 u8 log_page_size;
195 u8 rqe_log_size;
196 u8 max_fin_rt;
197 u8 gl_rq_pi;
198 u8 gl_cmd_pi;
199 u8 debug_mode;
200 u8 ll2_ooo_queue_id;
201 u8 ooo_enable;
202
203 u8 is_target;
204 u8 bdq_pbl_num_entries[2];
205};
206
207struct qed_rdma_pf_params {
208 /* Supplied to QED during resource allocation (may affect the ILT and
209 * the doorbell BAR).
210 */
211 u32 min_dpis; /* number of requested DPIs */
212 u32 num_mrs; /* number of requested memory regions */
213 u32 num_qps; /* number of requested Queue Pairs */
214 u32 num_srqs; /* number of requested SRQ */
215 u8 roce_edpm_mode; /* see QED_ROCE_EDPM_MODE_ENABLE */
216 u8 gl_pi; /* protocol index */
217
218 /* Will allocate rate limiters to be used with QPs */
219 u8 enable_dcqcn;
220};
221
fe56b9e6
YM		 222struct qed_pf_params {
223 struct qed_eth_pf_params eth_pf_params;
c5ac9319
YM		 224 struct qed_iscsi_pf_params iscsi_pf_params;
225 struct qed_rdma_pf_params rdma_pf_params;
fe56b9e6
YM		 226};
227
228enum qed_int_mode {
229 QED_INT_MODE_INTA,
230 QED_INT_MODE_MSIX,
231 QED_INT_MODE_MSI,
232 QED_INT_MODE_POLL,
233};
234
235struct qed_sb_info {
236 struct status_block *sb_virt;
237 dma_addr_t sb_phys;
238 u32 sb_ack; /* Last given ack */
239 u16 igu_sb_id;
240 void __iomem *igu_addr;
241 u8 flags;
242#define QED_SB_INFO_INIT 0x1
243#define QED_SB_INFO_SETUP 0x2
244
245 struct qed_dev *cdev;
246};
247
248struct qed_dev_info {
249 unsigned long pci_mem_start;
250 unsigned long pci_mem_end;
251 unsigned int pci_irq;
252 u8 num_hwfns;
253
254 u8 hw_mac[ETH_ALEN];
fc48b7a6 255 bool is_mf_default;
fe56b9e6
YM		 256
257 /* FW version */
258 u16 fw_major;
259 u16 fw_minor;
260 u16 fw_rev;
261 u16 fw_eng;
262
263 /* MFW version */
264 u32 mfw_rev;
265
266 u32 flash_size;
267 u8 mf_mode;
831bfb0e 268 bool tx_switching;
cee9fbd8 269 bool rdma_supported;
0fefbfba 270 u16 mtu;
fe56b9e6
YM		 271};
272
273enum qed_sb_type {
274 QED_SB_TYPE_L2_QUEUE,
51ff1725 275 QED_SB_TYPE_CNQ,
fe56b9e6
YM		 276};
277
278enum qed_protocol {
279 QED_PROTOCOL_ETH,
c5ac9319 280 QED_PROTOCOL_ISCSI,
fe56b9e6
YM		 281};
282
054c67d1
SRK		 283enum qed_link_mode_bits {
284 QED_LM_FIBRE_BIT = BIT(0),
285 QED_LM_Autoneg_BIT = BIT(1),
286 QED_LM_Asym_Pause_BIT = BIT(2),
287 QED_LM_Pause_BIT = BIT(3),
288 QED_LM_1000baseT_Half_BIT = BIT(4),
289 QED_LM_1000baseT_Full_BIT = BIT(5),
290 QED_LM_10000baseKR_Full_BIT = BIT(6),
291 QED_LM_25000baseKR_Full_BIT = BIT(7),
292 QED_LM_40000baseLR4_Full_BIT = BIT(8),
293 QED_LM_50000baseKR2_Full_BIT = BIT(9),
294 QED_LM_100000baseKR4_Full_BIT = BIT(10),
295 QED_LM_COUNT = 11
296};
297
fe56b9e6
YM		 298struct qed_link_params {
299 bool link_up;
300
301#define QED_LINK_OVERRIDE_SPEED_AUTONEG BIT(0)
302#define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS BIT(1)
303#define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED BIT(2)
304#define QED_LINK_OVERRIDE_PAUSE_CONFIG BIT(3)
03dc76ca 305#define QED_LINK_OVERRIDE_LOOPBACK_MODE BIT(4)
fe56b9e6
YM		 306 u32 override_flags;
307 bool autoneg;
308 u32 adv_speeds;
309 u32 forced_speed;
310#define QED_LINK_PAUSE_AUTONEG_ENABLE BIT(0)
311#define QED_LINK_PAUSE_RX_ENABLE BIT(1)
312#define QED_LINK_PAUSE_TX_ENABLE BIT(2)
313 u32 pause_config;
03dc76ca
SRK		 314#define QED_LINK_LOOPBACK_NONE BIT(0)
315#define QED_LINK_LOOPBACK_INT_PHY BIT(1)
316#define QED_LINK_LOOPBACK_EXT_PHY BIT(2)
317#define QED_LINK_LOOPBACK_EXT BIT(3)
318#define QED_LINK_LOOPBACK_MAC BIT(4)
319 u32 loopback_mode;
fe56b9e6
YM		 320};
321
322struct qed_link_output {
323 bool link_up;
324
d194fd26
YM		 325 /* In QED_LM_* defs */
326 u32 supported_caps;
327 u32 advertised_caps;
328 u32 lp_caps;
329
fe56b9e6
YM		 330 u32 speed; /* In Mb/s */
331 u8 duplex; /* In DUPLEX defs */
332 u8 port; /* In PORT defs */
333 bool autoneg;
334 u32 pause_config;
335};
336
1408cc1f
YM		 337struct qed_probe_params {
338 enum qed_protocol protocol;
339 u32 dp_module;
340 u8 dp_level;
341 bool is_vf;
342};
343
fe56b9e6
YM		 344#define QED_DRV_VER_STR_SIZE 12
345struct qed_slowpath_params {
346 u32 int_mode;
347 u8 drv_major;
348 u8 drv_minor;
349 u8 drv_rev;
350 u8 drv_eng;
351 u8 name[QED_DRV_VER_STR_SIZE];
352};
353
354#define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */
355
356struct qed_int_info {
357 struct msix_entry *msix;
358 u8 msix_cnt;
359
360 /* This should be updated by the protocol driver */
361 u8 used_cnt;
362};
363
364struct qed_common_cb_ops {
365 void (*link_update)(void *dev,
366 struct qed_link_output *link);
367};
368
03dc76ca
SRK		 369struct qed_selftest_ops {
370/**
371 * @brief selftest_interrupt - Perform interrupt test
372 *
373 * @param cdev
374 *
375 * @return 0 on success, error otherwise.
376 */
377 int (*selftest_interrupt)(struct qed_dev *cdev);
378
379/**
380 * @brief selftest_memory - Perform memory test
381 *
382 * @param cdev
383 *
384 * @return 0 on success, error otherwise.
385 */
386 int (*selftest_memory)(struct qed_dev *cdev);
387
388/**
389 * @brief selftest_register - Perform register test
390 *
391 * @param cdev
392 *
393 * @return 0 on success, error otherwise.
394 */
395 int (*selftest_register)(struct qed_dev *cdev);
396
397/**
398 * @brief selftest_clock - Perform clock test
399 *
400 * @param cdev
401 *
402 * @return 0 on success, error otherwise.
403 */
404 int (*selftest_clock)(struct qed_dev *cdev);
7a4b21b7
MY		 405
406/**
407 * @brief selftest_nvram - Perform nvram test
408 *
409 * @param cdev
410 *
411 * @return 0 on success, error otherwise.
412 */
413 int (*selftest_nvram) (struct qed_dev *cdev);
03dc76ca
SRK		 414};
415
fe56b9e6 416struct qed_common_ops {
03dc76ca
SRK		 417 struct qed_selftest_ops *selftest;
418
fe56b9e6 419 struct qed_dev* (*probe)(struct pci_dev *dev,
1408cc1f 420 struct qed_probe_params *params);
fe56b9e6
YM		 421
422 void (*remove)(struct qed_dev *cdev);
423
424 int (*set_power_state)(struct qed_dev *cdev,
425 pci_power_t state);
426
427 void (*set_id)(struct qed_dev *cdev,
428 char name[],
429 char ver_str[]);
430
431 /* Client drivers need to make this call before slowpath_start.
432 * PF params required for the call before slowpath_start is
433 * documented within the qed_pf_params structure definition.
434 */
435 void (*update_pf_params)(struct qed_dev *cdev,
436 struct qed_pf_params *params);
437 int (*slowpath_start)(struct qed_dev *cdev,
438 struct qed_slowpath_params *params);
439
440 int (*slowpath_stop)(struct qed_dev *cdev);
441
442 /* Requests to use `cnt' interrupts for fastpath.
443 * upon success, returns number of interrupts allocated for fastpath.
444 */
445 int (*set_fp_int)(struct qed_dev *cdev,
446 u16 cnt);
447
448 /* Fills `info' with pointers required for utilizing interrupts */
449 int (*get_fp_int)(struct qed_dev *cdev,
450 struct qed_int_info *info);
451
452 u32 (*sb_init)(struct qed_dev *cdev,
453 struct qed_sb_info *sb_info,
454 void *sb_virt_addr,
455 dma_addr_t sb_phy_addr,
456 u16 sb_id,
457 enum qed_sb_type type);
458
459 u32 (*sb_release)(struct qed_dev *cdev,
460 struct qed_sb_info *sb_info,
461 u16 sb_id);
462
463 void (*simd_handler_config)(struct qed_dev *cdev,
464 void *token,
465 int index,
466 void (*handler)(void *));
467
468 void (*simd_handler_clean)(struct qed_dev *cdev,
469 int index);
fe7cd2bf 470
e0971c83
TT		 471 int (*dbg_all_data) (struct qed_dev *cdev, void *buffer);
472
473 int (*dbg_all_data_size) (struct qed_dev *cdev);
474
fe7cd2bf
YM		 475/**
476 * @brief can_link_change - can the instance change the link or not
477 *
478 * @param cdev
479 *
480 * @return true if link-change is allowed, false otherwise.
481 */
482 bool (*can_link_change)(struct qed_dev *cdev);
483
fe56b9e6
YM		 484/**
485 * @brief set_link - set links according to params
486 *
487 * @param cdev
488 * @param params - values used to override the default link configuration
489 *
490 * @return 0 on success, error otherwise.
491 */
492 int (*set_link)(struct qed_dev *cdev,
493 struct qed_link_params *params);
494
495/**
496 * @brief get_link - returns the current link state.
497 *
498 * @param cdev
499 * @param if_link - structure to be filled with current link configuration.
500 */
501 void (*get_link)(struct qed_dev *cdev,
502 struct qed_link_output *if_link);
503
504/**
505 * @brief - drains chip in case Tx completions fail to arrive due to pause.
506 *
507 * @param cdev
508 */
509 int (*drain)(struct qed_dev *cdev);
510
511/**
512 * @brief update_msglvl - update module debug level
513 *
514 * @param cdev
515 * @param dp_module
516 * @param dp_level
517 */
518 void (*update_msglvl)(struct qed_dev *cdev,
519 u32 dp_module,
520 u8 dp_level);
521
522 int (*chain_alloc)(struct qed_dev *cdev,
523 enum qed_chain_use_mode intended_use,
524 enum qed_chain_mode mode,
a91eb52a
YM		 525 enum qed_chain_cnt_type cnt_type,
526 u32 num_elems,
fe56b9e6
YM		 527 size_t elem_size,
528 struct qed_chain *p_chain);
529
530 void (*chain_free)(struct qed_dev *cdev,
531 struct qed_chain *p_chain);
91420b83 532
722003ac
SRK		 533/**
534 * @brief get_coalesce - Get coalesce parameters in usec
535 *
536 * @param cdev
537 * @param rx_coal - Rx coalesce value in usec
538 * @param tx_coal - Tx coalesce value in usec
539 *
540 */
541 void (*get_coalesce)(struct qed_dev *cdev, u16 *rx_coal, u16 *tx_coal);
542
543/**
544 * @brief set_coalesce - Configure Rx coalesce value in usec
545 *
546 * @param cdev
547 * @param rx_coal - Rx coalesce value in usec
548 * @param tx_coal - Tx coalesce value in usec
549 * @param qid - Queue index
550 * @param sb_id - Status Block Id
551 *
552 * @return 0 on success, error otherwise.
553 */
554 int (*set_coalesce)(struct qed_dev *cdev, u16 rx_coal, u16 tx_coal,
555 u8 qid, u16 sb_id);
556
91420b83
SK		 557/**
558 * @brief set_led - Configure LED mode
559 *
560 * @param cdev
561 * @param mode - LED mode
562 *
563 * @return 0 on success, error otherwise.
564 */
565 int (*set_led)(struct qed_dev *cdev,
566 enum qed_led_mode mode);
0fefbfba
SK		 567
568/**
569 * @brief update_drv_state - API to inform the change in the driver state.
570 *
571 * @param cdev
572 * @param active
573 *
574 */
575 int (*update_drv_state)(struct qed_dev *cdev, bool active);
576
577/**
578 * @brief update_mac - API to inform the change in the mac address
579 *
580 * @param cdev
581 * @param mac
582 *
583 */
584 int (*update_mac)(struct qed_dev *cdev, u8 *mac);
585
586/**
587 * @brief update_mtu - API to inform the change in the mtu
588 *
589 * @param cdev
590 * @param mtu
591 *
592 */
593 int (*update_mtu)(struct qed_dev *cdev, u16 mtu);
fe56b9e6
YM		 594};
595
fe56b9e6
YM		 596#define MASK_FIELD(_name, _value) \
597 ((_value) &= (_name ## _MASK))
598
599#define FIELD_VALUE(_name, _value) \
600 ((_value & _name ## _MASK) << _name ## _SHIFT)
601
602#define SET_FIELD(value, name, flag) \
603 do { \
604 (value) &= ~(name ## _MASK << name ## _SHIFT); \
605 (value) |= (((u64)flag) << (name ## _SHIFT)); \
606 } while (0)
607
608#define GET_FIELD(value, name) \
609 (((value) >> (name ## _SHIFT)) & name ## _MASK)
610
611/* Debug print definitions */
612#define DP_ERR(cdev, fmt, ...) \
613 pr_err("[%s:%d(%s)]" fmt, \
614 __func__, __LINE__, \
615 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
616 ## __VA_ARGS__) \
617
618#define DP_NOTICE(cdev, fmt, ...) \
619 do { \
620 if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \
621 pr_notice("[%s:%d(%s)]" fmt, \
622 __func__, __LINE__, \
623 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
624 ## __VA_ARGS__); \
625 \
626 } \
627 } while (0)
628
629#define DP_INFO(cdev, fmt, ...) \
630 do { \
631 if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) { \
632 pr_notice("[%s:%d(%s)]" fmt, \
633 __func__, __LINE__, \
634 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
635 ## __VA_ARGS__); \
636 } \
637 } while (0)
638
639#define DP_VERBOSE(cdev, module, fmt, ...) \
640 do { \
641 if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) && \
642 ((cdev)->dp_module & module))) { \
643 pr_notice("[%s:%d(%s)]" fmt, \
644 __func__, __LINE__, \
645 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
646 ## __VA_ARGS__); \
647 } \
648 } while (0)
649
650enum DP_LEVEL {
651 QED_LEVEL_VERBOSE = 0x0,
652 QED_LEVEL_INFO = 0x1,
653 QED_LEVEL_NOTICE = 0x2,
654 QED_LEVEL_ERR = 0x3,
655};
656
657#define QED_LOG_LEVEL_SHIFT (30)
658#define QED_LOG_VERBOSE_MASK (0x3fffffff)
659#define QED_LOG_INFO_MASK (0x40000000)
660#define QED_LOG_NOTICE_MASK (0x80000000)
661
662enum DP_MODULE {
663 QED_MSG_SPQ = 0x10000,
664 QED_MSG_STATS = 0x20000,
665 QED_MSG_DCB = 0x40000,
666 QED_MSG_IOV = 0x80000,
667 QED_MSG_SP = 0x100000,
668 QED_MSG_STORAGE = 0x200000,
669 QED_MSG_CXT = 0x800000,
0a7fb11c 670 QED_MSG_LL2 = 0x1000000,
fe56b9e6 671 QED_MSG_ILT = 0x2000000,
51ff1725 672 QED_MSG_RDMA = 0x4000000,
fe56b9e6
YM		 673 QED_MSG_DEBUG = 0x8000000,
674 /* to be added...up to 0x8000000 */
675};
676
fc48b7a6
YM		 677enum qed_mf_mode {
678 QED_MF_DEFAULT,
679 QED_MF_OVLAN,
680 QED_MF_NPAR,
681};
682
fe56b9e6
YM		 683struct qed_eth_stats {
684 u64 no_buff_discards;
685 u64 packet_too_big_discard;
686 u64 ttl0_discard;
687 u64 rx_ucast_bytes;
688 u64 rx_mcast_bytes;
689 u64 rx_bcast_bytes;
690 u64 rx_ucast_pkts;
691 u64 rx_mcast_pkts;
692 u64 rx_bcast_pkts;
693 u64 mftag_filter_discards;
694 u64 mac_filter_discards;
695 u64 tx_ucast_bytes;
696 u64 tx_mcast_bytes;
697 u64 tx_bcast_bytes;
698 u64 tx_ucast_pkts;
699 u64 tx_mcast_pkts;
700 u64 tx_bcast_pkts;
701 u64 tx_err_drop_pkts;
702 u64 tpa_coalesced_pkts;
703 u64 tpa_coalesced_events;
704 u64 tpa_aborts_num;
705 u64 tpa_not_coalesced_pkts;
706 u64 tpa_coalesced_bytes;
707
708 /* port */
709 u64 rx_64_byte_packets;
d4967cf3
YM		 710 u64 rx_65_to_127_byte_packets;
711 u64 rx_128_to_255_byte_packets;
712 u64 rx_256_to_511_byte_packets;
713 u64 rx_512_to_1023_byte_packets;
714 u64 rx_1024_to_1518_byte_packets;
715 u64 rx_1519_to_1522_byte_packets;
716 u64 rx_1519_to_2047_byte_packets;
717 u64 rx_2048_to_4095_byte_packets;
718 u64 rx_4096_to_9216_byte_packets;
719 u64 rx_9217_to_16383_byte_packets;
fe56b9e6
YM		 720 u64 rx_crc_errors;
721 u64 rx_mac_crtl_frames;
722 u64 rx_pause_frames;
723 u64 rx_pfc_frames;
724 u64 rx_align_errors;
725 u64 rx_carrier_errors;
726 u64 rx_oversize_packets;
727 u64 rx_jabbers;
728 u64 rx_undersize_packets;
729 u64 rx_fragments;
730 u64 tx_64_byte_packets;
731 u64 tx_65_to_127_byte_packets;
732 u64 tx_128_to_255_byte_packets;
733 u64 tx_256_to_511_byte_packets;
734 u64 tx_512_to_1023_byte_packets;
735 u64 tx_1024_to_1518_byte_packets;
736 u64 tx_1519_to_2047_byte_packets;
737 u64 tx_2048_to_4095_byte_packets;
738 u64 tx_4096_to_9216_byte_packets;
739 u64 tx_9217_to_16383_byte_packets;
740 u64 tx_pause_frames;
741 u64 tx_pfc_frames;
742 u64 tx_lpi_entry_count;
743 u64 tx_total_collisions;
744 u64 brb_truncates;
745 u64 brb_discards;
746 u64 rx_mac_bytes;
747 u64 rx_mac_uc_packets;
748 u64 rx_mac_mc_packets;
749 u64 rx_mac_bc_packets;
750 u64 rx_mac_frames_ok;
751 u64 tx_mac_bytes;
752 u64 tx_mac_uc_packets;
753 u64 tx_mac_mc_packets;
754 u64 tx_mac_bc_packets;
755 u64 tx_mac_ctrl_frames;
756};
757
758#define QED_SB_IDX 0x0002
759
760#define RX_PI 0
761#define TX_PI(tc) (RX_PI + 1 + tc)
762
4ac801b7
YM		 763struct qed_sb_cnt_info {
764 int sb_cnt;
765 int sb_iov_cnt;
766 int sb_free_blk;
767};
768
fe56b9e6
YM		 769static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info)
770{
771 u32 prod = 0;
772 u16 rc = 0;
773
774 prod = le32_to_cpu(sb_info->sb_virt->prod_index) &
775 STATUS_BLOCK_PROD_INDEX_MASK;
776 if (sb_info->sb_ack != prod) {
777 sb_info->sb_ack = prod;
778 rc |= QED_SB_IDX;
779 }
780
781 /* Let SB update */
782 mmiowb();
783 return rc;
784}
785
786/**
787 *
788 * @brief This function creates an update command for interrupts that is
789 * written to the IGU.
790 *
791 * @param sb_info - This is the structure allocated and
792 * initialized per status block. Assumption is
793 * that it was initialized using qed_sb_init
794 * @param int_cmd - Enable/Disable/Nop
795 * @param upd_flg - whether igu consumer should be
796 * updated.
797 *
798 * @return inline void
799 */
800static inline void qed_sb_ack(struct qed_sb_info *sb_info,
801 enum igu_int_cmd int_cmd,
802 u8 upd_flg)
803{
804 struct igu_prod_cons_update igu_ack = { 0 };
805
806 igu_ack.sb_id_and_flags =
807 ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
808 (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
809 (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
810 (IGU_SEG_ACCESS_REG <<
811 IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
812
813 DIRECT_REG_WR(sb_info->igu_addr, igu_ack.sb_id_and_flags);
814
815 /* Both segments (interrupts & acks) are written to same place address;
816 * Need to guarantee all commands will be received (in-order) by HW.
817 */
818 mmiowb();
819 barrier();
820}
821
822static inline void __internal_ram_wr(void *p_hwfn,
823 void __iomem *addr,
824 int size,
825 u32 *data)
826
827{
828 unsigned int i;
829
830 for (i = 0; i < size / sizeof(*data); i++)
831 DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]);
832}
833
834static inline void internal_ram_wr(void __iomem *addr,
835 int size,
836 u32 *data)
837{
838 __internal_ram_wr(NULL, addr, size, data);
839}
840
8c5ebd0c
SRK		 841enum qed_rss_caps {
842 QED_RSS_IPV4 = 0x1,
843 QED_RSS_IPV6 = 0x2,
844 QED_RSS_IPV4_TCP = 0x4,
845 QED_RSS_IPV6_TCP = 0x8,
846 QED_RSS_IPV4_UDP = 0x10,
847 QED_RSS_IPV6_UDP = 0x20,
848};
849
850#define QED_RSS_IND_TABLE_SIZE 128
851#define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */
fe56b9e6 852#endif
Linux 6.x block layer and io_uring tree(s)