[linux-2.6-block.git] / include / linux / qed / qed_if.h

/* QLogic qed NIC Driver
 *
 * Copyright (c) 2015 QLogic Corporation
 *
 * This software is available under the terms of the GNU General Public License
 * (GPL) Version 2, available from the file COPYING in the main directory of
 * this source tree.
 */

#ifndef _QED_IF_H
#define _QED_IF_H

#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/netdevice.h>
#include <linux/pci.h>
#include <linux/skbuff.h>
#include <linux/types.h>
#include <asm/byteorder.h>
#include <linux/io.h>
#include <linux/compiler.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/slab.h>
#include <linux/qed/common_hsi.h>
#include <linux/qed/qed_chain.h>

enum qed_led_mode {
	QED_LED_MODE_OFF,
	QED_LED_MODE_ON,
	QED_LED_MODE_RESTORE
};

#define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \
					    (void __iomem *)(reg_addr))

#define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr))

#define QED_COALESCE_MAX 0xFF

/* forward */
struct qed_dev;

struct qed_eth_pf_params {
	/* The following parameters are used during HW-init
	 * and these parameters need to be passed as arguments
	 * to update_pf_params routine invoked before slowpath start
	 */
	u16 num_cons;
};

struct qed_pf_params {
	struct qed_eth_pf_params eth_pf_params;
};

enum qed_int_mode {
	QED_INT_MODE_INTA,
	QED_INT_MODE_MSIX,
	QED_INT_MODE_MSI,
	QED_INT_MODE_POLL,
};

struct qed_sb_info {
	struct status_block	*sb_virt;
	dma_addr_t		sb_phys;
	u32			sb_ack; /* Last given ack */
	u16			igu_sb_id;
	void __iomem		*igu_addr;
	u8			flags;
#define QED_SB_INFO_INIT        0x1
#define QED_SB_INFO_SETUP       0x2

	struct qed_dev		*cdev;
};

struct qed_dev_info {
	unsigned long	pci_mem_start;
	unsigned long	pci_mem_end;
	unsigned int	pci_irq;
	u8		num_hwfns;

	u8		hw_mac[ETH_ALEN];
	bool		is_mf_default;

	/* FW version */
	u16		fw_major;
	u16		fw_minor;
	u16		fw_rev;
	u16		fw_eng;

	/* MFW version */
	u32		mfw_rev;

	u32		flash_size;
	u8		mf_mode;
};

enum qed_sb_type {
	QED_SB_TYPE_L2_QUEUE,
};

enum qed_protocol {
	QED_PROTOCOL_ETH,
};

struct qed_link_params {
	bool	link_up;

#define QED_LINK_OVERRIDE_SPEED_AUTONEG         BIT(0)
#define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS      BIT(1)
#define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED    BIT(2)
#define QED_LINK_OVERRIDE_PAUSE_CONFIG          BIT(3)
#define QED_LINK_OVERRIDE_LOOPBACK_MODE         BIT(4)
	u32	override_flags;
	bool	autoneg;
	u32	adv_speeds;
	u32	forced_speed;
#define QED_LINK_PAUSE_AUTONEG_ENABLE           BIT(0)
#define QED_LINK_PAUSE_RX_ENABLE                BIT(1)
#define QED_LINK_PAUSE_TX_ENABLE                BIT(2)
	u32	pause_config;
#define QED_LINK_LOOPBACK_NONE                  BIT(0)
#define QED_LINK_LOOPBACK_INT_PHY               BIT(1)
#define QED_LINK_LOOPBACK_EXT_PHY               BIT(2)
#define QED_LINK_LOOPBACK_EXT                   BIT(3)
#define QED_LINK_LOOPBACK_MAC                   BIT(4)
	u32	loopback_mode;
};

struct qed_link_output {
	bool	link_up;

	u32	supported_caps;         /* In SUPPORTED defs */
	u32	advertised_caps;        /* In ADVERTISED defs */
	u32	lp_caps;                /* In ADVERTISED defs */
	u32	speed;                  /* In Mb/s */
	u8	duplex;                 /* In DUPLEX defs */
	u8	port;                   /* In PORT defs */
	bool	autoneg;
	u32	pause_config;
};

struct qed_probe_params {
	enum qed_protocol protocol;
	u32 dp_module;
	u8 dp_level;
	bool is_vf;
};

#define QED_DRV_VER_STR_SIZE 12
struct qed_slowpath_params {
	u32	int_mode;
	u8	drv_major;
	u8	drv_minor;
	u8	drv_rev;
	u8	drv_eng;
	u8	name[QED_DRV_VER_STR_SIZE];
};

#define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */

struct qed_int_info {
	struct msix_entry	*msix;
	u8			msix_cnt;

	/* This should be updated by the protocol driver */
	u8			used_cnt;
};

struct qed_common_cb_ops {
	void	(*link_update)(void			*dev,
			       struct qed_link_output	*link);
};

struct qed_selftest_ops {
/**
 * @brief selftest_interrupt - Perform interrupt test
 *
 * @param cdev
 *
 * @return 0 on success, error otherwise.
 */
	int (*selftest_interrupt)(struct qed_dev *cdev);

/**
 * @brief selftest_memory - Perform memory test
 *
 * @param cdev
 *
 * @return 0 on success, error otherwise.
 */
	int (*selftest_memory)(struct qed_dev *cdev);

/**
 * @brief selftest_register - Perform register test
 *
 * @param cdev
 *
 * @return 0 on success, error otherwise.
 */
	int (*selftest_register)(struct qed_dev *cdev);

/**
 * @brief selftest_clock - Perform clock test
 *
 * @param cdev
 *
 * @return 0 on success, error otherwise.
 */
	int (*selftest_clock)(struct qed_dev *cdev);
};

struct qed_common_ops {
	struct qed_selftest_ops *selftest;

	struct qed_dev*	(*probe)(struct pci_dev *dev,
				 struct qed_probe_params *params);

	void		(*remove)(struct qed_dev *cdev);

	int		(*set_power_state)(struct qed_dev *cdev,
					   pci_power_t state);

	void		(*set_id)(struct qed_dev *cdev,
				  char name[],
				  char ver_str[]);

	/* Client drivers need to make this call before slowpath_start.
	 * PF params required for the call before slowpath_start is
	 * documented within the qed_pf_params structure definition.
	 */
	void		(*update_pf_params)(struct qed_dev *cdev,
					    struct qed_pf_params *params);
	int		(*slowpath_start)(struct qed_dev *cdev,
					  struct qed_slowpath_params *params);

	int		(*slowpath_stop)(struct qed_dev *cdev);

	/* Requests to use `cnt' interrupts for fastpath.
	 * upon success, returns number of interrupts allocated for fastpath.
	 */
	int		(*set_fp_int)(struct qed_dev *cdev,
				      u16 cnt);

	/* Fills `info' with pointers required for utilizing interrupts */
	int		(*get_fp_int)(struct qed_dev *cdev,
				      struct qed_int_info *info);

	u32		(*sb_init)(struct qed_dev *cdev,
				   struct qed_sb_info *sb_info,
				   void *sb_virt_addr,
				   dma_addr_t sb_phy_addr,
				   u16 sb_id,
				   enum qed_sb_type type);

	u32		(*sb_release)(struct qed_dev *cdev,
				      struct qed_sb_info *sb_info,
				      u16 sb_id);

	void		(*simd_handler_config)(struct qed_dev *cdev,
					       void *token,
					       int index,
					       void (*handler)(void *));

	void		(*simd_handler_clean)(struct qed_dev *cdev,
					      int index);

/**
 * @brief can_link_change - can the instance change the link or not
 *
 * @param cdev
 *
 * @return true if link-change is allowed, false otherwise.
 */
	bool (*can_link_change)(struct qed_dev *cdev);

/**
 * @brief set_link - set links according to params
 *
 * @param cdev
 * @param params - values used to override the default link configuration
 *
 * @return 0 on success, error otherwise.
 */
	int		(*set_link)(struct qed_dev *cdev,
				    struct qed_link_params *params);

/**
 * @brief get_link - returns the current link state.
 *
 * @param cdev
 * @param if_link - structure to be filled with current link configuration.
 */
	void		(*get_link)(struct qed_dev *cdev,
				    struct qed_link_output *if_link);

/**
 * @brief - drains chip in case Tx completions fail to arrive due to pause.
 *
 * @param cdev
 */
	int		(*drain)(struct qed_dev *cdev);

/**
 * @brief update_msglvl - update module debug level
 *
 * @param cdev
 * @param dp_module
 * @param dp_level
 */
	void		(*update_msglvl)(struct qed_dev *cdev,
					 u32 dp_module,
					 u8 dp_level);

	int		(*chain_alloc)(struct qed_dev *cdev,
				       enum qed_chain_use_mode intended_use,
				       enum qed_chain_mode mode,
				       u16 num_elems,
				       size_t elem_size,
				       struct qed_chain *p_chain);

	void		(*chain_free)(struct qed_dev *cdev,
				      struct qed_chain *p_chain);

/**
 * @brief set_led - Configure LED mode
 *
 * @param cdev
 * @param mode - LED mode
 *
 * @return 0 on success, error otherwise.
 */
	int (*set_led)(struct qed_dev *cdev,
		       enum qed_led_mode mode);
};

#define MASK_FIELD(_name, _value) \
	((_value) &= (_name ## _MASK))

#define FIELD_VALUE(_name, _value) \
	((_value & _name ## _MASK) << _name ## _SHIFT)

#define SET_FIELD(value, name, flag)			       \
	do {						       \
		(value) &= ~(name ## _MASK << name ## _SHIFT); \
		(value) |= (((u64)flag) << (name ## _SHIFT));  \
	} while (0)

#define GET_FIELD(value, name) \
	(((value) >> (name ## _SHIFT)) & name ## _MASK)

/* Debug print definitions */
#define DP_ERR(cdev, fmt, ...)						     \
		pr_err("[%s:%d(%s)]" fmt,				     \
		       __func__, __LINE__,				     \
		       DP_NAME(cdev) ? DP_NAME(cdev) : "",		     \
		       ## __VA_ARGS__)					     \

#define DP_NOTICE(cdev, fmt, ...)				      \
	do {							      \
		if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \
			pr_notice("[%s:%d(%s)]" fmt,		      \
				  __func__, __LINE__,		      \
				  DP_NAME(cdev) ? DP_NAME(cdev) : "", \
				  ## __VA_ARGS__);		      \
								      \
		}						      \
	} while (0)

#define DP_INFO(cdev, fmt, ...)					      \
	do {							      \
		if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) {   \
			pr_notice("[%s:%d(%s)]" fmt,		      \
				  __func__, __LINE__,		      \
				  DP_NAME(cdev) ? DP_NAME(cdev) : "", \
				  ## __VA_ARGS__);		      \
		}						      \
	} while (0)

#define DP_VERBOSE(cdev, module, fmt, ...)				\
	do {								\
		if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) &&	\
			     ((cdev)->dp_module & module))) {		\
			pr_notice("[%s:%d(%s)]" fmt,			\
				  __func__, __LINE__,			\
				  DP_NAME(cdev) ? DP_NAME(cdev) : "",	\
				  ## __VA_ARGS__);			\
		}							\
	} while (0)

enum DP_LEVEL {
	QED_LEVEL_VERBOSE	= 0x0,
	QED_LEVEL_INFO		= 0x1,
	QED_LEVEL_NOTICE	= 0x2,
	QED_LEVEL_ERR		= 0x3,
};

#define QED_LOG_LEVEL_SHIFT     (30)
#define QED_LOG_VERBOSE_MASK    (0x3fffffff)
#define QED_LOG_INFO_MASK       (0x40000000)
#define QED_LOG_NOTICE_MASK     (0x80000000)

enum DP_MODULE {
	QED_MSG_SPQ	= 0x10000,
	QED_MSG_STATS	= 0x20000,
	QED_MSG_DCB	= 0x40000,
	QED_MSG_IOV	= 0x80000,
	QED_MSG_SP	= 0x100000,
	QED_MSG_STORAGE = 0x200000,
	QED_MSG_CXT	= 0x800000,
	QED_MSG_ILT	= 0x2000000,
	QED_MSG_ROCE	= 0x4000000,
	QED_MSG_DEBUG	= 0x8000000,
	/* to be added...up to 0x8000000 */
};

enum qed_mf_mode {
	QED_MF_DEFAULT,
	QED_MF_OVLAN,
	QED_MF_NPAR,
};

struct qed_eth_stats {
	u64	no_buff_discards;
	u64	packet_too_big_discard;
	u64	ttl0_discard;
	u64	rx_ucast_bytes;
	u64	rx_mcast_bytes;
	u64	rx_bcast_bytes;
	u64	rx_ucast_pkts;
	u64	rx_mcast_pkts;
	u64	rx_bcast_pkts;
	u64	mftag_filter_discards;
	u64	mac_filter_discards;
	u64	tx_ucast_bytes;
	u64	tx_mcast_bytes;
	u64	tx_bcast_bytes;
	u64	tx_ucast_pkts;
	u64	tx_mcast_pkts;
	u64	tx_bcast_pkts;
	u64	tx_err_drop_pkts;
	u64	tpa_coalesced_pkts;
	u64	tpa_coalesced_events;
	u64	tpa_aborts_num;
	u64	tpa_not_coalesced_pkts;
	u64	tpa_coalesced_bytes;

	/* port */
	u64	rx_64_byte_packets;
	u64	rx_65_to_127_byte_packets;
	u64	rx_128_to_255_byte_packets;
	u64	rx_256_to_511_byte_packets;
	u64	rx_512_to_1023_byte_packets;
	u64	rx_1024_to_1518_byte_packets;
	u64	rx_1519_to_1522_byte_packets;
	u64	rx_1519_to_2047_byte_packets;
	u64	rx_2048_to_4095_byte_packets;
	u64	rx_4096_to_9216_byte_packets;
	u64	rx_9217_to_16383_byte_packets;
	u64	rx_crc_errors;
	u64	rx_mac_crtl_frames;
	u64	rx_pause_frames;
	u64	rx_pfc_frames;
	u64	rx_align_errors;
	u64	rx_carrier_errors;
	u64	rx_oversize_packets;
	u64	rx_jabbers;
	u64	rx_undersize_packets;
	u64	rx_fragments;
	u64	tx_64_byte_packets;
	u64	tx_65_to_127_byte_packets;
	u64	tx_128_to_255_byte_packets;
	u64	tx_256_to_511_byte_packets;
	u64	tx_512_to_1023_byte_packets;
	u64	tx_1024_to_1518_byte_packets;
	u64	tx_1519_to_2047_byte_packets;
	u64	tx_2048_to_4095_byte_packets;
	u64	tx_4096_to_9216_byte_packets;
	u64	tx_9217_to_16383_byte_packets;
	u64	tx_pause_frames;
	u64	tx_pfc_frames;
	u64	tx_lpi_entry_count;
	u64	tx_total_collisions;
	u64	brb_truncates;
	u64	brb_discards;
	u64	rx_mac_bytes;
	u64	rx_mac_uc_packets;
	u64	rx_mac_mc_packets;
	u64	rx_mac_bc_packets;
	u64	rx_mac_frames_ok;
	u64	tx_mac_bytes;
	u64	tx_mac_uc_packets;
	u64	tx_mac_mc_packets;
	u64	tx_mac_bc_packets;
	u64	tx_mac_ctrl_frames;
};

#define QED_SB_IDX              0x0002

#define RX_PI           0
#define TX_PI(tc)       (RX_PI + 1 + tc)

struct qed_sb_cnt_info {
	int	sb_cnt;
	int	sb_iov_cnt;
	int	sb_free_blk;
};

static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info)
{
	u32 prod = 0;
	u16 rc = 0;

	prod = le32_to_cpu(sb_info->sb_virt->prod_index) &
	       STATUS_BLOCK_PROD_INDEX_MASK;
	if (sb_info->sb_ack != prod) {
		sb_info->sb_ack = prod;
		rc |= QED_SB_IDX;
	}

	/* Let SB update */
	mmiowb();
	return rc;
}

/**
 *
 * @brief This function creates an update command for interrupts that is
 *        written to the IGU.
 *
 * @param sb_info       - This is the structure allocated and
 *                 initialized per status block. Assumption is
 *                 that it was initialized using qed_sb_init
 * @param int_cmd       - Enable/Disable/Nop
 * @param upd_flg       - whether igu consumer should be
 *                 updated.
 *
 * @return inline void
 */
static inline void qed_sb_ack(struct qed_sb_info *sb_info,
			      enum igu_int_cmd int_cmd,
			      u8 upd_flg)
{
	struct igu_prod_cons_update igu_ack = { 0 };

	igu_ack.sb_id_and_flags =
		((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
		 (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
		 (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
		 (IGU_SEG_ACCESS_REG <<
		  IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));

	DIRECT_REG_WR(sb_info->igu_addr, igu_ack.sb_id_and_flags);

	/* Both segments (interrupts & acks) are written to same place address;
	 * Need to guarantee all commands will be received (in-order) by HW.
	 */
	mmiowb();
	barrier();
}

static inline void __internal_ram_wr(void *p_hwfn,
				     void __iomem *addr,
				     int size,
				     u32 *data)

{
	unsigned int i;

	for (i = 0; i < size / sizeof(*data); i++)
		DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]);
}

static inline void internal_ram_wr(void __iomem *addr,
				   int size,
				   u32 *data)
{
	__internal_ram_wr(NULL, addr, size, data);
}

enum qed_rss_caps {
	QED_RSS_IPV4		= 0x1,
	QED_RSS_IPV6		= 0x2,
	QED_RSS_IPV4_TCP	= 0x4,
	QED_RSS_IPV6_TCP	= 0x8,
	QED_RSS_IPV4_UDP	= 0x10,
	QED_RSS_IPV6_UDP	= 0x20,
};

#define QED_RSS_IND_TABLE_SIZE 128
#define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */
#endif
Commit	Line	Data
fe56b9e6 YM	1	/* QLogic qed NIC Driver
	2	*
	3	* Copyright (c) 2015 QLogic Corporation
	4	*
	5	* This software is available under the terms of the GNU General Public License
	6	* (GPL) Version 2, available from the file COPYING in the main directory of
	7	* this source tree.
	8	*/
	9
	10	#ifndef _QED_IF_H
	11	#define _QED_IF_H
	12
	13	#include <linux/types.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/netdevice.h>
	16	#include <linux/pci.h>
	17	#include <linux/skbuff.h>
	18	#include <linux/types.h>
	19	#include <asm/byteorder.h>
	20	#include <linux/io.h>
	21	#include <linux/compiler.h>
	22	#include <linux/kernel.h>
	23	#include <linux/list.h>
	24	#include <linux/slab.h>
	25	#include <linux/qed/common_hsi.h>
	26	#include <linux/qed/qed_chain.h>
	27
91420b83 SK	28	enum qed_led_mode {
	29	QED_LED_MODE_OFF,
	30	QED_LED_MODE_ON,
	31	QED_LED_MODE_RESTORE
	32	};
	33
fe56b9e6 YM	34	#define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \
	35	(void __iomem *)(reg_addr))
	36
	37	#define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr))
	38
	39	#define QED_COALESCE_MAX 0xFF
	40
	41	/* forward */
	42	struct qed_dev;
	43
	44	struct qed_eth_pf_params {
	45	/* The following parameters are used during HW-init
	46	* and these parameters need to be passed as arguments
	47	* to update_pf_params routine invoked before slowpath start
	48	*/
	49	u16 num_cons;
	50	};
	51
	52	struct qed_pf_params {
	53	struct qed_eth_pf_params eth_pf_params;
	54	};
	55
	56	enum qed_int_mode {
	57	QED_INT_MODE_INTA,
	58	QED_INT_MODE_MSIX,
	59	QED_INT_MODE_MSI,
	60	QED_INT_MODE_POLL,
	61	};
	62
	63	struct qed_sb_info {
	64	struct status_block *sb_virt;
	65	dma_addr_t sb_phys;
	66	u32 sb_ack; /* Last given ack */
	67	u16 igu_sb_id;
	68	void __iomem *igu_addr;
	69	u8 flags;
	70	#define QED_SB_INFO_INIT 0x1
	71	#define QED_SB_INFO_SETUP 0x2
	72
	73	struct qed_dev *cdev;
	74	};
	75
	76	struct qed_dev_info {
	77	unsigned long pci_mem_start;
	78	unsigned long pci_mem_end;
	79	unsigned int pci_irq;
	80	u8 num_hwfns;
	81
	82	u8 hw_mac[ETH_ALEN];
fc48b7a6	83	bool is_mf_default;
fe56b9e6 YM	84
	85	/* FW version */
	86	u16 fw_major;
	87	u16 fw_minor;
	88	u16 fw_rev;
	89	u16 fw_eng;
	90
	91	/* MFW version */
	92	u32 mfw_rev;
	93
	94	u32 flash_size;
	95	u8 mf_mode;
	96	};
	97
	98	enum qed_sb_type {
	99	QED_SB_TYPE_L2_QUEUE,
	100	};
	101
	102	enum qed_protocol {
	103	QED_PROTOCOL_ETH,
	104	};
	105
	106	struct qed_link_params {
	107	bool link_up;
	108
	109	#define QED_LINK_OVERRIDE_SPEED_AUTONEG BIT(0)
	110	#define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS BIT(1)
	111	#define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED BIT(2)
	112	#define QED_LINK_OVERRIDE_PAUSE_CONFIG BIT(3)
03dc76ca	113	#define QED_LINK_OVERRIDE_LOOPBACK_MODE BIT(4)
fe56b9e6 YM	114	u32 override_flags;
	115	bool autoneg;
	116	u32 adv_speeds;
	117	u32 forced_speed;
	118	#define QED_LINK_PAUSE_AUTONEG_ENABLE BIT(0)
	119	#define QED_LINK_PAUSE_RX_ENABLE BIT(1)
	120	#define QED_LINK_PAUSE_TX_ENABLE BIT(2)
	121	u32 pause_config;
03dc76ca SRK	122	#define QED_LINK_LOOPBACK_NONE BIT(0)
	123	#define QED_LINK_LOOPBACK_INT_PHY BIT(1)
	124	#define QED_LINK_LOOPBACK_EXT_PHY BIT(2)
	125	#define QED_LINK_LOOPBACK_EXT BIT(3)
	126	#define QED_LINK_LOOPBACK_MAC BIT(4)
	127	u32 loopback_mode;
fe56b9e6 YM	128	};
	129
	130	struct qed_link_output {
	131	bool link_up;
	132
	133	u32 supported_caps; /* In SUPPORTED defs */
	134	u32 advertised_caps; /* In ADVERTISED defs */
	135	u32 lp_caps; /* In ADVERTISED defs */
	136	u32 speed; /* In Mb/s */
	137	u8 duplex; /* In DUPLEX defs */
	138	u8 port; /* In PORT defs */
	139	bool autoneg;
	140	u32 pause_config;
	141	};
	142
1408cc1f YM	143	struct qed_probe_params {
	144	enum qed_protocol protocol;
	145	u32 dp_module;
	146	u8 dp_level;
	147	bool is_vf;
	148	};
	149
fe56b9e6 YM	150	#define QED_DRV_VER_STR_SIZE 12
	151	struct qed_slowpath_params {
	152	u32 int_mode;
	153	u8 drv_major;
	154	u8 drv_minor;
	155	u8 drv_rev;
	156	u8 drv_eng;
	157	u8 name[QED_DRV_VER_STR_SIZE];
	158	};
	159
	160	#define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */
	161
	162	struct qed_int_info {
	163	struct msix_entry *msix;
	164	u8 msix_cnt;
	165
	166	/* This should be updated by the protocol driver */
	167	u8 used_cnt;
	168	};
	169
	170	struct qed_common_cb_ops {
	171	void (link_update)(void dev,
	172	struct qed_link_output *link);
	173	};
	174
03dc76ca SRK	175	struct qed_selftest_ops {
	176	/**
	177	* @brief selftest_interrupt - Perform interrupt test
	178	*
	179	* @param cdev
	180	*
	181	* @return 0 on success, error otherwise.
	182	*/
	183	int (selftest_interrupt)(struct qed_dev cdev);
	184
	185	/**
	186	* @brief selftest_memory - Perform memory test
	187	*
	188	* @param cdev
	189	*
	190	* @return 0 on success, error otherwise.
	191	*/
	192	int (selftest_memory)(struct qed_dev cdev);
	193
	194	/**
	195	* @brief selftest_register - Perform register test
	196	*
	197	* @param cdev
	198	*
	199	* @return 0 on success, error otherwise.
	200	*/
	201	int (selftest_register)(struct qed_dev cdev);
	202
	203	/**
	204	* @brief selftest_clock - Perform clock test
	205	*
	206	* @param cdev
	207	*
	208	* @return 0 on success, error otherwise.
	209	*/
	210	int (selftest_clock)(struct qed_dev cdev);
	211	};
	212
fe56b9e6	213	struct qed_common_ops {
03dc76ca SRK	214	struct qed_selftest_ops *selftest;
03dc76ca SRK	215
fe56b9e6	216	struct qed_dev* (probe)(struct pci_dev dev,
1408cc1f	217	struct qed_probe_params *params);
fe56b9e6 YM	218
	219	void (remove)(struct qed_dev cdev);
	220
	221	int (set_power_state)(struct qed_dev cdev,
	222	pci_power_t state);
	223
	224	void (set_id)(struct qed_dev cdev,
	225	char name[],
	226	char ver_str[]);
	227
	228	/* Client drivers need to make this call before slowpath_start.
	229	* PF params required for the call before slowpath_start is
	230	* documented within the qed_pf_params structure definition.
	231	*/
	232	void (update_pf_params)(struct qed_dev cdev,
	233	struct qed_pf_params *params);
	234	int (slowpath_start)(struct qed_dev cdev,
	235	struct qed_slowpath_params *params);
	236
	237	int (slowpath_stop)(struct qed_dev cdev);
	238
	239	/* Requests to use `cnt' interrupts for fastpath.
	240	* upon success, returns number of interrupts allocated for fastpath.
	241	*/
	242	int (set_fp_int)(struct qed_dev cdev,
	243	u16 cnt);
	244
	245	/* Fills `info' with pointers required for utilizing interrupts */
	246	int (get_fp_int)(struct qed_dev cdev,
	247	struct qed_int_info *info);
	248
	249	u32 (sb_init)(struct qed_dev cdev,
	250	struct qed_sb_info *sb_info,
	251	void *sb_virt_addr,
	252	dma_addr_t sb_phy_addr,
	253	u16 sb_id,
	254	enum qed_sb_type type);
	255
	256	u32 (sb_release)(struct qed_dev cdev,
	257	struct qed_sb_info *sb_info,
	258	u16 sb_id);
	259
	260	void (simd_handler_config)(struct qed_dev cdev,
	261	void *token,
	262	int index,
	263	void (handler)(void ));
	264
	265	void (simd_handler_clean)(struct qed_dev cdev,
	266	int index);
fe7cd2bf YM	267
	268	/**
	269	* @brief can_link_change - can the instance change the link or not
	270	*
	271	* @param cdev
	272	*
	273	* @return true if link-change is allowed, false otherwise.
	274	*/
	275	bool (can_link_change)(struct qed_dev cdev);
	276
fe56b9e6 YM	277	/**
	278	* @brief set_link - set links according to params
	279	*
	280	* @param cdev
	281	* @param params - values used to override the default link configuration
	282	*
	283	* @return 0 on success, error otherwise.
	284	*/
	285	int (set_link)(struct qed_dev cdev,
	286	struct qed_link_params *params);
	287
	288	/**
	289	* @brief get_link - returns the current link state.
	290	*
	291	* @param cdev
	292	* @param if_link - structure to be filled with current link configuration.
	293	*/
	294	void (get_link)(struct qed_dev cdev,
	295	struct qed_link_output *if_link);
	296
	297	/**
	298	* @brief - drains chip in case Tx completions fail to arrive due to pause.
	299	*
	300	* @param cdev
	301	*/
	302	int (drain)(struct qed_dev cdev);
	303
	304	/**
	305	* @brief update_msglvl - update module debug level
	306	*
	307	* @param cdev
	308	* @param dp_module
	309	* @param dp_level
	310	*/
	311	void (update_msglvl)(struct qed_dev cdev,
	312	u32 dp_module,
	313	u8 dp_level);
	314
	315	int (chain_alloc)(struct qed_dev cdev,
	316	enum qed_chain_use_mode intended_use,
	317	enum qed_chain_mode mode,
	318	u16 num_elems,
	319	size_t elem_size,
	320	struct qed_chain *p_chain);
	321
	322	void (chain_free)(struct qed_dev cdev,
	323	struct qed_chain *p_chain);
91420b83 SK	324
	325	/**
	326	* @brief set_led - Configure LED mode
	327	*
	328	* @param cdev
	329	* @param mode - LED mode
	330	*
	331	* @return 0 on success, error otherwise.
	332	*/
	333	int (set_led)(struct qed_dev cdev,
	334	enum qed_led_mode mode);
fe56b9e6 YM	335	};
fe56b9e6 YM	336
fe56b9e6 YM	337	#define MASK_FIELD(_name, _value) \
	338	((_value) &= (_name ## _MASK))
	339
	340	#define FIELD_VALUE(_name, _value) \
	341	((_value & _name ## _MASK) << _name ## _SHIFT)
	342
	343	#define SET_FIELD(value, name, flag) \
	344	do { \
	345	(value) &= ~(name ## _MASK << name ## _SHIFT); \
	346	(value) \|= (((u64)flag) << (name ## _SHIFT)); \
	347	} while (0)
	348
	349	#define GET_FIELD(value, name) \
	350	(((value) >> (name ## _SHIFT)) & name ## _MASK)
	351
	352	/* Debug print definitions */
	353	#define DP_ERR(cdev, fmt, ...) \
	354	pr_err("[%s:%d(%s)]" fmt, \
	355	__func__, __LINE__, \
	356	DP_NAME(cdev) ? DP_NAME(cdev) : "", \
	357	## __VA_ARGS__) \
	358
	359	#define DP_NOTICE(cdev, fmt, ...) \
	360	do { \
	361	if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \
	362	pr_notice("[%s:%d(%s)]" fmt, \
	363	__func__, __LINE__, \
	364	DP_NAME(cdev) ? DP_NAME(cdev) : "", \
	365	## __VA_ARGS__); \
	366	\
	367	} \
	368	} while (0)
	369
	370	#define DP_INFO(cdev, fmt, ...) \
	371	do { \
	372	if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) { \
	373	pr_notice("[%s:%d(%s)]" fmt, \
	374	__func__, __LINE__, \
	375	DP_NAME(cdev) ? DP_NAME(cdev) : "", \
	376	## __VA_ARGS__); \
	377	} \
	378	} while (0)
	379
	380	#define DP_VERBOSE(cdev, module, fmt, ...) \
	381	do { \
	382	if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) && \
	383	((cdev)->dp_module & module))) { \
	384	pr_notice("[%s:%d(%s)]" fmt, \
	385	__func__, __LINE__, \
	386	DP_NAME(cdev) ? DP_NAME(cdev) : "", \
	387	## __VA_ARGS__); \
	388	} \
	389	} while (0)
	390
	391	enum DP_LEVEL {
	392	QED_LEVEL_VERBOSE = 0x0,
	393	QED_LEVEL_INFO = 0x1,
	394	QED_LEVEL_NOTICE = 0x2,
	395	QED_LEVEL_ERR = 0x3,
	396	};
	397
	398	#define QED_LOG_LEVEL_SHIFT (30)
	399	#define QED_LOG_VERBOSE_MASK (0x3fffffff)
	400	#define QED_LOG_INFO_MASK (0x40000000)
401	#define QED_LOG_NOTICE_MASK (0x80000000)
402
403	enum DP_MODULE {
404	QED_MSG_SPQ = 0x10000,
405	QED_MSG_STATS = 0x20000,
406	QED_MSG_DCB = 0x40000,
407	QED_MSG_IOV = 0x80000,
408	QED_MSG_SP = 0x100000,
409	QED_MSG_STORAGE = 0x200000,
410	QED_MSG_CXT = 0x800000,
411	QED_MSG_ILT = 0x2000000,
412	QED_MSG_ROCE = 0x4000000,
413	QED_MSG_DEBUG = 0x8000000,
414	/* to be added...up to 0x8000000 */
415	};
416
fc48b7a6 YM	417	enum qed_mf_mode {
	418	QED_MF_DEFAULT,
	419	QED_MF_OVLAN,
	420	QED_MF_NPAR,
	421	};
	422
fe56b9e6 YM	423	struct qed_eth_stats {
	424	u64 no_buff_discards;
	425	u64 packet_too_big_discard;
	426	u64 ttl0_discard;
	427	u64 rx_ucast_bytes;
	428	u64 rx_mcast_bytes;
	429	u64 rx_bcast_bytes;
	430	u64 rx_ucast_pkts;
	431	u64 rx_mcast_pkts;
	432	u64 rx_bcast_pkts;
	433	u64 mftag_filter_discards;
	434	u64 mac_filter_discards;
	435	u64 tx_ucast_bytes;
	436	u64 tx_mcast_bytes;
	437	u64 tx_bcast_bytes;
	438	u64 tx_ucast_pkts;
	439	u64 tx_mcast_pkts;
	440	u64 tx_bcast_pkts;
	441	u64 tx_err_drop_pkts;
	442	u64 tpa_coalesced_pkts;
	443	u64 tpa_coalesced_events;
	444	u64 tpa_aborts_num;
	445	u64 tpa_not_coalesced_pkts;
	446	u64 tpa_coalesced_bytes;
	447
	448	/* port */
	449	u64 rx_64_byte_packets;
d4967cf3 YM	450	u64 rx_65_to_127_byte_packets;
	451	u64 rx_128_to_255_byte_packets;
	452	u64 rx_256_to_511_byte_packets;
	453	u64 rx_512_to_1023_byte_packets;
	454	u64 rx_1024_to_1518_byte_packets;
	455	u64 rx_1519_to_1522_byte_packets;
	456	u64 rx_1519_to_2047_byte_packets;
	457	u64 rx_2048_to_4095_byte_packets;
	458	u64 rx_4096_to_9216_byte_packets;
	459	u64 rx_9217_to_16383_byte_packets;
fe56b9e6 YM	460	u64 rx_crc_errors;
	461	u64 rx_mac_crtl_frames;
	462	u64 rx_pause_frames;
	463	u64 rx_pfc_frames;
	464	u64 rx_align_errors;
	465	u64 rx_carrier_errors;
	466	u64 rx_oversize_packets;
	467	u64 rx_jabbers;
	468	u64 rx_undersize_packets;
	469	u64 rx_fragments;
	470	u64 tx_64_byte_packets;
	471	u64 tx_65_to_127_byte_packets;
	472	u64 tx_128_to_255_byte_packets;
	473	u64 tx_256_to_511_byte_packets;
	474	u64 tx_512_to_1023_byte_packets;
	475	u64 tx_1024_to_1518_byte_packets;
	476	u64 tx_1519_to_2047_byte_packets;
	477	u64 tx_2048_to_4095_byte_packets;
	478	u64 tx_4096_to_9216_byte_packets;
	479	u64 tx_9217_to_16383_byte_packets;
	480	u64 tx_pause_frames;
	481	u64 tx_pfc_frames;
	482	u64 tx_lpi_entry_count;
	483	u64 tx_total_collisions;
	484	u64 brb_truncates;
	485	u64 brb_discards;
	486	u64 rx_mac_bytes;
	487	u64 rx_mac_uc_packets;
	488	u64 rx_mac_mc_packets;
	489	u64 rx_mac_bc_packets;
	490	u64 rx_mac_frames_ok;
	491	u64 tx_mac_bytes;
	492	u64 tx_mac_uc_packets;
	493	u64 tx_mac_mc_packets;
	494	u64 tx_mac_bc_packets;
	495	u64 tx_mac_ctrl_frames;
	496	};
	497
	498	#define QED_SB_IDX 0x0002
	499
	500	#define RX_PI 0
	501	#define TX_PI(tc) (RX_PI + 1 + tc)
	502
4ac801b7 YM	503	struct qed_sb_cnt_info {
	504	int sb_cnt;
	505	int sb_iov_cnt;
	506	int sb_free_blk;
	507	};
	508
fe56b9e6 YM	509	static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info)
	510	{
	511	u32 prod = 0;
	512	u16 rc = 0;
	513
	514	prod = le32_to_cpu(sb_info->sb_virt->prod_index) &
	515	STATUS_BLOCK_PROD_INDEX_MASK;
	516	if (sb_info->sb_ack != prod) {
	517	sb_info->sb_ack = prod;
	518	rc \|= QED_SB_IDX;
	519	}
	520
	521	/* Let SB update */
	522	mmiowb();
	523	return rc;
	524	}
	525
	526	/**
	527	*
	528	* @brief This function creates an update command for interrupts that is
	529	* written to the IGU.
	530	*
	531	* @param sb_info - This is the structure allocated and
	532	* initialized per status block. Assumption is
	533	* that it was initialized using qed_sb_init
	534	* @param int_cmd - Enable/Disable/Nop
	535	* @param upd_flg - whether igu consumer should be
	536	* updated.
	537	*
	538	* @return inline void
	539	*/
	540	static inline void qed_sb_ack(struct qed_sb_info *sb_info,
	541	enum igu_int_cmd int_cmd,
	542	u8 upd_flg)
	543	{
	544	struct igu_prod_cons_update igu_ack = { 0 };
	545
	546	igu_ack.sb_id_and_flags =
	547	((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) \|
	548	(upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) \|
	549	(int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) \|
	550	(IGU_SEG_ACCESS_REG <<
	551	IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
	552
	553	DIRECT_REG_WR(sb_info->igu_addr, igu_ack.sb_id_and_flags);
	554
	555	/* Both segments (interrupts & acks) are written to same place address;
	556	* Need to guarantee all commands will be received (in-order) by HW.
	557	*/
	558	mmiowb();
	559	barrier();
	560	}
	561
	562	static inline void __internal_ram_wr(void *p_hwfn,
	563	void __iomem *addr,
	564	int size,
	565	u32 *data)
	566
	567	{
	568	unsigned int i;
	569
	570	for (i = 0; i < size / sizeof(*data); i++)
	571	DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]);
	572	}
573
574	static inline void internal_ram_wr(void __iomem *addr,
575	int size,
576	u32 *data)
577	{
578	__internal_ram_wr(NULL, addr, size, data);
579	}
580
8c5ebd0c SRK	581	enum qed_rss_caps {
	582	QED_RSS_IPV4 = 0x1,
	583	QED_RSS_IPV6 = 0x2,
	584	QED_RSS_IPV4_TCP = 0x4,
	585	QED_RSS_IPV6_TCP = 0x8,
	586	QED_RSS_IPV4_UDP = 0x10,
	587	QED_RSS_IPV6_UDP = 0x20,
	588	};
	589
	590	#define QED_RSS_IND_TABLE_SIZE 128
	591	#define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */
fe56b9e6	592	#endif