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fe56b9e6 | 1 | /* QLogic qed NIC Driver |
e8f1cb50 | 2 | * Copyright (c) 2015-2017 QLogic Corporation |
fe56b9e6 | 3 | * |
e8f1cb50 MY |
4 | * This software is available to you under a choice of one of two |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
fe56b9e6 | 9 | * |
e8f1cb50 MY |
10 | * Redistribution and use in source and binary forms, with or |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and /or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
fe56b9e6 YM |
31 | */ |
32 | ||
33 | #ifndef _QED_IF_H | |
34 | #define _QED_IF_H | |
35 | ||
36 | #include <linux/types.h> | |
37 | #include <linux/interrupt.h> | |
38 | #include <linux/netdevice.h> | |
39 | #include <linux/pci.h> | |
40 | #include <linux/skbuff.h> | |
41 | #include <linux/types.h> | |
42 | #include <asm/byteorder.h> | |
43 | #include <linux/io.h> | |
44 | #include <linux/compiler.h> | |
45 | #include <linux/kernel.h> | |
46 | #include <linux/list.h> | |
47 | #include <linux/slab.h> | |
48 | #include <linux/qed/common_hsi.h> | |
49 | #include <linux/qed/qed_chain.h> | |
50 | ||
39651abd SRK |
51 | enum dcbx_protocol_type { |
52 | DCBX_PROTOCOL_ISCSI, | |
53 | DCBX_PROTOCOL_FCOE, | |
54 | DCBX_PROTOCOL_ROCE, | |
55 | DCBX_PROTOCOL_ROCE_V2, | |
56 | DCBX_PROTOCOL_ETH, | |
57 | DCBX_MAX_PROTOCOL_TYPE | |
58 | }; | |
59 | ||
51ff1725 RA |
60 | #define QED_ROCE_PROTOCOL_INDEX (3) |
61 | ||
6ad8c632 SRK |
62 | #define QED_LLDP_CHASSIS_ID_STAT_LEN 4 |
63 | #define QED_LLDP_PORT_ID_STAT_LEN 4 | |
64 | #define QED_DCBX_MAX_APP_PROTOCOL 32 | |
65 | #define QED_MAX_PFC_PRIORITIES 8 | |
66 | #define QED_DCBX_DSCP_SIZE 64 | |
67 | ||
68 | struct qed_dcbx_lldp_remote { | |
69 | u32 peer_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN]; | |
70 | u32 peer_port_id[QED_LLDP_PORT_ID_STAT_LEN]; | |
71 | bool enable_rx; | |
72 | bool enable_tx; | |
73 | u32 tx_interval; | |
74 | u32 max_credit; | |
75 | }; | |
76 | ||
77 | struct qed_dcbx_lldp_local { | |
78 | u32 local_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN]; | |
79 | u32 local_port_id[QED_LLDP_PORT_ID_STAT_LEN]; | |
80 | }; | |
81 | ||
82 | struct qed_dcbx_app_prio { | |
83 | u8 roce; | |
84 | u8 roce_v2; | |
85 | u8 fcoe; | |
86 | u8 iscsi; | |
87 | u8 eth; | |
88 | }; | |
89 | ||
90 | struct qed_dbcx_pfc_params { | |
91 | bool willing; | |
92 | bool enabled; | |
93 | u8 prio[QED_MAX_PFC_PRIORITIES]; | |
94 | u8 max_tc; | |
95 | }; | |
96 | ||
59bcb797 SRK |
97 | enum qed_dcbx_sf_ieee_type { |
98 | QED_DCBX_SF_IEEE_ETHTYPE, | |
99 | QED_DCBX_SF_IEEE_TCP_PORT, | |
100 | QED_DCBX_SF_IEEE_UDP_PORT, | |
101 | QED_DCBX_SF_IEEE_TCP_UDP_PORT | |
102 | }; | |
103 | ||
6ad8c632 SRK |
104 | struct qed_app_entry { |
105 | bool ethtype; | |
59bcb797 | 106 | enum qed_dcbx_sf_ieee_type sf_ieee; |
6ad8c632 SRK |
107 | bool enabled; |
108 | u8 prio; | |
109 | u16 proto_id; | |
110 | enum dcbx_protocol_type proto_type; | |
111 | }; | |
112 | ||
113 | struct qed_dcbx_params { | |
114 | struct qed_app_entry app_entry[QED_DCBX_MAX_APP_PROTOCOL]; | |
115 | u16 num_app_entries; | |
116 | bool app_willing; | |
117 | bool app_valid; | |
118 | bool app_error; | |
119 | bool ets_willing; | |
120 | bool ets_enabled; | |
121 | bool ets_cbs; | |
122 | bool valid; | |
123 | u8 ets_pri_tc_tbl[QED_MAX_PFC_PRIORITIES]; | |
124 | u8 ets_tc_bw_tbl[QED_MAX_PFC_PRIORITIES]; | |
125 | u8 ets_tc_tsa_tbl[QED_MAX_PFC_PRIORITIES]; | |
126 | struct qed_dbcx_pfc_params pfc; | |
127 | u8 max_ets_tc; | |
128 | }; | |
129 | ||
130 | struct qed_dcbx_admin_params { | |
131 | struct qed_dcbx_params params; | |
132 | bool valid; | |
133 | }; | |
134 | ||
135 | struct qed_dcbx_remote_params { | |
136 | struct qed_dcbx_params params; | |
137 | bool valid; | |
138 | }; | |
139 | ||
140 | struct qed_dcbx_operational_params { | |
141 | struct qed_dcbx_app_prio app_prio; | |
142 | struct qed_dcbx_params params; | |
143 | bool valid; | |
144 | bool enabled; | |
145 | bool ieee; | |
146 | bool cee; | |
49632b58 | 147 | bool local; |
6ad8c632 SRK |
148 | u32 err; |
149 | }; | |
150 | ||
151 | struct qed_dcbx_get { | |
152 | struct qed_dcbx_operational_params operational; | |
153 | struct qed_dcbx_lldp_remote lldp_remote; | |
154 | struct qed_dcbx_lldp_local lldp_local; | |
155 | struct qed_dcbx_remote_params remote; | |
156 | struct qed_dcbx_admin_params local; | |
157 | }; | |
6ad8c632 | 158 | |
20675b37 MY |
159 | enum qed_nvm_images { |
160 | QED_NVM_IMAGE_ISCSI_CFG, | |
161 | QED_NVM_IMAGE_FCOE_CFG, | |
1ac4329a DB |
162 | QED_NVM_IMAGE_NVM_CFG1, |
163 | QED_NVM_IMAGE_DEFAULT_CFG, | |
164 | QED_NVM_IMAGE_NVM_META, | |
20675b37 MY |
165 | }; |
166 | ||
645874e5 SRK |
167 | struct qed_link_eee_params { |
168 | u32 tx_lpi_timer; | |
169 | #define QED_EEE_1G_ADV BIT(0) | |
170 | #define QED_EEE_10G_ADV BIT(1) | |
171 | ||
172 | /* Capabilities are represented using QED_EEE_*_ADV values */ | |
173 | u8 adv_caps; | |
174 | u8 lp_adv_caps; | |
175 | bool enable; | |
176 | bool tx_lpi_enable; | |
177 | }; | |
178 | ||
91420b83 SK |
179 | enum qed_led_mode { |
180 | QED_LED_MODE_OFF, | |
181 | QED_LED_MODE_ON, | |
182 | QED_LED_MODE_RESTORE | |
183 | }; | |
184 | ||
2528c389 SRK |
185 | struct qed_mfw_tlv_eth { |
186 | u16 lso_maxoff_size; | |
187 | bool lso_maxoff_size_set; | |
188 | u16 lso_minseg_size; | |
189 | bool lso_minseg_size_set; | |
190 | u8 prom_mode; | |
191 | bool prom_mode_set; | |
192 | u16 tx_descr_size; | |
193 | bool tx_descr_size_set; | |
194 | u16 rx_descr_size; | |
195 | bool rx_descr_size_set; | |
196 | u16 netq_count; | |
197 | bool netq_count_set; | |
198 | u32 tcp4_offloads; | |
199 | bool tcp4_offloads_set; | |
200 | u32 tcp6_offloads; | |
201 | bool tcp6_offloads_set; | |
202 | u16 tx_descr_qdepth; | |
203 | bool tx_descr_qdepth_set; | |
204 | u16 rx_descr_qdepth; | |
205 | bool rx_descr_qdepth_set; | |
206 | u8 iov_offload; | |
207 | #define QED_MFW_TLV_IOV_OFFLOAD_NONE (0) | |
208 | #define QED_MFW_TLV_IOV_OFFLOAD_MULTIQUEUE (1) | |
209 | #define QED_MFW_TLV_IOV_OFFLOAD_VEB (2) | |
210 | #define QED_MFW_TLV_IOV_OFFLOAD_VEPA (3) | |
211 | bool iov_offload_set; | |
212 | u8 txqs_empty; | |
213 | bool txqs_empty_set; | |
214 | u8 rxqs_empty; | |
215 | bool rxqs_empty_set; | |
216 | u8 num_txqs_full; | |
217 | bool num_txqs_full_set; | |
218 | u8 num_rxqs_full; | |
219 | bool num_rxqs_full_set; | |
220 | }; | |
221 | ||
f240b688 SRK |
222 | #define QED_MFW_TLV_TIME_SIZE 14 |
223 | struct qed_mfw_tlv_time { | |
224 | bool b_set; | |
225 | u8 month; | |
226 | u8 day; | |
227 | u8 hour; | |
228 | u8 min; | |
229 | u16 msec; | |
230 | u16 usec; | |
231 | }; | |
232 | ||
233 | struct qed_mfw_tlv_fcoe { | |
234 | u8 scsi_timeout; | |
235 | bool scsi_timeout_set; | |
236 | u32 rt_tov; | |
237 | bool rt_tov_set; | |
238 | u32 ra_tov; | |
239 | bool ra_tov_set; | |
240 | u32 ed_tov; | |
241 | bool ed_tov_set; | |
242 | u32 cr_tov; | |
243 | bool cr_tov_set; | |
244 | u8 boot_type; | |
245 | bool boot_type_set; | |
246 | u8 npiv_state; | |
247 | bool npiv_state_set; | |
248 | u32 num_npiv_ids; | |
249 | bool num_npiv_ids_set; | |
250 | u8 switch_name[8]; | |
251 | bool switch_name_set; | |
252 | u16 switch_portnum; | |
253 | bool switch_portnum_set; | |
254 | u8 switch_portid[3]; | |
255 | bool switch_portid_set; | |
256 | u8 vendor_name[8]; | |
257 | bool vendor_name_set; | |
258 | u8 switch_model[8]; | |
259 | bool switch_model_set; | |
260 | u8 switch_fw_version[8]; | |
261 | bool switch_fw_version_set; | |
262 | u8 qos_pri; | |
263 | bool qos_pri_set; | |
264 | u8 port_alias[3]; | |
265 | bool port_alias_set; | |
266 | u8 port_state; | |
267 | #define QED_MFW_TLV_PORT_STATE_OFFLINE (0) | |
268 | #define QED_MFW_TLV_PORT_STATE_LOOP (1) | |
269 | #define QED_MFW_TLV_PORT_STATE_P2P (2) | |
270 | #define QED_MFW_TLV_PORT_STATE_FABRIC (3) | |
271 | bool port_state_set; | |
272 | u16 fip_tx_descr_size; | |
273 | bool fip_tx_descr_size_set; | |
274 | u16 fip_rx_descr_size; | |
275 | bool fip_rx_descr_size_set; | |
276 | u16 link_failures; | |
277 | bool link_failures_set; | |
278 | u8 fcoe_boot_progress; | |
279 | bool fcoe_boot_progress_set; | |
280 | u64 rx_bcast; | |
281 | bool rx_bcast_set; | |
282 | u64 tx_bcast; | |
283 | bool tx_bcast_set; | |
284 | u16 fcoe_txq_depth; | |
285 | bool fcoe_txq_depth_set; | |
286 | u16 fcoe_rxq_depth; | |
287 | bool fcoe_rxq_depth_set; | |
288 | u64 fcoe_rx_frames; | |
289 | bool fcoe_rx_frames_set; | |
290 | u64 fcoe_rx_bytes; | |
291 | bool fcoe_rx_bytes_set; | |
292 | u64 fcoe_tx_frames; | |
293 | bool fcoe_tx_frames_set; | |
294 | u64 fcoe_tx_bytes; | |
295 | bool fcoe_tx_bytes_set; | |
296 | u16 crc_count; | |
297 | bool crc_count_set; | |
298 | u32 crc_err_src_fcid[5]; | |
299 | bool crc_err_src_fcid_set[5]; | |
300 | struct qed_mfw_tlv_time crc_err[5]; | |
301 | u16 losync_err; | |
302 | bool losync_err_set; | |
303 | u16 losig_err; | |
304 | bool losig_err_set; | |
305 | u16 primtive_err; | |
306 | bool primtive_err_set; | |
307 | u16 disparity_err; | |
308 | bool disparity_err_set; | |
309 | u16 code_violation_err; | |
310 | bool code_violation_err_set; | |
311 | u32 flogi_param[4]; | |
312 | bool flogi_param_set[4]; | |
313 | struct qed_mfw_tlv_time flogi_tstamp; | |
314 | u32 flogi_acc_param[4]; | |
315 | bool flogi_acc_param_set[4]; | |
316 | struct qed_mfw_tlv_time flogi_acc_tstamp; | |
317 | u32 flogi_rjt; | |
318 | bool flogi_rjt_set; | |
319 | struct qed_mfw_tlv_time flogi_rjt_tstamp; | |
320 | u32 fdiscs; | |
321 | bool fdiscs_set; | |
322 | u8 fdisc_acc; | |
323 | bool fdisc_acc_set; | |
324 | u8 fdisc_rjt; | |
325 | bool fdisc_rjt_set; | |
326 | u8 plogi; | |
327 | bool plogi_set; | |
328 | u8 plogi_acc; | |
329 | bool plogi_acc_set; | |
330 | u8 plogi_rjt; | |
331 | bool plogi_rjt_set; | |
332 | u32 plogi_dst_fcid[5]; | |
333 | bool plogi_dst_fcid_set[5]; | |
334 | struct qed_mfw_tlv_time plogi_tstamp[5]; | |
335 | u32 plogi_acc_src_fcid[5]; | |
336 | bool plogi_acc_src_fcid_set[5]; | |
337 | struct qed_mfw_tlv_time plogi_acc_tstamp[5]; | |
338 | u8 tx_plogos; | |
339 | bool tx_plogos_set; | |
340 | u8 plogo_acc; | |
341 | bool plogo_acc_set; | |
342 | u8 plogo_rjt; | |
343 | bool plogo_rjt_set; | |
344 | u32 plogo_src_fcid[5]; | |
345 | bool plogo_src_fcid_set[5]; | |
346 | struct qed_mfw_tlv_time plogo_tstamp[5]; | |
347 | u8 rx_logos; | |
348 | bool rx_logos_set; | |
349 | u8 tx_accs; | |
350 | bool tx_accs_set; | |
351 | u8 tx_prlis; | |
352 | bool tx_prlis_set; | |
353 | u8 rx_accs; | |
354 | bool rx_accs_set; | |
355 | u8 tx_abts; | |
356 | bool tx_abts_set; | |
357 | u8 rx_abts_acc; | |
358 | bool rx_abts_acc_set; | |
359 | u8 rx_abts_rjt; | |
360 | bool rx_abts_rjt_set; | |
361 | u32 abts_dst_fcid[5]; | |
362 | bool abts_dst_fcid_set[5]; | |
363 | struct qed_mfw_tlv_time abts_tstamp[5]; | |
364 | u8 rx_rscn; | |
365 | bool rx_rscn_set; | |
366 | u32 rx_rscn_nport[4]; | |
367 | bool rx_rscn_nport_set[4]; | |
368 | u8 tx_lun_rst; | |
369 | bool tx_lun_rst_set; | |
370 | u8 abort_task_sets; | |
371 | bool abort_task_sets_set; | |
372 | u8 tx_tprlos; | |
373 | bool tx_tprlos_set; | |
374 | u8 tx_nos; | |
375 | bool tx_nos_set; | |
376 | u8 rx_nos; | |
377 | bool rx_nos_set; | |
378 | u8 ols; | |
379 | bool ols_set; | |
380 | u8 lr; | |
381 | bool lr_set; | |
382 | u8 lrr; | |
383 | bool lrr_set; | |
384 | u8 tx_lip; | |
385 | bool tx_lip_set; | |
386 | u8 rx_lip; | |
387 | bool rx_lip_set; | |
388 | u8 eofa; | |
389 | bool eofa_set; | |
390 | u8 eofni; | |
391 | bool eofni_set; | |
392 | u8 scsi_chks; | |
393 | bool scsi_chks_set; | |
394 | u8 scsi_cond_met; | |
395 | bool scsi_cond_met_set; | |
396 | u8 scsi_busy; | |
397 | bool scsi_busy_set; | |
398 | u8 scsi_inter; | |
399 | bool scsi_inter_set; | |
400 | u8 scsi_inter_cond_met; | |
401 | bool scsi_inter_cond_met_set; | |
402 | u8 scsi_rsv_conflicts; | |
403 | bool scsi_rsv_conflicts_set; | |
404 | u8 scsi_tsk_full; | |
405 | bool scsi_tsk_full_set; | |
406 | u8 scsi_aca_active; | |
407 | bool scsi_aca_active_set; | |
408 | u8 scsi_tsk_abort; | |
409 | bool scsi_tsk_abort_set; | |
410 | u32 scsi_rx_chk[5]; | |
411 | bool scsi_rx_chk_set[5]; | |
412 | struct qed_mfw_tlv_time scsi_chk_tstamp[5]; | |
413 | }; | |
414 | ||
77a509e4 SRK |
415 | struct qed_mfw_tlv_iscsi { |
416 | u8 target_llmnr; | |
417 | bool target_llmnr_set; | |
418 | u8 header_digest; | |
419 | bool header_digest_set; | |
420 | u8 data_digest; | |
421 | bool data_digest_set; | |
422 | u8 auth_method; | |
423 | #define QED_MFW_TLV_AUTH_METHOD_NONE (1) | |
424 | #define QED_MFW_TLV_AUTH_METHOD_CHAP (2) | |
425 | #define QED_MFW_TLV_AUTH_METHOD_MUTUAL_CHAP (3) | |
426 | bool auth_method_set; | |
427 | u16 boot_taget_portal; | |
428 | bool boot_taget_portal_set; | |
429 | u16 frame_size; | |
430 | bool frame_size_set; | |
431 | u16 tx_desc_size; | |
432 | bool tx_desc_size_set; | |
433 | u16 rx_desc_size; | |
434 | bool rx_desc_size_set; | |
435 | u8 boot_progress; | |
436 | bool boot_progress_set; | |
437 | u16 tx_desc_qdepth; | |
438 | bool tx_desc_qdepth_set; | |
439 | u16 rx_desc_qdepth; | |
440 | bool rx_desc_qdepth_set; | |
441 | u64 rx_frames; | |
442 | bool rx_frames_set; | |
443 | u64 rx_bytes; | |
444 | bool rx_bytes_set; | |
445 | u64 tx_frames; | |
446 | bool tx_frames_set; | |
447 | u64 tx_bytes; | |
448 | bool tx_bytes_set; | |
449 | }; | |
450 | ||
fe56b9e6 YM |
451 | #define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \ |
452 | (void __iomem *)(reg_addr)) | |
453 | ||
454 | #define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr)) | |
455 | ||
41822878 | 456 | #define QED_COALESCE_MAX 0x1FF |
0e191827 | 457 | #define QED_DEFAULT_RX_USECS 12 |
bf5a94bf | 458 | #define QED_DEFAULT_TX_USECS 48 |
fe56b9e6 YM |
459 | |
460 | /* forward */ | |
461 | struct qed_dev; | |
462 | ||
463 | struct qed_eth_pf_params { | |
464 | /* The following parameters are used during HW-init | |
465 | * and these parameters need to be passed as arguments | |
466 | * to update_pf_params routine invoked before slowpath start | |
467 | */ | |
468 | u16 num_cons; | |
d51e4af5 | 469 | |
08bc8f15 MY |
470 | /* per-VF number of CIDs */ |
471 | u8 num_vf_cons; | |
472 | #define ETH_PF_PARAMS_VF_CONS_DEFAULT (32) | |
473 | ||
d51e4af5 CM |
474 | /* To enable arfs, previous to HW-init a positive number needs to be |
475 | * set [as filters require allocated searcher ILT memory]. | |
476 | * This will set the maximal number of configured steering-filters. | |
477 | */ | |
478 | u32 num_arfs_filters; | |
fe56b9e6 YM |
479 | }; |
480 | ||
1e128c81 AE |
481 | struct qed_fcoe_pf_params { |
482 | /* The following parameters are used during protocol-init */ | |
483 | u64 glbl_q_params_addr; | |
484 | u64 bdq_pbl_base_addr[2]; | |
485 | ||
486 | /* The following parameters are used during HW-init | |
487 | * and these parameters need to be passed as arguments | |
488 | * to update_pf_params routine invoked before slowpath start | |
489 | */ | |
490 | u16 num_cons; | |
491 | u16 num_tasks; | |
492 | ||
493 | /* The following parameters are used during protocol-init */ | |
494 | u16 sq_num_pbl_pages; | |
495 | ||
496 | u16 cq_num_entries; | |
497 | u16 cmdq_num_entries; | |
498 | u16 rq_buffer_log_size; | |
499 | u16 mtu; | |
500 | u16 dummy_icid; | |
501 | u16 bdq_xoff_threshold[2]; | |
502 | u16 bdq_xon_threshold[2]; | |
503 | u16 rq_buffer_size; | |
504 | u8 num_cqs; /* num of global CQs */ | |
505 | u8 log_page_size; | |
506 | u8 gl_rq_pi; | |
507 | u8 gl_cmd_pi; | |
508 | u8 debug_mode; | |
509 | u8 is_target; | |
510 | u8 bdq_pbl_num_entries[2]; | |
511 | }; | |
512 | ||
c5ac9319 YM |
513 | /* Most of the the parameters below are described in the FW iSCSI / TCP HSI */ |
514 | struct qed_iscsi_pf_params { | |
515 | u64 glbl_q_params_addr; | |
da090917 | 516 | u64 bdq_pbl_base_addr[3]; |
c5ac9319 YM |
517 | u16 cq_num_entries; |
518 | u16 cmdq_num_entries; | |
fc831825 | 519 | u32 two_msl_timer; |
c5ac9319 | 520 | u16 tx_sws_timer; |
c5ac9319 YM |
521 | |
522 | /* The following parameters are used during HW-init | |
523 | * and these parameters need to be passed as arguments | |
524 | * to update_pf_params routine invoked before slowpath start | |
525 | */ | |
526 | u16 num_cons; | |
527 | u16 num_tasks; | |
528 | ||
529 | /* The following parameters are used during protocol-init */ | |
530 | u16 half_way_close_timeout; | |
da090917 TT |
531 | u16 bdq_xoff_threshold[3]; |
532 | u16 bdq_xon_threshold[3]; | |
c5ac9319 YM |
533 | u16 cmdq_xoff_threshold; |
534 | u16 cmdq_xon_threshold; | |
535 | u16 rq_buffer_size; | |
536 | ||
537 | u8 num_sq_pages_in_ring; | |
538 | u8 num_r2tq_pages_in_ring; | |
539 | u8 num_uhq_pages_in_ring; | |
540 | u8 num_queues; | |
541 | u8 log_page_size; | |
542 | u8 rqe_log_size; | |
543 | u8 max_fin_rt; | |
544 | u8 gl_rq_pi; | |
545 | u8 gl_cmd_pi; | |
546 | u8 debug_mode; | |
547 | u8 ll2_ooo_queue_id; | |
c5ac9319 YM |
548 | |
549 | u8 is_target; | |
da090917 TT |
550 | u8 is_soc_en; |
551 | u8 soc_num_of_blocks_log; | |
552 | u8 bdq_pbl_num_entries[3]; | |
c5ac9319 YM |
553 | }; |
554 | ||
555 | struct qed_rdma_pf_params { | |
556 | /* Supplied to QED during resource allocation (may affect the ILT and | |
557 | * the doorbell BAR). | |
558 | */ | |
559 | u32 min_dpis; /* number of requested DPIs */ | |
c5ac9319 YM |
560 | u32 num_qps; /* number of requested Queue Pairs */ |
561 | u32 num_srqs; /* number of requested SRQ */ | |
562 | u8 roce_edpm_mode; /* see QED_ROCE_EDPM_MODE_ENABLE */ | |
563 | u8 gl_pi; /* protocol index */ | |
564 | ||
565 | /* Will allocate rate limiters to be used with QPs */ | |
566 | u8 enable_dcqcn; | |
567 | }; | |
568 | ||
fe56b9e6 YM |
569 | struct qed_pf_params { |
570 | struct qed_eth_pf_params eth_pf_params; | |
1e128c81 | 571 | struct qed_fcoe_pf_params fcoe_pf_params; |
c5ac9319 YM |
572 | struct qed_iscsi_pf_params iscsi_pf_params; |
573 | struct qed_rdma_pf_params rdma_pf_params; | |
fe56b9e6 YM |
574 | }; |
575 | ||
576 | enum qed_int_mode { | |
577 | QED_INT_MODE_INTA, | |
578 | QED_INT_MODE_MSIX, | |
579 | QED_INT_MODE_MSI, | |
580 | QED_INT_MODE_POLL, | |
581 | }; | |
582 | ||
583 | struct qed_sb_info { | |
21dd79e8 | 584 | struct status_block_e4 *sb_virt; |
a2e7699e TT |
585 | dma_addr_t sb_phys; |
586 | u32 sb_ack; /* Last given ack */ | |
587 | u16 igu_sb_id; | |
588 | void __iomem *igu_addr; | |
589 | u8 flags; | |
590 | #define QED_SB_INFO_INIT 0x1 | |
591 | #define QED_SB_INFO_SETUP 0x2 | |
592 | ||
593 | struct qed_dev *cdev; | |
fe56b9e6 YM |
594 | }; |
595 | ||
9c79ddaa MY |
596 | enum qed_dev_type { |
597 | QED_DEV_TYPE_BB, | |
598 | QED_DEV_TYPE_AH, | |
599 | }; | |
600 | ||
fe56b9e6 YM |
601 | struct qed_dev_info { |
602 | unsigned long pci_mem_start; | |
603 | unsigned long pci_mem_end; | |
604 | unsigned int pci_irq; | |
605 | u8 num_hwfns; | |
606 | ||
607 | u8 hw_mac[ETH_ALEN]; | |
fe56b9e6 YM |
608 | |
609 | /* FW version */ | |
610 | u16 fw_major; | |
611 | u16 fw_minor; | |
612 | u16 fw_rev; | |
613 | u16 fw_eng; | |
614 | ||
615 | /* MFW version */ | |
616 | u32 mfw_rev; | |
ae33666a TT |
617 | #define QED_MFW_VERSION_0_MASK 0x000000FF |
618 | #define QED_MFW_VERSION_0_OFFSET 0 | |
619 | #define QED_MFW_VERSION_1_MASK 0x0000FF00 | |
620 | #define QED_MFW_VERSION_1_OFFSET 8 | |
621 | #define QED_MFW_VERSION_2_MASK 0x00FF0000 | |
622 | #define QED_MFW_VERSION_2_OFFSET 16 | |
623 | #define QED_MFW_VERSION_3_MASK 0xFF000000 | |
624 | #define QED_MFW_VERSION_3_OFFSET 24 | |
fe56b9e6 YM |
625 | |
626 | u32 flash_size; | |
0bc5fe85 | 627 | bool b_inter_pf_switch; |
831bfb0e | 628 | bool tx_switching; |
cee9fbd8 | 629 | bool rdma_supported; |
0fefbfba | 630 | u16 mtu; |
14d39648 MY |
631 | |
632 | bool wol_support; | |
9c79ddaa | 633 | |
ae33666a TT |
634 | /* MBI version */ |
635 | u32 mbi_version; | |
636 | #define QED_MBI_VERSION_0_MASK 0x000000FF | |
637 | #define QED_MBI_VERSION_0_OFFSET 0 | |
638 | #define QED_MBI_VERSION_1_MASK 0x0000FF00 | |
639 | #define QED_MBI_VERSION_1_OFFSET 8 | |
640 | #define QED_MBI_VERSION_2_MASK 0x00FF0000 | |
641 | #define QED_MBI_VERSION_2_OFFSET 16 | |
642 | ||
9c79ddaa | 643 | enum qed_dev_type dev_type; |
19489c7f CM |
644 | |
645 | /* Output parameters for qede */ | |
646 | bool vxlan_enable; | |
647 | bool gre_enable; | |
648 | bool geneve_enable; | |
3c5da942 MY |
649 | |
650 | u8 abs_pf_id; | |
fe56b9e6 YM |
651 | }; |
652 | ||
653 | enum qed_sb_type { | |
654 | QED_SB_TYPE_L2_QUEUE, | |
51ff1725 | 655 | QED_SB_TYPE_CNQ, |
fc831825 | 656 | QED_SB_TYPE_STORAGE, |
fe56b9e6 YM |
657 | }; |
658 | ||
659 | enum qed_protocol { | |
660 | QED_PROTOCOL_ETH, | |
c5ac9319 | 661 | QED_PROTOCOL_ISCSI, |
1e128c81 | 662 | QED_PROTOCOL_FCOE, |
fe56b9e6 YM |
663 | }; |
664 | ||
054c67d1 SRK |
665 | enum qed_link_mode_bits { |
666 | QED_LM_FIBRE_BIT = BIT(0), | |
667 | QED_LM_Autoneg_BIT = BIT(1), | |
668 | QED_LM_Asym_Pause_BIT = BIT(2), | |
669 | QED_LM_Pause_BIT = BIT(3), | |
670 | QED_LM_1000baseT_Half_BIT = BIT(4), | |
671 | QED_LM_1000baseT_Full_BIT = BIT(5), | |
672 | QED_LM_10000baseKR_Full_BIT = BIT(6), | |
673 | QED_LM_25000baseKR_Full_BIT = BIT(7), | |
674 | QED_LM_40000baseLR4_Full_BIT = BIT(8), | |
675 | QED_LM_50000baseKR2_Full_BIT = BIT(9), | |
676 | QED_LM_100000baseKR4_Full_BIT = BIT(10), | |
677 | QED_LM_COUNT = 11 | |
678 | }; | |
679 | ||
fe56b9e6 YM |
680 | struct qed_link_params { |
681 | bool link_up; | |
682 | ||
683 | #define QED_LINK_OVERRIDE_SPEED_AUTONEG BIT(0) | |
684 | #define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS BIT(1) | |
685 | #define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED BIT(2) | |
686 | #define QED_LINK_OVERRIDE_PAUSE_CONFIG BIT(3) | |
03dc76ca | 687 | #define QED_LINK_OVERRIDE_LOOPBACK_MODE BIT(4) |
645874e5 | 688 | #define QED_LINK_OVERRIDE_EEE_CONFIG BIT(5) |
fe56b9e6 YM |
689 | u32 override_flags; |
690 | bool autoneg; | |
691 | u32 adv_speeds; | |
692 | u32 forced_speed; | |
693 | #define QED_LINK_PAUSE_AUTONEG_ENABLE BIT(0) | |
694 | #define QED_LINK_PAUSE_RX_ENABLE BIT(1) | |
695 | #define QED_LINK_PAUSE_TX_ENABLE BIT(2) | |
696 | u32 pause_config; | |
03dc76ca SRK |
697 | #define QED_LINK_LOOPBACK_NONE BIT(0) |
698 | #define QED_LINK_LOOPBACK_INT_PHY BIT(1) | |
699 | #define QED_LINK_LOOPBACK_EXT_PHY BIT(2) | |
700 | #define QED_LINK_LOOPBACK_EXT BIT(3) | |
701 | #define QED_LINK_LOOPBACK_MAC BIT(4) | |
702 | u32 loopback_mode; | |
645874e5 | 703 | struct qed_link_eee_params eee; |
fe56b9e6 YM |
704 | }; |
705 | ||
706 | struct qed_link_output { | |
707 | bool link_up; | |
708 | ||
d194fd26 YM |
709 | /* In QED_LM_* defs */ |
710 | u32 supported_caps; | |
711 | u32 advertised_caps; | |
712 | u32 lp_caps; | |
713 | ||
fe56b9e6 YM |
714 | u32 speed; /* In Mb/s */ |
715 | u8 duplex; /* In DUPLEX defs */ | |
716 | u8 port; /* In PORT defs */ | |
717 | bool autoneg; | |
718 | u32 pause_config; | |
645874e5 SRK |
719 | |
720 | /* EEE - capability & param */ | |
721 | bool eee_supported; | |
722 | bool eee_active; | |
723 | u8 sup_caps; | |
724 | struct qed_link_eee_params eee; | |
fe56b9e6 YM |
725 | }; |
726 | ||
1408cc1f YM |
727 | struct qed_probe_params { |
728 | enum qed_protocol protocol; | |
729 | u32 dp_module; | |
730 | u8 dp_level; | |
731 | bool is_vf; | |
732 | }; | |
733 | ||
fe56b9e6 YM |
734 | #define QED_DRV_VER_STR_SIZE 12 |
735 | struct qed_slowpath_params { | |
736 | u32 int_mode; | |
737 | u8 drv_major; | |
738 | u8 drv_minor; | |
739 | u8 drv_rev; | |
740 | u8 drv_eng; | |
741 | u8 name[QED_DRV_VER_STR_SIZE]; | |
742 | }; | |
743 | ||
744 | #define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */ | |
745 | ||
746 | struct qed_int_info { | |
747 | struct msix_entry *msix; | |
748 | u8 msix_cnt; | |
749 | ||
750 | /* This should be updated by the protocol driver */ | |
751 | u8 used_cnt; | |
752 | }; | |
753 | ||
59ccf86f SRK |
754 | struct qed_generic_tlvs { |
755 | #define QED_TLV_IP_CSUM BIT(0) | |
756 | #define QED_TLV_LSO BIT(1) | |
757 | u16 feat_flags; | |
758 | #define QED_TLV_MAC_COUNT 3 | |
759 | u8 mac[QED_TLV_MAC_COUNT][ETH_ALEN]; | |
760 | }; | |
761 | ||
b51dab46 SRK |
762 | #define QED_I2C_DEV_ADDR_A0 0xA0 |
763 | #define QED_I2C_DEV_ADDR_A2 0xA2 | |
764 | ||
3a69cae8 SRK |
765 | #define QED_NVM_SIGNATURE 0x12435687 |
766 | ||
767 | enum qed_nvm_flash_cmd { | |
768 | QED_NVM_FLASH_CMD_FILE_DATA = 0x2, | |
769 | QED_NVM_FLASH_CMD_FILE_START = 0x3, | |
770 | QED_NVM_FLASH_CMD_NVM_CHANGE = 0x4, | |
771 | QED_NVM_FLASH_CMD_NVM_MAX, | |
772 | }; | |
773 | ||
fe56b9e6 | 774 | struct qed_common_cb_ops { |
d51e4af5 | 775 | void (*arfs_filter_op)(void *dev, void *fltr, u8 fw_rc); |
fe56b9e6 YM |
776 | void (*link_update)(void *dev, |
777 | struct qed_link_output *link); | |
1e128c81 | 778 | void (*dcbx_aen)(void *dev, struct qed_dcbx_get *get, u32 mib_type); |
59ccf86f SRK |
779 | void (*get_generic_tlv_data)(void *dev, struct qed_generic_tlvs *data); |
780 | void (*get_protocol_tlv_data)(void *dev, void *data); | |
fe56b9e6 YM |
781 | }; |
782 | ||
03dc76ca SRK |
783 | struct qed_selftest_ops { |
784 | /** | |
785 | * @brief selftest_interrupt - Perform interrupt test | |
786 | * | |
787 | * @param cdev | |
788 | * | |
789 | * @return 0 on success, error otherwise. | |
790 | */ | |
791 | int (*selftest_interrupt)(struct qed_dev *cdev); | |
792 | ||
793 | /** | |
794 | * @brief selftest_memory - Perform memory test | |
795 | * | |
796 | * @param cdev | |
797 | * | |
798 | * @return 0 on success, error otherwise. | |
799 | */ | |
800 | int (*selftest_memory)(struct qed_dev *cdev); | |
801 | ||
802 | /** | |
803 | * @brief selftest_register - Perform register test | |
804 | * | |
805 | * @param cdev | |
806 | * | |
807 | * @return 0 on success, error otherwise. | |
808 | */ | |
809 | int (*selftest_register)(struct qed_dev *cdev); | |
810 | ||
811 | /** | |
812 | * @brief selftest_clock - Perform clock test | |
813 | * | |
814 | * @param cdev | |
815 | * | |
816 | * @return 0 on success, error otherwise. | |
817 | */ | |
818 | int (*selftest_clock)(struct qed_dev *cdev); | |
7a4b21b7 MY |
819 | |
820 | /** | |
821 | * @brief selftest_nvram - Perform nvram test | |
822 | * | |
823 | * @param cdev | |
824 | * | |
825 | * @return 0 on success, error otherwise. | |
826 | */ | |
827 | int (*selftest_nvram) (struct qed_dev *cdev); | |
03dc76ca SRK |
828 | }; |
829 | ||
fe56b9e6 | 830 | struct qed_common_ops { |
03dc76ca SRK |
831 | struct qed_selftest_ops *selftest; |
832 | ||
fe56b9e6 | 833 | struct qed_dev* (*probe)(struct pci_dev *dev, |
1408cc1f | 834 | struct qed_probe_params *params); |
fe56b9e6 YM |
835 | |
836 | void (*remove)(struct qed_dev *cdev); | |
837 | ||
838 | int (*set_power_state)(struct qed_dev *cdev, | |
839 | pci_power_t state); | |
840 | ||
712c3cbf | 841 | void (*set_name) (struct qed_dev *cdev, char name[]); |
fe56b9e6 YM |
842 | |
843 | /* Client drivers need to make this call before slowpath_start. | |
844 | * PF params required for the call before slowpath_start is | |
845 | * documented within the qed_pf_params structure definition. | |
846 | */ | |
847 | void (*update_pf_params)(struct qed_dev *cdev, | |
848 | struct qed_pf_params *params); | |
849 | int (*slowpath_start)(struct qed_dev *cdev, | |
850 | struct qed_slowpath_params *params); | |
851 | ||
852 | int (*slowpath_stop)(struct qed_dev *cdev); | |
853 | ||
854 | /* Requests to use `cnt' interrupts for fastpath. | |
855 | * upon success, returns number of interrupts allocated for fastpath. | |
856 | */ | |
857 | int (*set_fp_int)(struct qed_dev *cdev, | |
858 | u16 cnt); | |
859 | ||
860 | /* Fills `info' with pointers required for utilizing interrupts */ | |
861 | int (*get_fp_int)(struct qed_dev *cdev, | |
862 | struct qed_int_info *info); | |
863 | ||
864 | u32 (*sb_init)(struct qed_dev *cdev, | |
865 | struct qed_sb_info *sb_info, | |
866 | void *sb_virt_addr, | |
867 | dma_addr_t sb_phy_addr, | |
868 | u16 sb_id, | |
869 | enum qed_sb_type type); | |
870 | ||
871 | u32 (*sb_release)(struct qed_dev *cdev, | |
872 | struct qed_sb_info *sb_info, | |
873 | u16 sb_id); | |
874 | ||
875 | void (*simd_handler_config)(struct qed_dev *cdev, | |
876 | void *token, | |
877 | int index, | |
878 | void (*handler)(void *)); | |
879 | ||
880 | void (*simd_handler_clean)(struct qed_dev *cdev, | |
881 | int index); | |
1e128c81 AE |
882 | int (*dbg_grc)(struct qed_dev *cdev, |
883 | void *buffer, u32 *num_dumped_bytes); | |
884 | ||
885 | int (*dbg_grc_size)(struct qed_dev *cdev); | |
fe7cd2bf | 886 | |
e0971c83 TT |
887 | int (*dbg_all_data) (struct qed_dev *cdev, void *buffer); |
888 | ||
889 | int (*dbg_all_data_size) (struct qed_dev *cdev); | |
890 | ||
fe7cd2bf YM |
891 | /** |
892 | * @brief can_link_change - can the instance change the link or not | |
893 | * | |
894 | * @param cdev | |
895 | * | |
896 | * @return true if link-change is allowed, false otherwise. | |
897 | */ | |
898 | bool (*can_link_change)(struct qed_dev *cdev); | |
899 | ||
fe56b9e6 YM |
900 | /** |
901 | * @brief set_link - set links according to params | |
902 | * | |
903 | * @param cdev | |
904 | * @param params - values used to override the default link configuration | |
905 | * | |
906 | * @return 0 on success, error otherwise. | |
907 | */ | |
908 | int (*set_link)(struct qed_dev *cdev, | |
909 | struct qed_link_params *params); | |
910 | ||
911 | /** | |
912 | * @brief get_link - returns the current link state. | |
913 | * | |
914 | * @param cdev | |
915 | * @param if_link - structure to be filled with current link configuration. | |
916 | */ | |
917 | void (*get_link)(struct qed_dev *cdev, | |
918 | struct qed_link_output *if_link); | |
919 | ||
920 | /** | |
921 | * @brief - drains chip in case Tx completions fail to arrive due to pause. | |
922 | * | |
923 | * @param cdev | |
924 | */ | |
925 | int (*drain)(struct qed_dev *cdev); | |
926 | ||
927 | /** | |
928 | * @brief update_msglvl - update module debug level | |
929 | * | |
930 | * @param cdev | |
931 | * @param dp_module | |
932 | * @param dp_level | |
933 | */ | |
934 | void (*update_msglvl)(struct qed_dev *cdev, | |
935 | u32 dp_module, | |
936 | u8 dp_level); | |
937 | ||
938 | int (*chain_alloc)(struct qed_dev *cdev, | |
939 | enum qed_chain_use_mode intended_use, | |
940 | enum qed_chain_mode mode, | |
a91eb52a YM |
941 | enum qed_chain_cnt_type cnt_type, |
942 | u32 num_elems, | |
fe56b9e6 | 943 | size_t elem_size, |
1a4a6975 MY |
944 | struct qed_chain *p_chain, |
945 | struct qed_chain_ext_pbl *ext_pbl); | |
fe56b9e6 YM |
946 | |
947 | void (*chain_free)(struct qed_dev *cdev, | |
948 | struct qed_chain *p_chain); | |
91420b83 | 949 | |
3a69cae8 SRK |
950 | /** |
951 | * @brief nvm_flash - Flash nvm data. | |
952 | * | |
953 | * @param cdev | |
954 | * @param name - file containing the data | |
955 | * | |
956 | * @return 0 on success, error otherwise. | |
957 | */ | |
958 | int (*nvm_flash)(struct qed_dev *cdev, const char *name); | |
959 | ||
20675b37 MY |
960 | /** |
961 | * @brief nvm_get_image - reads an entire image from nvram | |
962 | * | |
963 | * @param cdev | |
964 | * @param type - type of the request nvram image | |
965 | * @param buf - preallocated buffer to fill with the image | |
966 | * @param len - length of the allocated buffer | |
967 | * | |
968 | * @return 0 on success, error otherwise | |
969 | */ | |
970 | int (*nvm_get_image)(struct qed_dev *cdev, | |
971 | enum qed_nvm_images type, u8 *buf, u16 len); | |
972 | ||
722003ac SRK |
973 | /** |
974 | * @brief set_coalesce - Configure Rx coalesce value in usec | |
975 | * | |
976 | * @param cdev | |
977 | * @param rx_coal - Rx coalesce value in usec | |
978 | * @param tx_coal - Tx coalesce value in usec | |
979 | * @param qid - Queue index | |
980 | * @param sb_id - Status Block Id | |
981 | * | |
982 | * @return 0 on success, error otherwise. | |
983 | */ | |
477f2d14 RV |
984 | int (*set_coalesce)(struct qed_dev *cdev, |
985 | u16 rx_coal, u16 tx_coal, void *handle); | |
722003ac | 986 | |
91420b83 SK |
987 | /** |
988 | * @brief set_led - Configure LED mode | |
989 | * | |
990 | * @param cdev | |
991 | * @param mode - LED mode | |
992 | * | |
993 | * @return 0 on success, error otherwise. | |
994 | */ | |
995 | int (*set_led)(struct qed_dev *cdev, | |
996 | enum qed_led_mode mode); | |
0fefbfba SK |
997 | |
998 | /** | |
999 | * @brief update_drv_state - API to inform the change in the driver state. | |
1000 | * | |
1001 | * @param cdev | |
1002 | * @param active | |
1003 | * | |
1004 | */ | |
1005 | int (*update_drv_state)(struct qed_dev *cdev, bool active); | |
1006 | ||
1007 | /** | |
1008 | * @brief update_mac - API to inform the change in the mac address | |
1009 | * | |
1010 | * @param cdev | |
1011 | * @param mac | |
1012 | * | |
1013 | */ | |
1014 | int (*update_mac)(struct qed_dev *cdev, u8 *mac); | |
1015 | ||
1016 | /** | |
1017 | * @brief update_mtu - API to inform the change in the mtu | |
1018 | * | |
1019 | * @param cdev | |
1020 | * @param mtu | |
1021 | * | |
1022 | */ | |
1023 | int (*update_mtu)(struct qed_dev *cdev, u16 mtu); | |
14d39648 MY |
1024 | |
1025 | /** | |
1026 | * @brief update_wol - update of changes in the WoL configuration | |
1027 | * | |
1028 | * @param cdev | |
1029 | * @param enabled - true iff WoL should be enabled. | |
1030 | */ | |
1031 | int (*update_wol) (struct qed_dev *cdev, bool enabled); | |
b51dab46 SRK |
1032 | |
1033 | /** | |
1034 | * @brief read_module_eeprom | |
1035 | * | |
1036 | * @param cdev | |
1037 | * @param buf - buffer | |
1038 | * @param dev_addr - PHY device memory region | |
1039 | * @param offset - offset into eeprom contents to be read | |
1040 | * @param len - buffer length, i.e., max bytes to be read | |
1041 | */ | |
1042 | int (*read_module_eeprom)(struct qed_dev *cdev, | |
1043 | char *buf, u8 dev_addr, u32 offset, u32 len); | |
fe56b9e6 YM |
1044 | }; |
1045 | ||
fe56b9e6 YM |
1046 | #define MASK_FIELD(_name, _value) \ |
1047 | ((_value) &= (_name ## _MASK)) | |
1048 | ||
1049 | #define FIELD_VALUE(_name, _value) \ | |
1050 | ((_value & _name ## _MASK) << _name ## _SHIFT) | |
1051 | ||
1052 | #define SET_FIELD(value, name, flag) \ | |
1053 | do { \ | |
1054 | (value) &= ~(name ## _MASK << name ## _SHIFT); \ | |
1055 | (value) |= (((u64)flag) << (name ## _SHIFT)); \ | |
1056 | } while (0) | |
1057 | ||
1058 | #define GET_FIELD(value, name) \ | |
1059 | (((value) >> (name ## _SHIFT)) & name ## _MASK) | |
1060 | ||
1061 | /* Debug print definitions */ | |
9d7650c2 MY |
1062 | #define DP_ERR(cdev, fmt, ...) \ |
1063 | do { \ | |
1064 | pr_err("[%s:%d(%s)]" fmt, \ | |
1065 | __func__, __LINE__, \ | |
1066 | DP_NAME(cdev) ? DP_NAME(cdev) : "", \ | |
1067 | ## __VA_ARGS__); \ | |
1068 | } while (0) | |
fe56b9e6 YM |
1069 | |
1070 | #define DP_NOTICE(cdev, fmt, ...) \ | |
1071 | do { \ | |
1072 | if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \ | |
1073 | pr_notice("[%s:%d(%s)]" fmt, \ | |
1074 | __func__, __LINE__, \ | |
1075 | DP_NAME(cdev) ? DP_NAME(cdev) : "", \ | |
1076 | ## __VA_ARGS__); \ | |
1077 | \ | |
1078 | } \ | |
1079 | } while (0) | |
1080 | ||
1081 | #define DP_INFO(cdev, fmt, ...) \ | |
1082 | do { \ | |
1083 | if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) { \ | |
1084 | pr_notice("[%s:%d(%s)]" fmt, \ | |
1085 | __func__, __LINE__, \ | |
1086 | DP_NAME(cdev) ? DP_NAME(cdev) : "", \ | |
1087 | ## __VA_ARGS__); \ | |
1088 | } \ | |
1089 | } while (0) | |
1090 | ||
1091 | #define DP_VERBOSE(cdev, module, fmt, ...) \ | |
1092 | do { \ | |
1093 | if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) && \ | |
1094 | ((cdev)->dp_module & module))) { \ | |
1095 | pr_notice("[%s:%d(%s)]" fmt, \ | |
1096 | __func__, __LINE__, \ | |
1097 | DP_NAME(cdev) ? DP_NAME(cdev) : "", \ | |
1098 | ## __VA_ARGS__); \ | |
1099 | } \ | |
1100 | } while (0) | |
1101 | ||
1102 | enum DP_LEVEL { | |
1103 | QED_LEVEL_VERBOSE = 0x0, | |
1104 | QED_LEVEL_INFO = 0x1, | |
1105 | QED_LEVEL_NOTICE = 0x2, | |
1106 | QED_LEVEL_ERR = 0x3, | |
1107 | }; | |
1108 | ||
1109 | #define QED_LOG_LEVEL_SHIFT (30) | |
1110 | #define QED_LOG_VERBOSE_MASK (0x3fffffff) | |
1111 | #define QED_LOG_INFO_MASK (0x40000000) | |
1112 | #define QED_LOG_NOTICE_MASK (0x80000000) | |
1113 | ||
1114 | enum DP_MODULE { | |
1115 | QED_MSG_SPQ = 0x10000, | |
1116 | QED_MSG_STATS = 0x20000, | |
1117 | QED_MSG_DCB = 0x40000, | |
1118 | QED_MSG_IOV = 0x80000, | |
1119 | QED_MSG_SP = 0x100000, | |
1120 | QED_MSG_STORAGE = 0x200000, | |
1121 | QED_MSG_CXT = 0x800000, | |
0a7fb11c | 1122 | QED_MSG_LL2 = 0x1000000, |
fe56b9e6 | 1123 | QED_MSG_ILT = 0x2000000, |
51ff1725 | 1124 | QED_MSG_RDMA = 0x4000000, |
fe56b9e6 YM |
1125 | QED_MSG_DEBUG = 0x8000000, |
1126 | /* to be added...up to 0x8000000 */ | |
1127 | }; | |
1128 | ||
fc48b7a6 YM |
1129 | enum qed_mf_mode { |
1130 | QED_MF_DEFAULT, | |
1131 | QED_MF_OVLAN, | |
1132 | QED_MF_NPAR, | |
1133 | }; | |
1134 | ||
9c79ddaa | 1135 | struct qed_eth_stats_common { |
fe56b9e6 YM |
1136 | u64 no_buff_discards; |
1137 | u64 packet_too_big_discard; | |
1138 | u64 ttl0_discard; | |
1139 | u64 rx_ucast_bytes; | |
1140 | u64 rx_mcast_bytes; | |
1141 | u64 rx_bcast_bytes; | |
1142 | u64 rx_ucast_pkts; | |
1143 | u64 rx_mcast_pkts; | |
1144 | u64 rx_bcast_pkts; | |
1145 | u64 mftag_filter_discards; | |
1146 | u64 mac_filter_discards; | |
608e00d0 | 1147 | u64 gft_filter_drop; |
fe56b9e6 YM |
1148 | u64 tx_ucast_bytes; |
1149 | u64 tx_mcast_bytes; | |
1150 | u64 tx_bcast_bytes; | |
1151 | u64 tx_ucast_pkts; | |
1152 | u64 tx_mcast_pkts; | |
1153 | u64 tx_bcast_pkts; | |
1154 | u64 tx_err_drop_pkts; | |
1155 | u64 tpa_coalesced_pkts; | |
1156 | u64 tpa_coalesced_events; | |
1157 | u64 tpa_aborts_num; | |
1158 | u64 tpa_not_coalesced_pkts; | |
1159 | u64 tpa_coalesced_bytes; | |
1160 | ||
1161 | /* port */ | |
1162 | u64 rx_64_byte_packets; | |
d4967cf3 YM |
1163 | u64 rx_65_to_127_byte_packets; |
1164 | u64 rx_128_to_255_byte_packets; | |
1165 | u64 rx_256_to_511_byte_packets; | |
1166 | u64 rx_512_to_1023_byte_packets; | |
1167 | u64 rx_1024_to_1518_byte_packets; | |
fe56b9e6 YM |
1168 | u64 rx_crc_errors; |
1169 | u64 rx_mac_crtl_frames; | |
1170 | u64 rx_pause_frames; | |
1171 | u64 rx_pfc_frames; | |
1172 | u64 rx_align_errors; | |
1173 | u64 rx_carrier_errors; | |
1174 | u64 rx_oversize_packets; | |
1175 | u64 rx_jabbers; | |
1176 | u64 rx_undersize_packets; | |
1177 | u64 rx_fragments; | |
1178 | u64 tx_64_byte_packets; | |
1179 | u64 tx_65_to_127_byte_packets; | |
1180 | u64 tx_128_to_255_byte_packets; | |
1181 | u64 tx_256_to_511_byte_packets; | |
1182 | u64 tx_512_to_1023_byte_packets; | |
1183 | u64 tx_1024_to_1518_byte_packets; | |
fe56b9e6 YM |
1184 | u64 tx_pause_frames; |
1185 | u64 tx_pfc_frames; | |
fe56b9e6 YM |
1186 | u64 brb_truncates; |
1187 | u64 brb_discards; | |
1188 | u64 rx_mac_bytes; | |
1189 | u64 rx_mac_uc_packets; | |
1190 | u64 rx_mac_mc_packets; | |
1191 | u64 rx_mac_bc_packets; | |
1192 | u64 rx_mac_frames_ok; | |
1193 | u64 tx_mac_bytes; | |
1194 | u64 tx_mac_uc_packets; | |
1195 | u64 tx_mac_mc_packets; | |
1196 | u64 tx_mac_bc_packets; | |
1197 | u64 tx_mac_ctrl_frames; | |
32d26a68 | 1198 | u64 link_change_count; |
fe56b9e6 YM |
1199 | }; |
1200 | ||
9c79ddaa MY |
1201 | struct qed_eth_stats_bb { |
1202 | u64 rx_1519_to_1522_byte_packets; | |
1203 | u64 rx_1519_to_2047_byte_packets; | |
1204 | u64 rx_2048_to_4095_byte_packets; | |
1205 | u64 rx_4096_to_9216_byte_packets; | |
1206 | u64 rx_9217_to_16383_byte_packets; | |
1207 | u64 tx_1519_to_2047_byte_packets; | |
1208 | u64 tx_2048_to_4095_byte_packets; | |
1209 | u64 tx_4096_to_9216_byte_packets; | |
1210 | u64 tx_9217_to_16383_byte_packets; | |
1211 | u64 tx_lpi_entry_count; | |
1212 | u64 tx_total_collisions; | |
1213 | }; | |
1214 | ||
1215 | struct qed_eth_stats_ah { | |
1216 | u64 rx_1519_to_max_byte_packets; | |
1217 | u64 tx_1519_to_max_byte_packets; | |
1218 | }; | |
1219 | ||
1220 | struct qed_eth_stats { | |
1221 | struct qed_eth_stats_common common; | |
1222 | ||
1223 | union { | |
1224 | struct qed_eth_stats_bb bb; | |
1225 | struct qed_eth_stats_ah ah; | |
1226 | }; | |
1227 | }; | |
1228 | ||
fe56b9e6 YM |
1229 | #define QED_SB_IDX 0x0002 |
1230 | ||
1231 | #define RX_PI 0 | |
1232 | #define TX_PI(tc) (RX_PI + 1 + tc) | |
1233 | ||
4ac801b7 | 1234 | struct qed_sb_cnt_info { |
726fdbe9 MY |
1235 | /* Original, current, and free SBs for PF */ |
1236 | int orig; | |
1237 | int cnt; | |
1238 | int free_cnt; | |
1239 | ||
1240 | /* Original, current and free SBS for child VFs */ | |
1241 | int iov_orig; | |
1242 | int iov_cnt; | |
1243 | int free_cnt_iov; | |
4ac801b7 YM |
1244 | }; |
1245 | ||
fe56b9e6 YM |
1246 | static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info) |
1247 | { | |
1248 | u32 prod = 0; | |
1249 | u16 rc = 0; | |
1250 | ||
1251 | prod = le32_to_cpu(sb_info->sb_virt->prod_index) & | |
21dd79e8 | 1252 | STATUS_BLOCK_E4_PROD_INDEX_MASK; |
fe56b9e6 YM |
1253 | if (sb_info->sb_ack != prod) { |
1254 | sb_info->sb_ack = prod; | |
1255 | rc |= QED_SB_IDX; | |
1256 | } | |
1257 | ||
1258 | /* Let SB update */ | |
1259 | mmiowb(); | |
1260 | return rc; | |
1261 | } | |
1262 | ||
1263 | /** | |
1264 | * | |
1265 | * @brief This function creates an update command for interrupts that is | |
1266 | * written to the IGU. | |
1267 | * | |
1268 | * @param sb_info - This is the structure allocated and | |
1269 | * initialized per status block. Assumption is | |
1270 | * that it was initialized using qed_sb_init | |
1271 | * @param int_cmd - Enable/Disable/Nop | |
1272 | * @param upd_flg - whether igu consumer should be | |
1273 | * updated. | |
1274 | * | |
1275 | * @return inline void | |
1276 | */ | |
1277 | static inline void qed_sb_ack(struct qed_sb_info *sb_info, | |
1278 | enum igu_int_cmd int_cmd, | |
1279 | u8 upd_flg) | |
1280 | { | |
1281 | struct igu_prod_cons_update igu_ack = { 0 }; | |
1282 | ||
1283 | igu_ack.sb_id_and_flags = | |
1284 | ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) | | |
1285 | (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) | | |
1286 | (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) | | |
1287 | (IGU_SEG_ACCESS_REG << | |
1288 | IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT)); | |
1289 | ||
1290 | DIRECT_REG_WR(sb_info->igu_addr, igu_ack.sb_id_and_flags); | |
1291 | ||
1292 | /* Both segments (interrupts & acks) are written to same place address; | |
1293 | * Need to guarantee all commands will be received (in-order) by HW. | |
1294 | */ | |
1295 | mmiowb(); | |
1296 | barrier(); | |
1297 | } | |
1298 | ||
1299 | static inline void __internal_ram_wr(void *p_hwfn, | |
1300 | void __iomem *addr, | |
1301 | int size, | |
1302 | u32 *data) | |
1303 | ||
1304 | { | |
1305 | unsigned int i; | |
1306 | ||
1307 | for (i = 0; i < size / sizeof(*data); i++) | |
1308 | DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]); | |
1309 | } | |
1310 | ||
1311 | static inline void internal_ram_wr(void __iomem *addr, | |
1312 | int size, | |
1313 | u32 *data) | |
1314 | { | |
1315 | __internal_ram_wr(NULL, addr, size, data); | |
1316 | } | |
1317 | ||
8c5ebd0c SRK |
1318 | enum qed_rss_caps { |
1319 | QED_RSS_IPV4 = 0x1, | |
1320 | QED_RSS_IPV6 = 0x2, | |
1321 | QED_RSS_IPV4_TCP = 0x4, | |
1322 | QED_RSS_IPV6_TCP = 0x8, | |
1323 | QED_RSS_IPV4_UDP = 0x10, | |
1324 | QED_RSS_IPV6_UDP = 0x20, | |
1325 | }; | |
1326 | ||
1327 | #define QED_RSS_IND_TABLE_SIZE 128 | |
1328 | #define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */ | |
fe56b9e6 | 1329 | #endif |