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Merge tag 'gvt-fixes-2019-11-12' of https://github.com/intel/gvt-linux into drm-intel...
[linux-2.6-block.git] / include / linux / qed / qed_if.h
CommitLineData
fe56b9e6 1/* QLogic qed NIC Driver
e8f1cb50 2 * Copyright (c) 2015-2017 QLogic Corporation
fe56b9e6 3 *
e8f1cb50
MY		 4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
fe56b9e6 9 *
e8f1cb50
MY		 10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
fe56b9e6
YM		 31 */
32
33#ifndef _QED_IF_H
34#define _QED_IF_H
35
36#include <linux/types.h>
37#include <linux/interrupt.h>
38#include <linux/netdevice.h>
39#include <linux/pci.h>
40#include <linux/skbuff.h>
fe56b9e6
YM		 41#include <asm/byteorder.h>
42#include <linux/io.h>
43#include <linux/compiler.h>
44#include <linux/kernel.h>
45#include <linux/list.h>
46#include <linux/slab.h>
47#include <linux/qed/common_hsi.h>
48#include <linux/qed/qed_chain.h>
36907cd5 49#include <linux/io-64-nonatomic-lo-hi.h>
fe56b9e6 50
39651abd
SRK		 51enum dcbx_protocol_type {
52 DCBX_PROTOCOL_ISCSI,
53 DCBX_PROTOCOL_FCOE,
54 DCBX_PROTOCOL_ROCE,
55 DCBX_PROTOCOL_ROCE_V2,
56 DCBX_PROTOCOL_ETH,
57 DCBX_MAX_PROTOCOL_TYPE
58};
59
51ff1725
RA		 60#define QED_ROCE_PROTOCOL_INDEX (3)
61
6ad8c632
SRK		 62#define QED_LLDP_CHASSIS_ID_STAT_LEN 4
63#define QED_LLDP_PORT_ID_STAT_LEN 4
64#define QED_DCBX_MAX_APP_PROTOCOL 32
65#define QED_MAX_PFC_PRIORITIES 8
66#define QED_DCBX_DSCP_SIZE 64
67
68struct qed_dcbx_lldp_remote {
69 u32 peer_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
70 u32 peer_port_id[QED_LLDP_PORT_ID_STAT_LEN];
71 bool enable_rx;
72 bool enable_tx;
73 u32 tx_interval;
74 u32 max_credit;
75};
76
77struct qed_dcbx_lldp_local {
78 u32 local_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
79 u32 local_port_id[QED_LLDP_PORT_ID_STAT_LEN];
80};
81
82struct qed_dcbx_app_prio {
83 u8 roce;
84 u8 roce_v2;
85 u8 fcoe;
86 u8 iscsi;
87 u8 eth;
88};
89
90struct qed_dbcx_pfc_params {
91 bool willing;
92 bool enabled;
93 u8 prio[QED_MAX_PFC_PRIORITIES];
94 u8 max_tc;
95};
96
59bcb797
SRK		 97enum qed_dcbx_sf_ieee_type {
98 QED_DCBX_SF_IEEE_ETHTYPE,
99 QED_DCBX_SF_IEEE_TCP_PORT,
100 QED_DCBX_SF_IEEE_UDP_PORT,
101 QED_DCBX_SF_IEEE_TCP_UDP_PORT
102};
103
6ad8c632
SRK		 104struct qed_app_entry {
105 bool ethtype;
59bcb797 106 enum qed_dcbx_sf_ieee_type sf_ieee;
6ad8c632
SRK		 107 bool enabled;
108 u8 prio;
109 u16 proto_id;
110 enum dcbx_protocol_type proto_type;
111};
112
113struct qed_dcbx_params {
114 struct qed_app_entry app_entry[QED_DCBX_MAX_APP_PROTOCOL];
115 u16 num_app_entries;
116 bool app_willing;
117 bool app_valid;
118 bool app_error;
119 bool ets_willing;
120 bool ets_enabled;
121 bool ets_cbs;
122 bool valid;
123 u8 ets_pri_tc_tbl[QED_MAX_PFC_PRIORITIES];
124 u8 ets_tc_bw_tbl[QED_MAX_PFC_PRIORITIES];
125 u8 ets_tc_tsa_tbl[QED_MAX_PFC_PRIORITIES];
126 struct qed_dbcx_pfc_params pfc;
127 u8 max_ets_tc;
128};
129
130struct qed_dcbx_admin_params {
131 struct qed_dcbx_params params;
132 bool valid;
133};
134
135struct qed_dcbx_remote_params {
136 struct qed_dcbx_params params;
137 bool valid;
138};
139
140struct qed_dcbx_operational_params {
141 struct qed_dcbx_app_prio app_prio;
142 struct qed_dcbx_params params;
143 bool valid;
144 bool enabled;
145 bool ieee;
146 bool cee;
49632b58 147 bool local;
6ad8c632
SRK		 148 u32 err;
149};
150
151struct qed_dcbx_get {
152 struct qed_dcbx_operational_params operational;
153 struct qed_dcbx_lldp_remote lldp_remote;
154 struct qed_dcbx_lldp_local lldp_local;
155 struct qed_dcbx_remote_params remote;
156 struct qed_dcbx_admin_params local;
157};
6ad8c632 158
20675b37
MY		 159enum qed_nvm_images {
160 QED_NVM_IMAGE_ISCSI_CFG,
161 QED_NVM_IMAGE_FCOE_CFG,
1ac4329a
DB		 162 QED_NVM_IMAGE_NVM_CFG1,
163 QED_NVM_IMAGE_DEFAULT_CFG,
164 QED_NVM_IMAGE_NVM_META,
20675b37
MY		 165};
166
645874e5
SRK		 167struct qed_link_eee_params {
168 u32 tx_lpi_timer;
169#define QED_EEE_1G_ADV BIT(0)
170#define QED_EEE_10G_ADV BIT(1)
171
172 /* Capabilities are represented using QED_EEE_*_ADV values */
173 u8 adv_caps;
174 u8 lp_adv_caps;
175 bool enable;
176 bool tx_lpi_enable;
177};
178
91420b83
SK		 179enum qed_led_mode {
180 QED_LED_MODE_OFF,
181 QED_LED_MODE_ON,
182 QED_LED_MODE_RESTORE
183};
184
2528c389
SRK		 185struct qed_mfw_tlv_eth {
186 u16 lso_maxoff_size;
187 bool lso_maxoff_size_set;
188 u16 lso_minseg_size;
189 bool lso_minseg_size_set;
190 u8 prom_mode;
191 bool prom_mode_set;
192 u16 tx_descr_size;
193 bool tx_descr_size_set;
194 u16 rx_descr_size;
195 bool rx_descr_size_set;
196 u16 netq_count;
197 bool netq_count_set;
198 u32 tcp4_offloads;
199 bool tcp4_offloads_set;
200 u32 tcp6_offloads;
201 bool tcp6_offloads_set;
202 u16 tx_descr_qdepth;
203 bool tx_descr_qdepth_set;
204 u16 rx_descr_qdepth;
205 bool rx_descr_qdepth_set;
206 u8 iov_offload;
207#define QED_MFW_TLV_IOV_OFFLOAD_NONE (0)
208#define QED_MFW_TLV_IOV_OFFLOAD_MULTIQUEUE (1)
209#define QED_MFW_TLV_IOV_OFFLOAD_VEB (2)
210#define QED_MFW_TLV_IOV_OFFLOAD_VEPA (3)
211 bool iov_offload_set;
212 u8 txqs_empty;
213 bool txqs_empty_set;
214 u8 rxqs_empty;
215 bool rxqs_empty_set;
216 u8 num_txqs_full;
217 bool num_txqs_full_set;
218 u8 num_rxqs_full;
219 bool num_rxqs_full_set;
220};
221
f240b688
SRK		 222#define QED_MFW_TLV_TIME_SIZE 14
223struct qed_mfw_tlv_time {
224 bool b_set;
225 u8 month;
226 u8 day;
227 u8 hour;
228 u8 min;
229 u16 msec;
230 u16 usec;
231};
232
233struct qed_mfw_tlv_fcoe {
234 u8 scsi_timeout;
235 bool scsi_timeout_set;
236 u32 rt_tov;
237 bool rt_tov_set;
238 u32 ra_tov;
239 bool ra_tov_set;
240 u32 ed_tov;
241 bool ed_tov_set;
242 u32 cr_tov;
243 bool cr_tov_set;
244 u8 boot_type;
245 bool boot_type_set;
246 u8 npiv_state;
247 bool npiv_state_set;
248 u32 num_npiv_ids;
249 bool num_npiv_ids_set;
250 u8 switch_name[8];
251 bool switch_name_set;
252 u16 switch_portnum;
253 bool switch_portnum_set;
254 u8 switch_portid[3];
255 bool switch_portid_set;
256 u8 vendor_name[8];
257 bool vendor_name_set;
258 u8 switch_model[8];
259 bool switch_model_set;
260 u8 switch_fw_version[8];
261 bool switch_fw_version_set;
262 u8 qos_pri;
263 bool qos_pri_set;
264 u8 port_alias[3];
265 bool port_alias_set;
266 u8 port_state;
267#define QED_MFW_TLV_PORT_STATE_OFFLINE (0)
268#define QED_MFW_TLV_PORT_STATE_LOOP (1)
269#define QED_MFW_TLV_PORT_STATE_P2P (2)
270#define QED_MFW_TLV_PORT_STATE_FABRIC (3)
271 bool port_state_set;
272 u16 fip_tx_descr_size;
273 bool fip_tx_descr_size_set;
274 u16 fip_rx_descr_size;
275 bool fip_rx_descr_size_set;
276 u16 link_failures;
277 bool link_failures_set;
278 u8 fcoe_boot_progress;
279 bool fcoe_boot_progress_set;
280 u64 rx_bcast;
281 bool rx_bcast_set;
282 u64 tx_bcast;
283 bool tx_bcast_set;
284 u16 fcoe_txq_depth;
285 bool fcoe_txq_depth_set;
286 u16 fcoe_rxq_depth;
287 bool fcoe_rxq_depth_set;
288 u64 fcoe_rx_frames;
289 bool fcoe_rx_frames_set;
290 u64 fcoe_rx_bytes;
291 bool fcoe_rx_bytes_set;
292 u64 fcoe_tx_frames;
293 bool fcoe_tx_frames_set;
294 u64 fcoe_tx_bytes;
295 bool fcoe_tx_bytes_set;
296 u16 crc_count;
297 bool crc_count_set;
298 u32 crc_err_src_fcid[5];
299 bool crc_err_src_fcid_set[5];
300 struct qed_mfw_tlv_time crc_err[5];
301 u16 losync_err;
302 bool losync_err_set;
303 u16 losig_err;
304 bool losig_err_set;
305 u16 primtive_err;
306 bool primtive_err_set;
307 u16 disparity_err;
308 bool disparity_err_set;
309 u16 code_violation_err;
310 bool code_violation_err_set;
311 u32 flogi_param[4];
312 bool flogi_param_set[4];
313 struct qed_mfw_tlv_time flogi_tstamp;
314 u32 flogi_acc_param[4];
315 bool flogi_acc_param_set[4];
316 struct qed_mfw_tlv_time flogi_acc_tstamp;
317 u32 flogi_rjt;
318 bool flogi_rjt_set;
319 struct qed_mfw_tlv_time flogi_rjt_tstamp;
320 u32 fdiscs;
321 bool fdiscs_set;
322 u8 fdisc_acc;
323 bool fdisc_acc_set;
324 u8 fdisc_rjt;
325 bool fdisc_rjt_set;
326 u8 plogi;
327 bool plogi_set;
328 u8 plogi_acc;
329 bool plogi_acc_set;
330 u8 plogi_rjt;
331 bool plogi_rjt_set;
332 u32 plogi_dst_fcid[5];
333 bool plogi_dst_fcid_set[5];
334 struct qed_mfw_tlv_time plogi_tstamp[5];
335 u32 plogi_acc_src_fcid[5];
336 bool plogi_acc_src_fcid_set[5];
337 struct qed_mfw_tlv_time plogi_acc_tstamp[5];
338 u8 tx_plogos;
339 bool tx_plogos_set;
340 u8 plogo_acc;
341 bool plogo_acc_set;
342 u8 plogo_rjt;
343 bool plogo_rjt_set;
344 u32 plogo_src_fcid[5];
345 bool plogo_src_fcid_set[5];
346 struct qed_mfw_tlv_time plogo_tstamp[5];
347 u8 rx_logos;
348 bool rx_logos_set;
349 u8 tx_accs;
350 bool tx_accs_set;
351 u8 tx_prlis;
352 bool tx_prlis_set;
353 u8 rx_accs;
354 bool rx_accs_set;
355 u8 tx_abts;
356 bool tx_abts_set;
357 u8 rx_abts_acc;
358 bool rx_abts_acc_set;
359 u8 rx_abts_rjt;
360 bool rx_abts_rjt_set;
361 u32 abts_dst_fcid[5];
362 bool abts_dst_fcid_set[5];
363 struct qed_mfw_tlv_time abts_tstamp[5];
364 u8 rx_rscn;
365 bool rx_rscn_set;
366 u32 rx_rscn_nport[4];
367 bool rx_rscn_nport_set[4];
368 u8 tx_lun_rst;
369 bool tx_lun_rst_set;
370 u8 abort_task_sets;
371 bool abort_task_sets_set;
372 u8 tx_tprlos;
373 bool tx_tprlos_set;
374 u8 tx_nos;
375 bool tx_nos_set;
376 u8 rx_nos;
377 bool rx_nos_set;
378 u8 ols;
379 bool ols_set;
380 u8 lr;
381 bool lr_set;
382 u8 lrr;
383 bool lrr_set;
384 u8 tx_lip;
385 bool tx_lip_set;
386 u8 rx_lip;
387 bool rx_lip_set;
388 u8 eofa;
389 bool eofa_set;
390 u8 eofni;
391 bool eofni_set;
392 u8 scsi_chks;
393 bool scsi_chks_set;
394 u8 scsi_cond_met;
395 bool scsi_cond_met_set;
396 u8 scsi_busy;
397 bool scsi_busy_set;
398 u8 scsi_inter;
399 bool scsi_inter_set;
400 u8 scsi_inter_cond_met;
401 bool scsi_inter_cond_met_set;
402 u8 scsi_rsv_conflicts;
403 bool scsi_rsv_conflicts_set;
404 u8 scsi_tsk_full;
405 bool scsi_tsk_full_set;
406 u8 scsi_aca_active;
407 bool scsi_aca_active_set;
408 u8 scsi_tsk_abort;
409 bool scsi_tsk_abort_set;
410 u32 scsi_rx_chk[5];
411 bool scsi_rx_chk_set[5];
412 struct qed_mfw_tlv_time scsi_chk_tstamp[5];
413};
414
77a509e4
SRK		 415struct qed_mfw_tlv_iscsi {
416 u8 target_llmnr;
417 bool target_llmnr_set;
418 u8 header_digest;
419 bool header_digest_set;
420 u8 data_digest;
421 bool data_digest_set;
422 u8 auth_method;
423#define QED_MFW_TLV_AUTH_METHOD_NONE (1)
424#define QED_MFW_TLV_AUTH_METHOD_CHAP (2)
425#define QED_MFW_TLV_AUTH_METHOD_MUTUAL_CHAP (3)
426 bool auth_method_set;
427 u16 boot_taget_portal;
428 bool boot_taget_portal_set;
429 u16 frame_size;
430 bool frame_size_set;
431 u16 tx_desc_size;
432 bool tx_desc_size_set;
433 u16 rx_desc_size;
434 bool rx_desc_size_set;
435 u8 boot_progress;
436 bool boot_progress_set;
437 u16 tx_desc_qdepth;
438 bool tx_desc_qdepth_set;
439 u16 rx_desc_qdepth;
440 bool rx_desc_qdepth_set;
441 u64 rx_frames;
442 bool rx_frames_set;
443 u64 rx_bytes;
444 bool rx_bytes_set;
445 u64 tx_frames;
446 bool tx_frames_set;
447 u64 tx_bytes;
448 bool tx_bytes_set;
449};
450
36907cd5
AE		 451enum qed_db_rec_width {
452 DB_REC_WIDTH_32B,
453 DB_REC_WIDTH_64B,
454};
455
456enum qed_db_rec_space {
457 DB_REC_KERNEL,
458 DB_REC_USER,
459};
460
fe56b9e6
YM		 461#define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \
462 (void __iomem *)(reg_addr))
463
464#define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr))
465
36907cd5
AE		 466#define DIRECT_REG_WR64(reg_addr, val) writeq((u32)val, \
467 (void __iomem *)(reg_addr))
468
41822878 469#define QED_COALESCE_MAX 0x1FF
0e191827 470#define QED_DEFAULT_RX_USECS 12
bf5a94bf 471#define QED_DEFAULT_TX_USECS 48
fe56b9e6
YM		 472
473/* forward */
474struct qed_dev;
475
476struct qed_eth_pf_params {
477 /* The following parameters are used during HW-init
478 * and these parameters need to be passed as arguments
479 * to update_pf_params routine invoked before slowpath start
480 */
481 u16 num_cons;
d51e4af5 482
08bc8f15
MY		 483 /* per-VF number of CIDs */
484 u8 num_vf_cons;
485#define ETH_PF_PARAMS_VF_CONS_DEFAULT (32)
486
d51e4af5
CM		 487 /* To enable arfs, previous to HW-init a positive number needs to be
488 * set [as filters require allocated searcher ILT memory].
489 * This will set the maximal number of configured steering-filters.
490 */
491 u32 num_arfs_filters;
fe56b9e6
YM		 492};
493
1e128c81
AE		 494struct qed_fcoe_pf_params {
495 /* The following parameters are used during protocol-init */
496 u64 glbl_q_params_addr;
497 u64 bdq_pbl_base_addr[2];
498
499 /* The following parameters are used during HW-init
500 * and these parameters need to be passed as arguments
501 * to update_pf_params routine invoked before slowpath start
502 */
503 u16 num_cons;
504 u16 num_tasks;
505
506 /* The following parameters are used during protocol-init */
507 u16 sq_num_pbl_pages;
508
509 u16 cq_num_entries;
510 u16 cmdq_num_entries;
511 u16 rq_buffer_log_size;
512 u16 mtu;
513 u16 dummy_icid;
514 u16 bdq_xoff_threshold[2];
515 u16 bdq_xon_threshold[2];
516 u16 rq_buffer_size;
517 u8 num_cqs; /* num of global CQs */
518 u8 log_page_size;
519 u8 gl_rq_pi;
520 u8 gl_cmd_pi;
521 u8 debug_mode;
522 u8 is_target;
523 u8 bdq_pbl_num_entries[2];
524};
525
c5ac9319
YM		 526/* Most of the the parameters below are described in the FW iSCSI / TCP HSI */
527struct qed_iscsi_pf_params {
528 u64 glbl_q_params_addr;
da090917 529 u64 bdq_pbl_base_addr[3];
c5ac9319
YM		 530 u16 cq_num_entries;
531 u16 cmdq_num_entries;
fc831825 532 u32 two_msl_timer;
c5ac9319 533 u16 tx_sws_timer;
c5ac9319
YM		 534
535 /* The following parameters are used during HW-init
536 * and these parameters need to be passed as arguments
537 * to update_pf_params routine invoked before slowpath start
538 */
539 u16 num_cons;
540 u16 num_tasks;
541
542 /* The following parameters are used during protocol-init */
543 u16 half_way_close_timeout;
da090917
TT		 544 u16 bdq_xoff_threshold[3];
545 u16 bdq_xon_threshold[3];
c5ac9319
YM		 546 u16 cmdq_xoff_threshold;
547 u16 cmdq_xon_threshold;
548 u16 rq_buffer_size;
549
550 u8 num_sq_pages_in_ring;
551 u8 num_r2tq_pages_in_ring;
552 u8 num_uhq_pages_in_ring;
553 u8 num_queues;
554 u8 log_page_size;
555 u8 rqe_log_size;
556 u8 max_fin_rt;
557 u8 gl_rq_pi;
558 u8 gl_cmd_pi;
559 u8 debug_mode;
560 u8 ll2_ooo_queue_id;
c5ac9319
YM		 561
562 u8 is_target;
da090917
TT		 563 u8 is_soc_en;
564 u8 soc_num_of_blocks_log;
565 u8 bdq_pbl_num_entries[3];
c5ac9319
YM		 566};
567
568struct qed_rdma_pf_params {
569 /* Supplied to QED during resource allocation (may affect the ILT and
570 * the doorbell BAR).
571 */
572 u32 min_dpis; /* number of requested DPIs */
c5ac9319
YM		 573 u32 num_qps; /* number of requested Queue Pairs */
574 u32 num_srqs; /* number of requested SRQ */
575 u8 roce_edpm_mode; /* see QED_ROCE_EDPM_MODE_ENABLE */
576 u8 gl_pi; /* protocol index */
577
578 /* Will allocate rate limiters to be used with QPs */
579 u8 enable_dcqcn;
580};
581
fe56b9e6
YM		 582struct qed_pf_params {
583 struct qed_eth_pf_params eth_pf_params;
1e128c81 584 struct qed_fcoe_pf_params fcoe_pf_params;
c5ac9319
YM		 585 struct qed_iscsi_pf_params iscsi_pf_params;
586 struct qed_rdma_pf_params rdma_pf_params;
fe56b9e6
YM		 587};
588
589enum qed_int_mode {
590 QED_INT_MODE_INTA,
591 QED_INT_MODE_MSIX,
592 QED_INT_MODE_MSI,
593 QED_INT_MODE_POLL,
594};
595
596struct qed_sb_info {
21dd79e8 597 struct status_block_e4 *sb_virt;
a2e7699e
TT		 598 dma_addr_t sb_phys;
599 u32 sb_ack; /* Last given ack */
600 u16 igu_sb_id;
601 void __iomem *igu_addr;
602 u8 flags;
603#define QED_SB_INFO_INIT 0x1
604#define QED_SB_INFO_SETUP 0x2
605
606 struct qed_dev *cdev;
fe56b9e6
YM		 607};
608
9c79ddaa
MY		 609enum qed_dev_type {
610 QED_DEV_TYPE_BB,
611 QED_DEV_TYPE_AH,
612};
613
fe56b9e6
YM		 614struct qed_dev_info {
615 unsigned long pci_mem_start;
616 unsigned long pci_mem_end;
617 unsigned int pci_irq;
618 u8 num_hwfns;
619
620 u8 hw_mac[ETH_ALEN];
fe56b9e6
YM		 621
622 /* FW version */
623 u16 fw_major;
624 u16 fw_minor;
625 u16 fw_rev;
626 u16 fw_eng;
627
628 /* MFW version */
629 u32 mfw_rev;
ae33666a
TT		 630#define QED_MFW_VERSION_0_MASK 0x000000FF
631#define QED_MFW_VERSION_0_OFFSET 0
632#define QED_MFW_VERSION_1_MASK 0x0000FF00
633#define QED_MFW_VERSION_1_OFFSET 8
634#define QED_MFW_VERSION_2_MASK 0x00FF0000
635#define QED_MFW_VERSION_2_OFFSET 16
636#define QED_MFW_VERSION_3_MASK 0xFF000000
637#define QED_MFW_VERSION_3_OFFSET 24
fe56b9e6
YM		 638
639 u32 flash_size;
0bc5fe85 640 bool b_inter_pf_switch;
831bfb0e 641 bool tx_switching;
cee9fbd8 642 bool rdma_supported;
0fefbfba 643 u16 mtu;
14d39648
MY		 644
645 bool wol_support;
df9c716d 646 bool smart_an;
9c79ddaa 647
ae33666a
TT		 648 /* MBI version */
649 u32 mbi_version;
650#define QED_MBI_VERSION_0_MASK 0x000000FF
651#define QED_MBI_VERSION_0_OFFSET 0
652#define QED_MBI_VERSION_1_MASK 0x0000FF00
653#define QED_MBI_VERSION_1_OFFSET 8
654#define QED_MBI_VERSION_2_MASK 0x00FF0000
655#define QED_MBI_VERSION_2_OFFSET 16
656
9c79ddaa 657 enum qed_dev_type dev_type;
19489c7f
CM		 658
659 /* Output parameters for qede */
660 bool vxlan_enable;
661 bool gre_enable;
662 bool geneve_enable;
3c5da942
MY		 663
664 u8 abs_pf_id;
fe56b9e6
YM		 665};
666
667enum qed_sb_type {
668 QED_SB_TYPE_L2_QUEUE,
51ff1725 669 QED_SB_TYPE_CNQ,
fc831825 670 QED_SB_TYPE_STORAGE,
fe56b9e6
YM		 671};
672
673enum qed_protocol {
674 QED_PROTOCOL_ETH,
c5ac9319 675 QED_PROTOCOL_ISCSI,
1e128c81 676 QED_PROTOCOL_FCOE,
fe56b9e6
YM		 677};
678
054c67d1
SRK		 679enum qed_link_mode_bits {
680 QED_LM_FIBRE_BIT = BIT(0),
681 QED_LM_Autoneg_BIT = BIT(1),
682 QED_LM_Asym_Pause_BIT = BIT(2),
683 QED_LM_Pause_BIT = BIT(3),
c56a8be7
RV		 684 QED_LM_1000baseT_Full_BIT = BIT(4),
685 QED_LM_10000baseT_Full_BIT = BIT(5),
054c67d1 686 QED_LM_10000baseKR_Full_BIT = BIT(6),
5bf0961c
SRK		 687 QED_LM_20000baseKR2_Full_BIT = BIT(7),
688 QED_LM_25000baseKR_Full_BIT = BIT(8),
689 QED_LM_40000baseLR4_Full_BIT = BIT(9),
690 QED_LM_50000baseKR2_Full_BIT = BIT(10),
691 QED_LM_100000baseKR4_Full_BIT = BIT(11),
5e6d9fc7 692 QED_LM_TP_BIT = BIT(12),
c56a8be7
RV		 693 QED_LM_Backplane_BIT = BIT(13),
694 QED_LM_1000baseKX_Full_BIT = BIT(14),
695 QED_LM_10000baseKX4_Full_BIT = BIT(15),
696 QED_LM_10000baseR_FEC_BIT = BIT(16),
697 QED_LM_40000baseKR4_Full_BIT = BIT(17),
698 QED_LM_40000baseCR4_Full_BIT = BIT(18),
699 QED_LM_40000baseSR4_Full_BIT = BIT(19),
700 QED_LM_25000baseCR_Full_BIT = BIT(20),
701 QED_LM_25000baseSR_Full_BIT = BIT(21),
702 QED_LM_50000baseCR2_Full_BIT = BIT(22),
703 QED_LM_100000baseSR4_Full_BIT = BIT(23),
704 QED_LM_100000baseCR4_Full_BIT = BIT(24),
705 QED_LM_100000baseLR4_ER4_Full_BIT = BIT(25),
706 QED_LM_50000baseSR2_Full_BIT = BIT(26),
707 QED_LM_1000baseX_Full_BIT = BIT(27),
708 QED_LM_10000baseCR_Full_BIT = BIT(28),
709 QED_LM_10000baseSR_Full_BIT = BIT(29),
710 QED_LM_10000baseLR_Full_BIT = BIT(30),
711 QED_LM_10000baseLRM_Full_BIT = BIT(31),
712 QED_LM_COUNT = 32
054c67d1
SRK		 713};
714
fe56b9e6
YM		 715struct qed_link_params {
716 bool link_up;
717
718#define QED_LINK_OVERRIDE_SPEED_AUTONEG BIT(0)
719#define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS BIT(1)
720#define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED BIT(2)
721#define QED_LINK_OVERRIDE_PAUSE_CONFIG BIT(3)
03dc76ca 722#define QED_LINK_OVERRIDE_LOOPBACK_MODE BIT(4)
645874e5 723#define QED_LINK_OVERRIDE_EEE_CONFIG BIT(5)
fe56b9e6
YM		 724 u32 override_flags;
725 bool autoneg;
726 u32 adv_speeds;
727 u32 forced_speed;
728#define QED_LINK_PAUSE_AUTONEG_ENABLE BIT(0)
729#define QED_LINK_PAUSE_RX_ENABLE BIT(1)
730#define QED_LINK_PAUSE_TX_ENABLE BIT(2)
731 u32 pause_config;
03dc76ca
SRK		 732#define QED_LINK_LOOPBACK_NONE BIT(0)
733#define QED_LINK_LOOPBACK_INT_PHY BIT(1)
734#define QED_LINK_LOOPBACK_EXT_PHY BIT(2)
735#define QED_LINK_LOOPBACK_EXT BIT(3)
736#define QED_LINK_LOOPBACK_MAC BIT(4)
737 u32 loopback_mode;
645874e5 738 struct qed_link_eee_params eee;
fe56b9e6
YM		 739};
740
741struct qed_link_output {
742 bool link_up;
743
d194fd26
YM		 744 /* In QED_LM_* defs */
745 u32 supported_caps;
746 u32 advertised_caps;
747 u32 lp_caps;
748
fe56b9e6
YM		 749 u32 speed; /* In Mb/s */
750 u8 duplex; /* In DUPLEX defs */
751 u8 port; /* In PORT defs */
752 bool autoneg;
753 u32 pause_config;
645874e5
SRK		 754
755 /* EEE - capability & param */
756 bool eee_supported;
757 bool eee_active;
758 u8 sup_caps;
759 struct qed_link_eee_params eee;
fe56b9e6
YM		 760};
761
1408cc1f
YM		 762struct qed_probe_params {
763 enum qed_protocol protocol;
764 u32 dp_module;
765 u8 dp_level;
766 bool is_vf;
64515dc8 767 bool recov_in_prog;
1408cc1f
YM		 768};
769
fe56b9e6
YM		 770#define QED_DRV_VER_STR_SIZE 12
771struct qed_slowpath_params {
772 u32 int_mode;
773 u8 drv_major;
774 u8 drv_minor;
775 u8 drv_rev;
776 u8 drv_eng;
777 u8 name[QED_DRV_VER_STR_SIZE];
778};
779
780#define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */
781
782struct qed_int_info {
783 struct msix_entry *msix;
784 u8 msix_cnt;
785
786 /* This should be updated by the protocol driver */
787 u8 used_cnt;
788};
789
59ccf86f
SRK		 790struct qed_generic_tlvs {
791#define QED_TLV_IP_CSUM BIT(0)
792#define QED_TLV_LSO BIT(1)
793 u16 feat_flags;
794#define QED_TLV_MAC_COUNT 3
795 u8 mac[QED_TLV_MAC_COUNT][ETH_ALEN];
796};
797
b51dab46
SRK		 798#define QED_I2C_DEV_ADDR_A0 0xA0
799#define QED_I2C_DEV_ADDR_A2 0xA2
800
3a69cae8
SRK		 801#define QED_NVM_SIGNATURE 0x12435687
802
803enum qed_nvm_flash_cmd {
804 QED_NVM_FLASH_CMD_FILE_DATA = 0x2,
805 QED_NVM_FLASH_CMD_FILE_START = 0x3,
806 QED_NVM_FLASH_CMD_NVM_CHANGE = 0x4,
0dabbe1b 807 QED_NVM_FLASH_CMD_NVM_CFG_ID = 0x5,
3a69cae8
SRK		 808 QED_NVM_FLASH_CMD_NVM_MAX,
809};
810
fe56b9e6 811struct qed_common_cb_ops {
d51e4af5 812 void (*arfs_filter_op)(void *dev, void *fltr, u8 fw_rc);
fe56b9e6
YM		 813 void (*link_update)(void *dev,
814 struct qed_link_output *link);
64515dc8 815 void (*schedule_recovery_handler)(void *dev);
1e128c81 816 void (*dcbx_aen)(void *dev, struct qed_dcbx_get *get, u32 mib_type);
59ccf86f
SRK		 817 void (*get_generic_tlv_data)(void *dev, struct qed_generic_tlvs *data);
818 void (*get_protocol_tlv_data)(void *dev, void *data);
fe56b9e6
YM		 819};
820
03dc76ca
SRK		 821struct qed_selftest_ops {
822/**
823 * @brief selftest_interrupt - Perform interrupt test
824 *
825 * @param cdev
826 *
827 * @return 0 on success, error otherwise.
828 */
829 int (*selftest_interrupt)(struct qed_dev *cdev);
830
831/**
832 * @brief selftest_memory - Perform memory test
833 *
834 * @param cdev
835 *
836 * @return 0 on success, error otherwise.
837 */
838 int (*selftest_memory)(struct qed_dev *cdev);
839
840/**
841 * @brief selftest_register - Perform register test
842 *
843 * @param cdev
844 *
845 * @return 0 on success, error otherwise.
846 */
847 int (*selftest_register)(struct qed_dev *cdev);
848
849/**
850 * @brief selftest_clock - Perform clock test
851 *
852 * @param cdev
853 *
854 * @return 0 on success, error otherwise.
855 */
856 int (*selftest_clock)(struct qed_dev *cdev);
7a4b21b7
MY		 857
858/**
859 * @brief selftest_nvram - Perform nvram test
860 *
861 * @param cdev
862 *
863 * @return 0 on success, error otherwise.
864 */
865 int (*selftest_nvram) (struct qed_dev *cdev);
03dc76ca
SRK		 866};
867
fe56b9e6 868struct qed_common_ops {
03dc76ca
SRK		 869 struct qed_selftest_ops *selftest;
870
fe56b9e6 871 struct qed_dev* (*probe)(struct pci_dev *dev,
1408cc1f 872 struct qed_probe_params *params);
fe56b9e6
YM		 873
874 void (*remove)(struct qed_dev *cdev);
875
876 int (*set_power_state)(struct qed_dev *cdev,
877 pci_power_t state);
878
712c3cbf 879 void (*set_name) (struct qed_dev *cdev, char name[]);
fe56b9e6
YM		 880
881 /* Client drivers need to make this call before slowpath_start.
882 * PF params required for the call before slowpath_start is
883 * documented within the qed_pf_params structure definition.
884 */
885 void (*update_pf_params)(struct qed_dev *cdev,
886 struct qed_pf_params *params);
887 int (*slowpath_start)(struct qed_dev *cdev,
888 struct qed_slowpath_params *params);
889
890 int (*slowpath_stop)(struct qed_dev *cdev);
891
892 /* Requests to use `cnt' interrupts for fastpath.
893 * upon success, returns number of interrupts allocated for fastpath.
894 */
895 int (*set_fp_int)(struct qed_dev *cdev,
896 u16 cnt);
897
898 /* Fills `info' with pointers required for utilizing interrupts */
899 int (*get_fp_int)(struct qed_dev *cdev,
900 struct qed_int_info *info);
901
902 u32 (*sb_init)(struct qed_dev *cdev,
903 struct qed_sb_info *sb_info,
904 void *sb_virt_addr,
905 dma_addr_t sb_phy_addr,
906 u16 sb_id,
907 enum qed_sb_type type);
908
909 u32 (*sb_release)(struct qed_dev *cdev,
910 struct qed_sb_info *sb_info,
08eb1fb0
MK		 911 u16 sb_id,
912 enum qed_sb_type type);
fe56b9e6
YM		 913
914 void (*simd_handler_config)(struct qed_dev *cdev,
915 void *token,
916 int index,
917 void (*handler)(void *));
918
919 void (*simd_handler_clean)(struct qed_dev *cdev,
920 int index);
1e128c81
AE		 921 int (*dbg_grc)(struct qed_dev *cdev,
922 void *buffer, u32 *num_dumped_bytes);
923
924 int (*dbg_grc_size)(struct qed_dev *cdev);
fe7cd2bf 925
e0971c83
TT		 926 int (*dbg_all_data) (struct qed_dev *cdev, void *buffer);
927
928 int (*dbg_all_data_size) (struct qed_dev *cdev);
929
fe7cd2bf
YM		 930/**
931 * @brief can_link_change - can the instance change the link or not
932 *
933 * @param cdev
934 *
935 * @return true if link-change is allowed, false otherwise.
936 */
937 bool (*can_link_change)(struct qed_dev *cdev);
938
fe56b9e6
YM		 939/**
940 * @brief set_link - set links according to params
941 *
942 * @param cdev
943 * @param params - values used to override the default link configuration
944 *
945 * @return 0 on success, error otherwise.
946 */
947 int (*set_link)(struct qed_dev *cdev,
948 struct qed_link_params *params);
949
950/**
951 * @brief get_link - returns the current link state.
952 *
953 * @param cdev
954 * @param if_link - structure to be filled with current link configuration.
955 */
956 void (*get_link)(struct qed_dev *cdev,
957 struct qed_link_output *if_link);
958
959/**
960 * @brief - drains chip in case Tx completions fail to arrive due to pause.
961 *
962 * @param cdev
963 */
964 int (*drain)(struct qed_dev *cdev);
965
966/**
967 * @brief update_msglvl - update module debug level
968 *
969 * @param cdev
970 * @param dp_module
971 * @param dp_level
972 */
973 void (*update_msglvl)(struct qed_dev *cdev,
974 u32 dp_module,
975 u8 dp_level);
976
977 int (*chain_alloc)(struct qed_dev *cdev,
978 enum qed_chain_use_mode intended_use,
979 enum qed_chain_mode mode,
a91eb52a
YM		 980 enum qed_chain_cnt_type cnt_type,
981 u32 num_elems,
fe56b9e6 982 size_t elem_size,
1a4a6975
MY		 983 struct qed_chain *p_chain,
984 struct qed_chain_ext_pbl *ext_pbl);
fe56b9e6
YM		 985
986 void (*chain_free)(struct qed_dev *cdev,
987 struct qed_chain *p_chain);
91420b83 988
3a69cae8
SRK		 989/**
990 * @brief nvm_flash - Flash nvm data.
991 *
992 * @param cdev
993 * @param name - file containing the data
994 *
995 * @return 0 on success, error otherwise.
996 */
997 int (*nvm_flash)(struct qed_dev *cdev, const char *name);
998
20675b37
MY		 999/**
1000 * @brief nvm_get_image - reads an entire image from nvram
1001 *
1002 * @param cdev
1003 * @param type - type of the request nvram image
1004 * @param buf - preallocated buffer to fill with the image
1005 * @param len - length of the allocated buffer
1006 *
1007 * @return 0 on success, error otherwise
1008 */
1009 int (*nvm_get_image)(struct qed_dev *cdev,
1010 enum qed_nvm_images type, u8 *buf, u16 len);
1011
722003ac
SRK		 1012/**
1013 * @brief set_coalesce - Configure Rx coalesce value in usec
1014 *
1015 * @param cdev
1016 * @param rx_coal - Rx coalesce value in usec
1017 * @param tx_coal - Tx coalesce value in usec
1018 * @param qid - Queue index
1019 * @param sb_id - Status Block Id
1020 *
1021 * @return 0 on success, error otherwise.
1022 */
477f2d14
RV		 1023 int (*set_coalesce)(struct qed_dev *cdev,
1024 u16 rx_coal, u16 tx_coal, void *handle);
722003ac 1025
91420b83
SK		 1026/**
1027 * @brief set_led - Configure LED mode
1028 *
1029 * @param cdev
1030 * @param mode - LED mode
1031 *
1032 * @return 0 on success, error otherwise.
1033 */
1034 int (*set_led)(struct qed_dev *cdev,
1035 enum qed_led_mode mode);
0e1f1044
AE		 1036/**
1037 * @brief db_recovery_add - add doorbell information to the doorbell
1038 * recovery mechanism.
1039 *
1040 * @param cdev
1041 * @param db_addr - doorbell address
1042 * @param db_data - address of where db_data is stored
1043 * @param db_is_32b - doorbell is 32b pr 64b
1044 * @param db_is_user - doorbell recovery addresses are user or kernel space
1045 */
1046 int (*db_recovery_add)(struct qed_dev *cdev,
1047 void __iomem *db_addr,
1048 void *db_data,
1049 enum qed_db_rec_width db_width,
1050 enum qed_db_rec_space db_space);
1051
1052/**
1053 * @brief db_recovery_del - remove doorbell information from the doorbell
1054 * recovery mechanism. db_data serves as key (db_addr is not unique).
1055 *
1056 * @param cdev
1057 * @param db_addr - doorbell address
1058 * @param db_data - address where db_data is stored. Serves as key for the
1059 * entry to delete.
1060 */
1061 int (*db_recovery_del)(struct qed_dev *cdev,
1062 void __iomem *db_addr, void *db_data);
0fefbfba 1063
64515dc8
TT		 1064/**
1065 * @brief recovery_process - Trigger a recovery process
1066 *
1067 * @param cdev
1068 *
1069 * @return 0 on success, error otherwise.
1070 */
1071 int (*recovery_process)(struct qed_dev *cdev);
1072
1073/**
1074 * @brief recovery_prolog - Execute the prolog operations of a recovery process
1075 *
1076 * @param cdev
1077 *
1078 * @return 0 on success, error otherwise.
1079 */
1080 int (*recovery_prolog)(struct qed_dev *cdev);
1081
0fefbfba
SK		 1082/**
1083 * @brief update_drv_state - API to inform the change in the driver state.
1084 *
1085 * @param cdev
1086 * @param active
1087 *
1088 */
1089 int (*update_drv_state)(struct qed_dev *cdev, bool active);
1090
1091/**
1092 * @brief update_mac - API to inform the change in the mac address
1093 *
1094 * @param cdev
1095 * @param mac
1096 *
1097 */
1098 int (*update_mac)(struct qed_dev *cdev, u8 *mac);
1099
1100/**
1101 * @brief update_mtu - API to inform the change in the mtu
1102 *
1103 * @param cdev
1104 * @param mtu
1105 *
1106 */
1107 int (*update_mtu)(struct qed_dev *cdev, u16 mtu);
14d39648
MY		 1108
1109/**
1110 * @brief update_wol - update of changes in the WoL configuration
1111 *
1112 * @param cdev
1113 * @param enabled - true iff WoL should be enabled.
1114 */
1115 int (*update_wol) (struct qed_dev *cdev, bool enabled);
b51dab46
SRK		 1116
1117/**
1118 * @brief read_module_eeprom
1119 *
1120 * @param cdev
1121 * @param buf - buffer
1122 * @param dev_addr - PHY device memory region
1123 * @param offset - offset into eeprom contents to be read
1124 * @param len - buffer length, i.e., max bytes to be read
1125 */
1126 int (*read_module_eeprom)(struct qed_dev *cdev,
1127 char *buf, u8 dev_addr, u32 offset, u32 len);
08eb1fb0
MK		 1128
1129/**
1130 * @brief get_affin_hwfn_idx
1131 *
1132 * @param cdev
1133 */
1134 u8 (*get_affin_hwfn_idx)(struct qed_dev *cdev);
2d4c8495
SRK		 1135
1136/**
1137 * @brief read_nvm_cfg - Read NVM config attribute value.
1138 * @param cdev
1139 * @param buf - buffer
1140 * @param cmd - NVM CFG command id
1141 * @param entity_id - Entity id
1142 *
1143 */
1144 int (*read_nvm_cfg)(struct qed_dev *cdev, u8 **buf, u32 cmd,
1145 u32 entity_id);
9e54ba7c
SRK		 1146/**
1147 * @brief read_nvm_cfg - Read NVM config attribute value.
1148 * @param cdev
1149 * @param cmd - NVM CFG command id
1150 *
1151 * @return config id length, 0 on error.
1152 */
1153 int (*read_nvm_cfg_len)(struct qed_dev *cdev, u32 cmd);
3b86bd07
SRK		 1154
1155/**
1156 * @brief set_grc_config - Configure value for grc config id.
1157 * @param cdev
1158 * @param cfg_id - grc config id
1159 * @param val - grc config value
1160 *
1161 */
1162 int (*set_grc_config)(struct qed_dev *cdev, u32 cfg_id, u32 val);
fe56b9e6
YM		 1163};
1164
fe56b9e6
YM		 1165#define MASK_FIELD(_name, _value) \
1166 ((_value) &= (_name ## _MASK))
1167
1168#define FIELD_VALUE(_name, _value) \
1169 ((_value & _name ## _MASK) << _name ## _SHIFT)
1170
1171#define SET_FIELD(value, name, flag) \
1172 do { \
1173 (value) &= ~(name ## _MASK << name ## _SHIFT); \
1174 (value) |= (((u64)flag) << (name ## _SHIFT)); \
1175 } while (0)
1176
1177#define GET_FIELD(value, name) \
1178 (((value) >> (name ## _SHIFT)) & name ## _MASK)
1179
1180/* Debug print definitions */
9d7650c2
MY		 1181#define DP_ERR(cdev, fmt, ...) \
1182 do { \
1183 pr_err("[%s:%d(%s)]" fmt, \
1184 __func__, __LINE__, \
1185 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1186 ## __VA_ARGS__); \
1187 } while (0)
fe56b9e6
YM		 1188
1189#define DP_NOTICE(cdev, fmt, ...) \
1190 do { \
1191 if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \
1192 pr_notice("[%s:%d(%s)]" fmt, \
1193 __func__, __LINE__, \
1194 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1195 ## __VA_ARGS__); \
1196 \
1197 } \
1198 } while (0)
1199
1200#define DP_INFO(cdev, fmt, ...) \
1201 do { \
1202 if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) { \
1203 pr_notice("[%s:%d(%s)]" fmt, \
1204 __func__, __LINE__, \
1205 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1206 ## __VA_ARGS__); \
1207 } \
1208 } while (0)
1209
1210#define DP_VERBOSE(cdev, module, fmt, ...) \
1211 do { \
1212 if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) && \
1213 ((cdev)->dp_module & module))) { \
1214 pr_notice("[%s:%d(%s)]" fmt, \
1215 __func__, __LINE__, \
1216 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1217 ## __VA_ARGS__); \
1218 } \
1219 } while (0)
1220
1221enum DP_LEVEL {
1222 QED_LEVEL_VERBOSE = 0x0,
1223 QED_LEVEL_INFO = 0x1,
1224 QED_LEVEL_NOTICE = 0x2,
1225 QED_LEVEL_ERR = 0x3,
1226};
1227
1228#define QED_LOG_LEVEL_SHIFT (30)
1229#define QED_LOG_VERBOSE_MASK (0x3fffffff)
1230#define QED_LOG_INFO_MASK (0x40000000)
1231#define QED_LOG_NOTICE_MASK (0x80000000)
1232
1233enum DP_MODULE {
1234 QED_MSG_SPQ = 0x10000,
1235 QED_MSG_STATS = 0x20000,
1236 QED_MSG_DCB = 0x40000,
1237 QED_MSG_IOV = 0x80000,
1238 QED_MSG_SP = 0x100000,
1239 QED_MSG_STORAGE = 0x200000,
1240 QED_MSG_CXT = 0x800000,
0a7fb11c 1241 QED_MSG_LL2 = 0x1000000,
fe56b9e6 1242 QED_MSG_ILT = 0x2000000,
51ff1725 1243 QED_MSG_RDMA = 0x4000000,
fe56b9e6
YM		 1244 QED_MSG_DEBUG = 0x8000000,
1245 /* to be added...up to 0x8000000 */
1246};
1247
fc48b7a6
YM		 1248enum qed_mf_mode {
1249 QED_MF_DEFAULT,
1250 QED_MF_OVLAN,
1251 QED_MF_NPAR,
1252};
1253
9c79ddaa 1254struct qed_eth_stats_common {
fe56b9e6
YM		 1255 u64 no_buff_discards;
1256 u64 packet_too_big_discard;
1257 u64 ttl0_discard;
1258 u64 rx_ucast_bytes;
1259 u64 rx_mcast_bytes;
1260 u64 rx_bcast_bytes;
1261 u64 rx_ucast_pkts;
1262 u64 rx_mcast_pkts;
1263 u64 rx_bcast_pkts;
1264 u64 mftag_filter_discards;
1265 u64 mac_filter_discards;
608e00d0 1266 u64 gft_filter_drop;
fe56b9e6
YM		 1267 u64 tx_ucast_bytes;
1268 u64 tx_mcast_bytes;
1269 u64 tx_bcast_bytes;
1270 u64 tx_ucast_pkts;
1271 u64 tx_mcast_pkts;
1272 u64 tx_bcast_pkts;
1273 u64 tx_err_drop_pkts;
1274 u64 tpa_coalesced_pkts;
1275 u64 tpa_coalesced_events;
1276 u64 tpa_aborts_num;
1277 u64 tpa_not_coalesced_pkts;
1278 u64 tpa_coalesced_bytes;
1279
1280 /* port */
1281 u64 rx_64_byte_packets;
d4967cf3
YM		 1282 u64 rx_65_to_127_byte_packets;
1283 u64 rx_128_to_255_byte_packets;
1284 u64 rx_256_to_511_byte_packets;
1285 u64 rx_512_to_1023_byte_packets;
1286 u64 rx_1024_to_1518_byte_packets;
fe56b9e6
YM		 1287 u64 rx_crc_errors;
1288 u64 rx_mac_crtl_frames;
1289 u64 rx_pause_frames;
1290 u64 rx_pfc_frames;
1291 u64 rx_align_errors;
1292 u64 rx_carrier_errors;
1293 u64 rx_oversize_packets;
1294 u64 rx_jabbers;
1295 u64 rx_undersize_packets;
1296 u64 rx_fragments;
1297 u64 tx_64_byte_packets;
1298 u64 tx_65_to_127_byte_packets;
1299 u64 tx_128_to_255_byte_packets;
1300 u64 tx_256_to_511_byte_packets;
1301 u64 tx_512_to_1023_byte_packets;
1302 u64 tx_1024_to_1518_byte_packets;
fe56b9e6
YM		 1303 u64 tx_pause_frames;
1304 u64 tx_pfc_frames;
fe56b9e6
YM		 1305 u64 brb_truncates;
1306 u64 brb_discards;
1307 u64 rx_mac_bytes;
1308 u64 rx_mac_uc_packets;
1309 u64 rx_mac_mc_packets;
1310 u64 rx_mac_bc_packets;
1311 u64 rx_mac_frames_ok;
1312 u64 tx_mac_bytes;
1313 u64 tx_mac_uc_packets;
1314 u64 tx_mac_mc_packets;
1315 u64 tx_mac_bc_packets;
1316 u64 tx_mac_ctrl_frames;
32d26a68 1317 u64 link_change_count;
fe56b9e6
YM		 1318};
1319
9c79ddaa
MY		 1320struct qed_eth_stats_bb {
1321 u64 rx_1519_to_1522_byte_packets;
1322 u64 rx_1519_to_2047_byte_packets;
1323 u64 rx_2048_to_4095_byte_packets;
1324 u64 rx_4096_to_9216_byte_packets;
1325 u64 rx_9217_to_16383_byte_packets;
1326 u64 tx_1519_to_2047_byte_packets;
1327 u64 tx_2048_to_4095_byte_packets;
1328 u64 tx_4096_to_9216_byte_packets;
1329 u64 tx_9217_to_16383_byte_packets;
1330 u64 tx_lpi_entry_count;
1331 u64 tx_total_collisions;
1332};
1333
1334struct qed_eth_stats_ah {
1335 u64 rx_1519_to_max_byte_packets;
1336 u64 tx_1519_to_max_byte_packets;
1337};
1338
1339struct qed_eth_stats {
1340 struct qed_eth_stats_common common;
1341
1342 union {
1343 struct qed_eth_stats_bb bb;
1344 struct qed_eth_stats_ah ah;
1345 };
1346};
1347
fe56b9e6
YM		 1348#define QED_SB_IDX 0x0002
1349
1350#define RX_PI 0
1351#define TX_PI(tc) (RX_PI + 1 + tc)
1352
4ac801b7 1353struct qed_sb_cnt_info {
726fdbe9
MY		 1354 /* Original, current, and free SBs for PF */
1355 int orig;
1356 int cnt;
1357 int free_cnt;
1358
1359 /* Original, current and free SBS for child VFs */
1360 int iov_orig;
1361 int iov_cnt;
1362 int free_cnt_iov;
4ac801b7
YM		 1363};
1364
fe56b9e6
YM		 1365static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info)
1366{
1367 u32 prod = 0;
1368 u16 rc = 0;
1369
1370 prod = le32_to_cpu(sb_info->sb_virt->prod_index) &
21dd79e8 1371 STATUS_BLOCK_E4_PROD_INDEX_MASK;
fe56b9e6
YM		 1372 if (sb_info->sb_ack != prod) {
1373 sb_info->sb_ack = prod;
1374 rc |= QED_SB_IDX;
1375 }
1376
1377 /* Let SB update */
fe56b9e6
YM		 1378 return rc;
1379}
1380
1381/**
1382 *
1383 * @brief This function creates an update command for interrupts that is
1384 * written to the IGU.
1385 *
1386 * @param sb_info - This is the structure allocated and
1387 * initialized per status block. Assumption is
1388 * that it was initialized using qed_sb_init
1389 * @param int_cmd - Enable/Disable/Nop
1390 * @param upd_flg - whether igu consumer should be
1391 * updated.
1392 *
1393 * @return inline void
1394 */
1395static inline void qed_sb_ack(struct qed_sb_info *sb_info,
1396 enum igu_int_cmd int_cmd,
1397 u8 upd_flg)
1398{
1399 struct igu_prod_cons_update igu_ack = { 0 };
1400
1401 igu_ack.sb_id_and_flags =
1402 ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
1403 (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
1404 (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
1405 (IGU_SEG_ACCESS_REG <<
1406 IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
1407
1408 DIRECT_REG_WR(sb_info->igu_addr, igu_ack.sb_id_and_flags);
1409
1410 /* Both segments (interrupts & acks) are written to same place address;
1411 * Need to guarantee all commands will be received (in-order) by HW.
1412 */
fe56b9e6
YM		 1413 barrier();
1414}
1415
1416static inline void __internal_ram_wr(void *p_hwfn,
1417 void __iomem *addr,
1418 int size,
1419 u32 *data)
1420
1421{
1422 unsigned int i;
1423
1424 for (i = 0; i < size / sizeof(*data); i++)
1425 DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]);
1426}
1427
1428static inline void internal_ram_wr(void __iomem *addr,
1429 int size,
1430 u32 *data)
1431{
1432 __internal_ram_wr(NULL, addr, size, data);
1433}
1434
8c5ebd0c
SRK		 1435enum qed_rss_caps {
1436 QED_RSS_IPV4 = 0x1,
1437 QED_RSS_IPV6 = 0x2,
1438 QED_RSS_IPV4_TCP = 0x4,
1439 QED_RSS_IPV6_TCP = 0x8,
1440 QED_RSS_IPV4_UDP = 0x10,
1441 QED_RSS_IPV6_UDP = 0x20,
1442};
1443
1444#define QED_RSS_IND_TABLE_SIZE 128
1445#define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */
fe56b9e6 1446#endif
Linux 6.x block layer and io_uring tree(s)