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97fb5e8d | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
65f0c90b | 2 | /* Copyright (c) 2010-2015, 2018-2019 The Linux Foundation. All rights reserved. |
2ce76a6a | 3 | * Copyright (C) 2015 Linaro Ltd. |
2a1eb58a | 4 | */ |
4de43476 KG |
5 | #ifndef __QCOM_SCM_H |
6 | #define __QCOM_SCM_H | |
2a1eb58a | 7 | |
2076607a | 8 | #include <linux/err.h> |
29ff62f7 JC |
9 | #include <linux/types.h> |
10 | #include <linux/cpumask.h> | |
11 | ||
e1279912 SV |
12 | #define QCOM_SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF)) |
13 | #define QCOM_SCM_CPU_PWR_DOWN_L2_ON 0x0 | |
14 | #define QCOM_SCM_CPU_PWR_DOWN_L2_OFF 0x1 | |
9626b699 | 15 | #define QCOM_SCM_HDCP_MAX_REQ_CNT 5 |
16 | ||
17 | struct qcom_scm_hdcp_req { | |
18 | u32 addr; | |
19 | u32 val; | |
20 | }; | |
21 | ||
d82bd359 AKD |
22 | struct qcom_scm_vmperm { |
23 | int vmid; | |
24 | int perm; | |
25 | }; | |
26 | ||
b0a1614f RC |
27 | enum qcom_scm_ocmem_client { |
28 | QCOM_SCM_OCMEM_UNUSED_ID = 0x0, | |
29 | QCOM_SCM_OCMEM_GRAPHICS_ID, | |
30 | QCOM_SCM_OCMEM_VIDEO_ID, | |
31 | QCOM_SCM_OCMEM_LP_AUDIO_ID, | |
32 | QCOM_SCM_OCMEM_SENSORS_ID, | |
33 | QCOM_SCM_OCMEM_OTHER_OS_ID, | |
34 | QCOM_SCM_OCMEM_DEBUG_ID, | |
35 | }; | |
36 | ||
0434a406 RC |
37 | enum qcom_scm_sec_dev_id { |
38 | QCOM_SCM_MDSS_DEV_ID = 1, | |
39 | QCOM_SCM_OCMEM_DEV_ID = 5, | |
40 | QCOM_SCM_PCIE0_DEV_ID = 11, | |
41 | QCOM_SCM_PCIE1_DEV_ID = 12, | |
42 | QCOM_SCM_GFX_DEV_ID = 18, | |
43 | QCOM_SCM_UFS_DEV_ID = 19, | |
44 | QCOM_SCM_ICE_DEV_ID = 20, | |
45 | }; | |
46 | ||
0f206514 EB |
47 | enum qcom_scm_ice_cipher { |
48 | QCOM_SCM_ICE_CIPHER_AES_128_XTS = 0, | |
49 | QCOM_SCM_ICE_CIPHER_AES_128_CBC = 1, | |
50 | QCOM_SCM_ICE_CIPHER_AES_256_XTS = 3, | |
51 | QCOM_SCM_ICE_CIPHER_AES_256_CBC = 4, | |
52 | }; | |
53 | ||
d82bd359 AKD |
54 | #define QCOM_SCM_VMID_HLOS 0x3 |
55 | #define QCOM_SCM_VMID_MSS_MSA 0xF | |
cc53aabc GS |
56 | #define QCOM_SCM_VMID_WLAN 0x18 |
57 | #define QCOM_SCM_VMID_WLAN_CE 0x19 | |
d82bd359 AKD |
58 | #define QCOM_SCM_PERM_READ 0x4 |
59 | #define QCOM_SCM_PERM_WRITE 0x2 | |
60 | #define QCOM_SCM_PERM_EXEC 0x1 | |
61 | #define QCOM_SCM_PERM_RW (QCOM_SCM_PERM_READ | QCOM_SCM_PERM_WRITE) | |
62 | #define QCOM_SCM_PERM_RWX (QCOM_SCM_PERM_RW | QCOM_SCM_PERM_EXEC) | |
63 | ||
65f0c90b EB |
64 | extern bool qcom_scm_is_available(void); |
65 | ||
e1279912 SV |
66 | extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus); |
67 | extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus); | |
65f0c90b EB |
68 | extern void qcom_scm_cpu_power_down(u32 flags); |
69 | extern int qcom_scm_set_remote_state(u32 state, u32 id); | |
70 | ||
f01e90fe | 71 | extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, |
e1279912 | 72 | size_t size); |
f01e90fe | 73 | extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, |
e1279912 | 74 | phys_addr_t size); |
f01e90fe BA |
75 | extern int qcom_scm_pas_auth_and_reset(u32 peripheral); |
76 | extern int qcom_scm_pas_shutdown(u32 peripheral); | |
65f0c90b EB |
77 | extern bool qcom_scm_pas_supported(u32 peripheral); |
78 | ||
79 | extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val); | |
80 | extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val); | |
81 | ||
0434a406 | 82 | extern bool qcom_scm_restore_sec_cfg_available(void); |
a2c680c6 | 83 | extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare); |
b182cc4d SV |
84 | extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size); |
85 | extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare); | |
6d885330 SV |
86 | extern int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size, |
87 | u32 cp_nonpixel_start, | |
88 | u32 cp_nonpixel_size); | |
65f0c90b EB |
89 | extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz, |
90 | unsigned int *src, | |
91 | const struct qcom_scm_vmperm *newvm, | |
92 | unsigned int dest_cnt); | |
93 | ||
94 | extern bool qcom_scm_ocmem_lock_available(void); | |
95 | extern int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset, | |
96 | u32 size, u32 mode); | |
97 | extern int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset, | |
98 | u32 size); | |
99 | ||
0f206514 EB |
100 | extern bool qcom_scm_ice_available(void); |
101 | extern int qcom_scm_ice_invalidate_key(u32 index); | |
102 | extern int qcom_scm_ice_set_key(u32 index, const u8 *key, u32 key_size, | |
103 | enum qcom_scm_ice_cipher cipher, | |
104 | u32 data_unit_size); | |
105 | ||
65f0c90b EB |
106 | extern bool qcom_scm_hdcp_available(void); |
107 | extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, | |
108 | u32 *resp); | |
109 | ||
5eb0e0e4 | 110 | extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en); |
de3438c4 TG |
111 | |
112 | extern int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val, | |
113 | u64 limit_node, u32 node_id, u64 version); | |
114 | extern int qcom_scm_lmh_profile_change(u32 profile_id); | |
115 | extern bool qcom_scm_lmh_dcvsh_available(void); | |
116 | ||
2a1eb58a | 117 | #endif |