[linux-block.git] / include / linux / qcom_scm.h

/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2010-2015, 2018-2019 The Linux Foundation. All rights reserved.
 * Copyright (C) 2015 Linaro Ltd.
 */
#ifndef __QCOM_SCM_H
#define __QCOM_SCM_H

#include <linux/err.h>
#include <linux/types.h>
#include <linux/cpumask.h>

#define QCOM_SCM_VERSION(major, minor)	(((major) << 16) | ((minor) & 0xFF))
#define QCOM_SCM_CPU_PWR_DOWN_L2_ON	0x0
#define QCOM_SCM_CPU_PWR_DOWN_L2_OFF	0x1
#define QCOM_SCM_HDCP_MAX_REQ_CNT	5

struct qcom_scm_hdcp_req {
	u32 addr;
	u32 val;
};

struct qcom_scm_vmperm {
	int vmid;
	int perm;
};

enum qcom_scm_ocmem_client {
	QCOM_SCM_OCMEM_UNUSED_ID = 0x0,
	QCOM_SCM_OCMEM_GRAPHICS_ID,
	QCOM_SCM_OCMEM_VIDEO_ID,
	QCOM_SCM_OCMEM_LP_AUDIO_ID,
	QCOM_SCM_OCMEM_SENSORS_ID,
	QCOM_SCM_OCMEM_OTHER_OS_ID,
	QCOM_SCM_OCMEM_DEBUG_ID,
};

enum qcom_scm_sec_dev_id {
	QCOM_SCM_MDSS_DEV_ID    = 1,
	QCOM_SCM_OCMEM_DEV_ID   = 5,
	QCOM_SCM_PCIE0_DEV_ID   = 11,
	QCOM_SCM_PCIE1_DEV_ID   = 12,
	QCOM_SCM_GFX_DEV_ID     = 18,
	QCOM_SCM_UFS_DEV_ID     = 19,
	QCOM_SCM_ICE_DEV_ID     = 20,
};

enum qcom_scm_ice_cipher {
	QCOM_SCM_ICE_CIPHER_AES_128_XTS = 0,
	QCOM_SCM_ICE_CIPHER_AES_128_CBC = 1,
	QCOM_SCM_ICE_CIPHER_AES_256_XTS = 3,
	QCOM_SCM_ICE_CIPHER_AES_256_CBC = 4,
};

#define QCOM_SCM_VMID_HLOS       0x3
#define QCOM_SCM_VMID_MSS_MSA    0xF
#define QCOM_SCM_VMID_WLAN       0x18
#define QCOM_SCM_VMID_WLAN_CE    0x19
#define QCOM_SCM_PERM_READ       0x4
#define QCOM_SCM_PERM_WRITE      0x2
#define QCOM_SCM_PERM_EXEC       0x1
#define QCOM_SCM_PERM_RW (QCOM_SCM_PERM_READ | QCOM_SCM_PERM_WRITE)
#define QCOM_SCM_PERM_RWX (QCOM_SCM_PERM_RW | QCOM_SCM_PERM_EXEC)

extern bool qcom_scm_is_available(void);

extern int qcom_scm_set_cold_boot_addr(void *entry);
extern int qcom_scm_set_warm_boot_addr(void *entry);
extern void qcom_scm_cpu_power_down(u32 flags);
extern int qcom_scm_set_remote_state(u32 state, u32 id);

struct qcom_scm_pas_metadata {
	void *ptr;
	dma_addr_t phys;
	ssize_t size;
};

extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
				   size_t size,
				   struct qcom_scm_pas_metadata *ctx);
void qcom_scm_pas_metadata_release(struct qcom_scm_pas_metadata *ctx);
extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
				  phys_addr_t size);
extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
extern int qcom_scm_pas_shutdown(u32 peripheral);
extern bool qcom_scm_pas_supported(u32 peripheral);

extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);

extern bool qcom_scm_restore_sec_cfg_available(void);
extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
extern int qcom_scm_iommu_set_cp_pool_size(u32 spare, u32 size);
extern int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size,
					  u32 cp_nonpixel_start,
					  u32 cp_nonpixel_size);
extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
			       unsigned int *src,
			       const struct qcom_scm_vmperm *newvm,
			       unsigned int dest_cnt);

extern bool qcom_scm_ocmem_lock_available(void);
extern int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset,
			       u32 size, u32 mode);
extern int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset,
				 u32 size);

extern bool qcom_scm_ice_available(void);
extern int qcom_scm_ice_invalidate_key(u32 index);
extern int qcom_scm_ice_set_key(u32 index, const u8 *key, u32 key_size,
				enum qcom_scm_ice_cipher cipher,
				u32 data_unit_size);

extern bool qcom_scm_hdcp_available(void);
extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
			     u32 *resp);

extern int qcom_scm_iommu_set_pt_format(u32 sec_id, u32 ctx_num, u32 pt_fmt);
extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en);

extern int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val,
			      u64 limit_node, u32 node_id, u64 version);
extern int qcom_scm_lmh_profile_change(u32 profile_id);
extern bool qcom_scm_lmh_dcvsh_available(void);

#endif
Commit	Line	Data
97fb5e8d	1	/* SPDX-License-Identifier: GPL-2.0-only */
65f0c90b	2	/* Copyright (c) 2010-2015, 2018-2019 The Linux Foundation. All rights reserved.
2ce76a6a	3	* Copyright (C) 2015 Linaro Ltd.
2a1eb58a	4	*/
4de43476 KG	5	#ifndef __QCOM_SCM_H
4de43476 KG	6	#define __QCOM_SCM_H
2a1eb58a	7
2076607a	8	#include <linux/err.h>
29ff62f7 JC	9	#include <linux/types.h>
	10	#include <linux/cpumask.h>
	11
e1279912 SV	12	#define QCOM_SCM_VERSION(major, minor) (((major) << 16) \| ((minor) & 0xFF))
	13	#define QCOM_SCM_CPU_PWR_DOWN_L2_ON 0x0
	14	#define QCOM_SCM_CPU_PWR_DOWN_L2_OFF 0x1
9626b699	15	#define QCOM_SCM_HDCP_MAX_REQ_CNT 5
	16
	17	struct qcom_scm_hdcp_req {
	18	u32 addr;
	19	u32 val;
	20	};
	21
d82bd359 AKD	22	struct qcom_scm_vmperm {
	23	int vmid;
	24	int perm;
	25	};
	26
b0a1614f RC	27	enum qcom_scm_ocmem_client {
	28	QCOM_SCM_OCMEM_UNUSED_ID = 0x0,
	29	QCOM_SCM_OCMEM_GRAPHICS_ID,
	30	QCOM_SCM_OCMEM_VIDEO_ID,
	31	QCOM_SCM_OCMEM_LP_AUDIO_ID,
	32	QCOM_SCM_OCMEM_SENSORS_ID,
	33	QCOM_SCM_OCMEM_OTHER_OS_ID,
	34	QCOM_SCM_OCMEM_DEBUG_ID,
	35	};
	36
0434a406 RC	37	enum qcom_scm_sec_dev_id {
	38	QCOM_SCM_MDSS_DEV_ID = 1,
	39	QCOM_SCM_OCMEM_DEV_ID = 5,
	40	QCOM_SCM_PCIE0_DEV_ID = 11,
	41	QCOM_SCM_PCIE1_DEV_ID = 12,
	42	QCOM_SCM_GFX_DEV_ID = 18,
	43	QCOM_SCM_UFS_DEV_ID = 19,
	44	QCOM_SCM_ICE_DEV_ID = 20,
	45	};
	46
0f206514 EB	47	enum qcom_scm_ice_cipher {
	48	QCOM_SCM_ICE_CIPHER_AES_128_XTS = 0,
	49	QCOM_SCM_ICE_CIPHER_AES_128_CBC = 1,
	50	QCOM_SCM_ICE_CIPHER_AES_256_XTS = 3,
	51	QCOM_SCM_ICE_CIPHER_AES_256_CBC = 4,
	52	};
	53
d82bd359 AKD	54	#define QCOM_SCM_VMID_HLOS 0x3
d82bd359 AKD	55	#define QCOM_SCM_VMID_MSS_MSA 0xF
cc53aabc GS	56	#define QCOM_SCM_VMID_WLAN 0x18
cc53aabc GS	57	#define QCOM_SCM_VMID_WLAN_CE 0x19
d82bd359 AKD	58	#define QCOM_SCM_PERM_READ 0x4
	59	#define QCOM_SCM_PERM_WRITE 0x2
	60	#define QCOM_SCM_PERM_EXEC 0x1
	61	#define QCOM_SCM_PERM_RW (QCOM_SCM_PERM_READ \| QCOM_SCM_PERM_WRITE)
	62	#define QCOM_SCM_PERM_RWX (QCOM_SCM_PERM_RW \| QCOM_SCM_PERM_EXEC)
	63
65f0c90b EB	64	extern bool qcom_scm_is_available(void);
65f0c90b EB	65
52beb1fc SG	66	extern int qcom_scm_set_cold_boot_addr(void *entry);
52beb1fc SG	67	extern int qcom_scm_set_warm_boot_addr(void *entry);
65f0c90b EB	68	extern void qcom_scm_cpu_power_down(u32 flags);
	69	extern int qcom_scm_set_remote_state(u32 state, u32 id);
	70
3a99f121 BA	71	struct qcom_scm_pas_metadata {
	72	void *ptr;
	73	dma_addr_t phys;
	74	ssize_t size;
	75	};
	76
f01e90fe	77	extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
3a99f121 BA	78	size_t size,
	79	struct qcom_scm_pas_metadata *ctx);
	80	void qcom_scm_pas_metadata_release(struct qcom_scm_pas_metadata *ctx);
f01e90fe	81	extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
e1279912	82	phys_addr_t size);
f01e90fe BA	83	extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
f01e90fe BA	84	extern int qcom_scm_pas_shutdown(u32 peripheral);
65f0c90b EB	85	extern bool qcom_scm_pas_supported(u32 peripheral);
	86
	87	extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
	88	extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
	89
0434a406	90	extern bool qcom_scm_restore_sec_cfg_available(void);
a2c680c6	91	extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
b182cc4d SV	92	extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
b182cc4d SV	93	extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
94351509	94	extern int qcom_scm_iommu_set_cp_pool_size(u32 spare, u32 size);
6d885330 SV	95	extern int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size,
	96	u32 cp_nonpixel_start,
	97	u32 cp_nonpixel_size);
65f0c90b EB	98	extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
	99	unsigned int *src,
	100	const struct qcom_scm_vmperm *newvm,
	101	unsigned int dest_cnt);
	102
	103	extern bool qcom_scm_ocmem_lock_available(void);
	104	extern int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset,
	105	u32 size, u32 mode);
	106	extern int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset,
	107	u32 size);
	108
0f206514 EB	109	extern bool qcom_scm_ice_available(void);
	110	extern int qcom_scm_ice_invalidate_key(u32 index);
	111	extern int qcom_scm_ice_set_key(u32 index, const u8 *key, u32 key_size,
	112	enum qcom_scm_ice_cipher cipher,
	113	u32 data_unit_size);
	114
65f0c90b EB	115	extern bool qcom_scm_hdcp_available(void);
	116	extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
	117	u32 *resp);
	118
071a1333	119	extern int qcom_scm_iommu_set_pt_format(u32 sec_id, u32 ctx_num, u32 pt_fmt);
5eb0e0e4	120	extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en);
de3438c4 TG	121
	122	extern int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val,
	123	u64 limit_node, u32 node_id, u64 version);
	124	extern int qcom_scm_lmh_profile_change(u32 profile_id);
	125	extern bool qcom_scm_lmh_dcvsh_available(void);
	126
2a1eb58a	127	#endif