[linux-2.6-block.git] / include / linux / qcom_scm.h

/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2010-2015, 2018, The Linux Foundation. All rights reserved.
 * Copyright (C) 2015 Linaro Ltd.
 */
#ifndef __QCOM_SCM_H
#define __QCOM_SCM_H

#include <linux/err.h>
#include <linux/types.h>
#include <linux/cpumask.h>

#define QCOM_SCM_VERSION(major, minor)	(((major) << 16) | ((minor) & 0xFF))
#define QCOM_SCM_CPU_PWR_DOWN_L2_ON	0x0
#define QCOM_SCM_CPU_PWR_DOWN_L2_OFF	0x1
#define QCOM_SCM_HDCP_MAX_REQ_CNT	5

struct qcom_scm_hdcp_req {
	u32 addr;
	u32 val;
};

struct qcom_scm_vmperm {
	int vmid;
	int perm;
};

#define QCOM_SCM_VMID_HLOS       0x3
#define QCOM_SCM_VMID_MSS_MSA    0xF
#define QCOM_SCM_VMID_WLAN       0x18
#define QCOM_SCM_VMID_WLAN_CE    0x19
#define QCOM_SCM_PERM_READ       0x4
#define QCOM_SCM_PERM_WRITE      0x2
#define QCOM_SCM_PERM_EXEC       0x1
#define QCOM_SCM_PERM_RW (QCOM_SCM_PERM_READ | QCOM_SCM_PERM_WRITE)
#define QCOM_SCM_PERM_RWX (QCOM_SCM_PERM_RW | QCOM_SCM_PERM_EXEC)

#if IS_ENABLED(CONFIG_QCOM_SCM)
extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
extern bool qcom_scm_is_available(void);
extern bool qcom_scm_hdcp_available(void);
extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
			     u32 *resp);
extern bool qcom_scm_pas_supported(u32 peripheral);
extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
				   size_t size);
extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
				  phys_addr_t size);
extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
extern int qcom_scm_pas_shutdown(u32 peripheral);
extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
			       unsigned int *src, struct qcom_scm_vmperm *newvm,
			       int dest_cnt);
extern void qcom_scm_cpu_power_down(u32 flags);
extern u32 qcom_scm_get_version(void);
extern int qcom_scm_set_remote_state(u32 state, u32 id);
extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
#else

#include <linux/errno.h>

static inline
int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
{
	return -ENODEV;
}
static inline
int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
{
	return -ENODEV;
}
static inline bool qcom_scm_is_available(void) { return false; }
static inline bool qcom_scm_hdcp_available(void) { return false; }
static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
				    u32 *resp) { return -ENODEV; }
static inline bool qcom_scm_pas_supported(u32 peripheral) { return false; }
static inline int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
					  size_t size) { return -ENODEV; }
static inline int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
					 phys_addr_t size) { return -ENODEV; }
static inline int
qcom_scm_pas_auth_and_reset(u32 peripheral) { return -ENODEV; }
static inline int qcom_scm_pas_shutdown(u32 peripheral) { return -ENODEV; }
static inline int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
				      unsigned int *src,
				      struct qcom_scm_vmperm *newvm,
				      int dest_cnt) { return -ENODEV; }
static inline void qcom_scm_cpu_power_down(u32 flags) {}
static inline u32 qcom_scm_get_version(void) { return 0; }
static inline u32
qcom_scm_set_remote_state(u32 state,u32 id) { return -ENODEV; }
static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) { return -ENODEV; }
static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) { return -ENODEV; }
static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) { return -ENODEV; }
static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) { return -ENODEV; }
static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) { return -ENODEV; }
#endif
#endif
Commit	Line	Data
97fb5e8d	1	/* SPDX-License-Identifier: GPL-2.0-only */
cc53aabc	2	/* Copyright (c) 2010-2015, 2018, The Linux Foundation. All rights reserved.
2ce76a6a	3	* Copyright (C) 2015 Linaro Ltd.
2a1eb58a	4	*/
4de43476 KG	5	#ifndef __QCOM_SCM_H
4de43476 KG	6	#define __QCOM_SCM_H
2a1eb58a	7
2076607a	8	#include <linux/err.h>
29ff62f7 JC	9	#include <linux/types.h>
	10	#include <linux/cpumask.h>
	11
e1279912 SV	12	#define QCOM_SCM_VERSION(major, minor) (((major) << 16) \| ((minor) & 0xFF))
	13	#define QCOM_SCM_CPU_PWR_DOWN_L2_ON 0x0
	14	#define QCOM_SCM_CPU_PWR_DOWN_L2_OFF 0x1
9626b699	15	#define QCOM_SCM_HDCP_MAX_REQ_CNT 5
	16
	17	struct qcom_scm_hdcp_req {
	18	u32 addr;
	19	u32 val;
	20	};
	21
d82bd359 AKD	22	struct qcom_scm_vmperm {
	23	int vmid;
	24	int perm;
	25	};
	26
	27	#define QCOM_SCM_VMID_HLOS 0x3
	28	#define QCOM_SCM_VMID_MSS_MSA 0xF
cc53aabc GS	29	#define QCOM_SCM_VMID_WLAN 0x18
cc53aabc GS	30	#define QCOM_SCM_VMID_WLAN_CE 0x19
d82bd359 AKD	31	#define QCOM_SCM_PERM_READ 0x4
	32	#define QCOM_SCM_PERM_WRITE 0x2
	33	#define QCOM_SCM_PERM_EXEC 0x1
	34	#define QCOM_SCM_PERM_RW (QCOM_SCM_PERM_READ \| QCOM_SCM_PERM_WRITE)
	35	#define QCOM_SCM_PERM_RWX (QCOM_SCM_PERM_RW \| QCOM_SCM_PERM_EXEC)
	36
e1279912 SV	37	#if IS_ENABLED(CONFIG_QCOM_SCM)
	38	extern int qcom_scm_set_cold_boot_addr(void entry, const cpumask_t cpus);
	39	extern int qcom_scm_set_warm_boot_addr(void entry, const cpumask_t cpus);
2d3c277c	40	extern bool qcom_scm_is_available(void);
9626b699	41	extern bool qcom_scm_hdcp_available(void);
9626b699	42	extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
e1279912	43	u32 *resp);
f01e90fe BA	44	extern bool qcom_scm_pas_supported(u32 peripheral);
f01e90fe BA	45	extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
e1279912	46	size_t size);
f01e90fe	47	extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
e1279912	48	phys_addr_t size);
f01e90fe BA	49	extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
f01e90fe BA	50	extern int qcom_scm_pas_shutdown(u32 peripheral);
d82bd359 AKD	51	extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
	52	unsigned int src, struct qcom_scm_vmperm newvm,
	53	int dest_cnt);
767b0235	54	extern void qcom_scm_cpu_power_down(u32 flags);
4de43476	55	extern u32 qcom_scm_get_version(void);
a811b420	56	extern int qcom_scm_set_remote_state(u32 state, u32 id);
a2c680c6	57	extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
b182cc4d SV	58	extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
b182cc4d SV	59	extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
4e659dbe BA	60	extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
4e659dbe BA	61	extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
e1279912	62	#else
16ad9501 JM	63
	64	#include <linux/errno.h>
	65
e1279912 SV	66	static inline
	67	int qcom_scm_set_cold_boot_addr(void entry, const cpumask_t cpus)
	68	{
	69	return -ENODEV;
	70	}
	71	static inline
	72	int qcom_scm_set_warm_boot_addr(void entry, const cpumask_t cpus)
	73	{
	74	return -ENODEV;
	75	}
	76	static inline bool qcom_scm_is_available(void) { return false; }
	77	static inline bool qcom_scm_hdcp_available(void) { return false; }
	78	static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
	79	u32 *resp) { return -ENODEV; }
	80	static inline bool qcom_scm_pas_supported(u32 peripheral) { return false; }
	81	static inline int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
	82	size_t size) { return -ENODEV; }
	83	static inline int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
	84	phys_addr_t size) { return -ENODEV; }
	85	static inline int
	86	qcom_scm_pas_auth_and_reset(u32 peripheral) { return -ENODEV; }
	87	static inline int qcom_scm_pas_shutdown(u32 peripheral) { return -ENODEV; }
a0b1561f NC	88	static inline int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
	89	unsigned int *src,
	90	struct qcom_scm_vmperm *newvm,
	91	int dest_cnt) { return -ENODEV; }
e1279912 SV	92	static inline void qcom_scm_cpu_power_down(u32 flags) {}
e1279912 SV	93	static inline u32 qcom_scm_get_version(void) { return 0; }
a811b420 AG	94	static inline u32
a811b420 AG	95	qcom_scm_set_remote_state(u32 state,u32 id) { return -ENODEV; }
a2c680c6	96	static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) { return -ENODEV; }
b182cc4d SV	97	static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) { return -ENODEV; }
b182cc4d SV	98	static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) { return -ENODEV; }
4e659dbe BA	99	static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) { return -ENODEV; }
4e659dbe BA	100	static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) { return -ENODEV; }
e1279912	101	#endif
2a1eb58a	102	#endif