[linux-block.git] / include / linux / qcom-geni-se.h

/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
 */

#ifndef _LINUX_QCOM_GENI_SE
#define _LINUX_QCOM_GENI_SE

/* Transfer mode supported by GENI Serial Engines */
enum geni_se_xfer_mode {
	GENI_SE_INVALID,
	GENI_SE_FIFO,
	GENI_SE_DMA,
};

/* Protocols supported by GENI Serial Engines */
enum geni_se_protocol_type {
	GENI_SE_NONE,
	GENI_SE_SPI,
	GENI_SE_UART,
	GENI_SE_I2C,
	GENI_SE_I3C,
};

struct geni_wrapper;
struct clk;

/**
 * struct geni_se - GENI Serial Engine
 * @base:		Base Address of the Serial Engine's register block
 * @dev:		Pointer to the Serial Engine device
 * @wrapper:		Pointer to the parent QUP Wrapper core
 * @clk:		Handle to the core serial engine clock
 * @num_clk_levels:	Number of valid clock levels in clk_perf_tbl
 * @clk_perf_tbl:	Table of clock frequency input to serial engine clock
 */
struct geni_se {
	void __iomem *base;
	struct device *dev;
	struct geni_wrapper *wrapper;
	struct clk *clk;
	unsigned int num_clk_levels;
	unsigned long *clk_perf_tbl;
};

/* Common SE registers */
#define GENI_FORCE_DEFAULT_REG		0x20
#define SE_GENI_STATUS			0x40
#define GENI_SER_M_CLK_CFG		0x48
#define GENI_SER_S_CLK_CFG		0x4c
#define GENI_FW_REVISION_RO		0x68
#define SE_GENI_CLK_SEL			0x7c
#define SE_GENI_DMA_MODE_EN		0x258
#define SE_GENI_M_CMD0			0x600
#define SE_GENI_M_CMD_CTRL_REG		0x604
#define SE_GENI_M_IRQ_STATUS		0x610
#define SE_GENI_M_IRQ_EN		0x614
#define SE_GENI_M_IRQ_CLEAR		0x618
#define SE_GENI_S_CMD0			0x630
#define SE_GENI_S_CMD_CTRL_REG		0x634
#define SE_GENI_S_IRQ_STATUS		0x640
#define SE_GENI_S_IRQ_EN		0x644
#define SE_GENI_S_IRQ_CLEAR		0x648
#define SE_GENI_TX_FIFOn		0x700
#define SE_GENI_RX_FIFOn		0x780
#define SE_GENI_TX_FIFO_STATUS		0x800
#define SE_GENI_RX_FIFO_STATUS		0x804
#define SE_GENI_TX_WATERMARK_REG	0x80c
#define SE_GENI_RX_WATERMARK_REG	0x810
#define SE_GENI_RX_RFR_WATERMARK_REG	0x814
#define SE_GENI_IOS			0x908
#define SE_DMA_TX_IRQ_STAT		0xc40
#define SE_DMA_TX_IRQ_CLR		0xc44
#define SE_DMA_TX_FSM_RST		0xc58
#define SE_DMA_RX_IRQ_STAT		0xd40
#define SE_DMA_RX_IRQ_CLR		0xd44
#define SE_DMA_RX_FSM_RST		0xd58
#define SE_HW_PARAM_0			0xe24
#define SE_HW_PARAM_1			0xe28

/* GENI_FORCE_DEFAULT_REG fields */
#define FORCE_DEFAULT	BIT(0)

/* GENI_STATUS fields */
#define M_GENI_CMD_ACTIVE		BIT(0)
#define S_GENI_CMD_ACTIVE		BIT(12)

/* GENI_SER_M_CLK_CFG/GENI_SER_S_CLK_CFG */
#define SER_CLK_EN			BIT(0)
#define CLK_DIV_MSK			GENMASK(15, 4)
#define CLK_DIV_SHFT			4

/* GENI_FW_REVISION_RO fields */
#define FW_REV_PROTOCOL_MSK		GENMASK(15, 8)
#define FW_REV_PROTOCOL_SHFT		8

/* GENI_CLK_SEL fields */
#define CLK_SEL_MSK			GENMASK(2, 0)

/* SE_GENI_DMA_MODE_EN */
#define GENI_DMA_MODE_EN		BIT(0)

/* GENI_M_CMD0 fields */
#define M_OPCODE_MSK			GENMASK(31, 27)
#define M_OPCODE_SHFT			27
#define M_PARAMS_MSK			GENMASK(26, 0)

/* GENI_M_CMD_CTRL_REG */
#define M_GENI_CMD_CANCEL		BIT(2)
#define M_GENI_CMD_ABORT		BIT(1)
#define M_GENI_DISABLE			BIT(0)

/* GENI_S_CMD0 fields */
#define S_OPCODE_MSK			GENMASK(31, 27)
#define S_OPCODE_SHFT			27
#define S_PARAMS_MSK			GENMASK(26, 0)

/* GENI_S_CMD_CTRL_REG */
#define S_GENI_CMD_CANCEL		BIT(2)
#define S_GENI_CMD_ABORT		BIT(1)
#define S_GENI_DISABLE			BIT(0)

/* GENI_M_IRQ_EN fields */
#define M_CMD_DONE_EN			BIT(0)
#define M_CMD_OVERRUN_EN		BIT(1)
#define M_ILLEGAL_CMD_EN		BIT(2)
#define M_CMD_FAILURE_EN		BIT(3)
#define M_CMD_CANCEL_EN			BIT(4)
#define M_CMD_ABORT_EN			BIT(5)
#define M_TIMESTAMP_EN			BIT(6)
#define M_RX_IRQ_EN			BIT(7)
#define M_GP_SYNC_IRQ_0_EN		BIT(8)
#define M_GP_IRQ_0_EN			BIT(9)
#define M_GP_IRQ_1_EN			BIT(10)
#define M_GP_IRQ_2_EN			BIT(11)
#define M_GP_IRQ_3_EN			BIT(12)
#define M_GP_IRQ_4_EN			BIT(13)
#define M_GP_IRQ_5_EN			BIT(14)
#define M_IO_DATA_DEASSERT_EN		BIT(22)
#define M_IO_DATA_ASSERT_EN		BIT(23)
#define M_RX_FIFO_RD_ERR_EN		BIT(24)
#define M_RX_FIFO_WR_ERR_EN		BIT(25)
#define M_RX_FIFO_WATERMARK_EN		BIT(26)
#define M_RX_FIFO_LAST_EN		BIT(27)
#define M_TX_FIFO_RD_ERR_EN		BIT(28)
#define M_TX_FIFO_WR_ERR_EN		BIT(29)
#define M_TX_FIFO_WATERMARK_EN		BIT(30)
#define M_SEC_IRQ_EN			BIT(31)
#define M_COMMON_GENI_M_IRQ_EN	(GENMASK(6, 1) | \
				M_IO_DATA_DEASSERT_EN | \
				M_IO_DATA_ASSERT_EN | M_RX_FIFO_RD_ERR_EN | \
				M_RX_FIFO_WR_ERR_EN | M_TX_FIFO_RD_ERR_EN | \
				M_TX_FIFO_WR_ERR_EN)

/* GENI_S_IRQ_EN fields */
#define S_CMD_DONE_EN			BIT(0)
#define S_CMD_OVERRUN_EN		BIT(1)
#define S_ILLEGAL_CMD_EN		BIT(2)
#define S_CMD_FAILURE_EN		BIT(3)
#define S_CMD_CANCEL_EN			BIT(4)
#define S_CMD_ABORT_EN			BIT(5)
#define S_GP_SYNC_IRQ_0_EN		BIT(8)
#define S_GP_IRQ_0_EN			BIT(9)
#define S_GP_IRQ_1_EN			BIT(10)
#define S_GP_IRQ_2_EN			BIT(11)
#define S_GP_IRQ_3_EN			BIT(12)
#define S_GP_IRQ_4_EN			BIT(13)
#define S_GP_IRQ_5_EN			BIT(14)
#define S_IO_DATA_DEASSERT_EN		BIT(22)
#define S_IO_DATA_ASSERT_EN		BIT(23)
#define S_RX_FIFO_RD_ERR_EN		BIT(24)
#define S_RX_FIFO_WR_ERR_EN		BIT(25)
#define S_RX_FIFO_WATERMARK_EN		BIT(26)
#define S_RX_FIFO_LAST_EN		BIT(27)
#define S_COMMON_GENI_S_IRQ_EN	(GENMASK(5, 1) | GENMASK(13, 9) | \
				 S_RX_FIFO_RD_ERR_EN | S_RX_FIFO_WR_ERR_EN)

/*  GENI_/TX/RX/RX_RFR/_WATERMARK_REG fields */
#define WATERMARK_MSK			GENMASK(5, 0)

/* GENI_TX_FIFO_STATUS fields */
#define TX_FIFO_WC			GENMASK(27, 0)

/*  GENI_RX_FIFO_STATUS fields */
#define RX_LAST				BIT(31)
#define RX_LAST_BYTE_VALID_MSK		GENMASK(30, 28)
#define RX_LAST_BYTE_VALID_SHFT		28
#define RX_FIFO_WC_MSK			GENMASK(24, 0)

/* SE_GENI_IOS fields */
#define IO2_DATA_IN			BIT(1)
#define RX_DATA_IN			BIT(0)

/* SE_DMA_TX_IRQ_STAT Register fields */
#define TX_DMA_DONE			BIT(0)
#define TX_EOT				BIT(1)
#define TX_SBE				BIT(2)
#define TX_RESET_DONE			BIT(3)

/* SE_DMA_RX_IRQ_STAT Register fields */
#define RX_DMA_DONE			BIT(0)
#define RX_EOT				BIT(1)
#define RX_SBE				BIT(2)
#define RX_RESET_DONE			BIT(3)
#define RX_FLUSH_DONE			BIT(4)
#define RX_GENI_GP_IRQ			GENMASK(10, 5)
#define RX_GENI_CANCEL_IRQ		BIT(11)
#define RX_GENI_GP_IRQ_EXT		GENMASK(13, 12)

/* SE_HW_PARAM_0 fields */
#define TX_FIFO_WIDTH_MSK		GENMASK(29, 24)
#define TX_FIFO_WIDTH_SHFT		24
#define TX_FIFO_DEPTH_MSK		GENMASK(21, 16)
#define TX_FIFO_DEPTH_SHFT		16

/* SE_HW_PARAM_1 fields */
#define RX_FIFO_WIDTH_MSK		GENMASK(29, 24)
#define RX_FIFO_WIDTH_SHFT		24
#define RX_FIFO_DEPTH_MSK		GENMASK(21, 16)
#define RX_FIFO_DEPTH_SHFT		16

#define HW_VER_MAJOR_MASK		GENMASK(31, 28)
#define HW_VER_MAJOR_SHFT		28
#define HW_VER_MINOR_MASK		GENMASK(27, 16)
#define HW_VER_MINOR_SHFT		16
#define HW_VER_STEP_MASK		GENMASK(15, 0)

#define GENI_SE_VERSION_MAJOR(ver) ((ver & HW_VER_MAJOR_MASK) >> HW_VER_MAJOR_SHFT)
#define GENI_SE_VERSION_MINOR(ver) ((ver & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT)
#define GENI_SE_VERSION_STEP(ver) (ver & HW_VER_STEP_MASK)

#if IS_ENABLED(CONFIG_QCOM_GENI_SE)

u32 geni_se_get_qup_hw_version(struct geni_se *se);

/**
 * geni_se_read_proto() - Read the protocol configured for a serial engine
 * @se:		Pointer to the concerned serial engine.
 *
 * Return: Protocol value as configured in the serial engine.
 */
static inline u32 geni_se_read_proto(struct geni_se *se)
{
	u32 val;

	val = readl_relaxed(se->base + GENI_FW_REVISION_RO);

	return (val & FW_REV_PROTOCOL_MSK) >> FW_REV_PROTOCOL_SHFT;
}

/**
 * geni_se_setup_m_cmd() - Setup the primary sequencer
 * @se:		Pointer to the concerned serial engine.
 * @cmd:	Command/Operation to setup in the primary sequencer.
 * @params:	Parameter for the sequencer command.
 *
 * This function is used to configure the primary sequencer with the
 * command and its associated parameters.
 */
static inline void geni_se_setup_m_cmd(struct geni_se *se, u32 cmd, u32 params)
{
	u32 m_cmd;

	m_cmd = (cmd << M_OPCODE_SHFT) | (params & M_PARAMS_MSK);
	writel_relaxed(m_cmd, se->base + SE_GENI_M_CMD0);
}

/**
 * geni_se_setup_s_cmd() - Setup the secondary sequencer
 * @se:		Pointer to the concerned serial engine.
 * @cmd:	Command/Operation to setup in the secondary sequencer.
 * @params:	Parameter for the sequencer command.
 *
 * This function is used to configure the secondary sequencer with the
 * command and its associated parameters.
 */
static inline void geni_se_setup_s_cmd(struct geni_se *se, u32 cmd, u32 params)
{
	u32 s_cmd;

	s_cmd = readl_relaxed(se->base + SE_GENI_S_CMD0);
	s_cmd &= ~(S_OPCODE_MSK | S_PARAMS_MSK);
	s_cmd |= (cmd << S_OPCODE_SHFT);
	s_cmd |= (params & S_PARAMS_MSK);
	writel_relaxed(s_cmd, se->base + SE_GENI_S_CMD0);
}

/**
 * geni_se_cancel_m_cmd() - Cancel the command configured in the primary
 *                          sequencer
 * @se:	Pointer to the concerned serial engine.
 *
 * This function is used to cancel the currently configured command in the
 * primary sequencer.
 */
static inline void geni_se_cancel_m_cmd(struct geni_se *se)
{
	writel_relaxed(M_GENI_CMD_CANCEL, se->base + SE_GENI_M_CMD_CTRL_REG);
}

/**
 * geni_se_cancel_s_cmd() - Cancel the command configured in the secondary
 *                          sequencer
 * @se:	Pointer to the concerned serial engine.
 *
 * This function is used to cancel the currently configured command in the
 * secondary sequencer.
 */
static inline void geni_se_cancel_s_cmd(struct geni_se *se)
{
	writel_relaxed(S_GENI_CMD_CANCEL, se->base + SE_GENI_S_CMD_CTRL_REG);
}

/**
 * geni_se_abort_m_cmd() - Abort the command configured in the primary sequencer
 * @se:	Pointer to the concerned serial engine.
 *
 * This function is used to force abort the currently configured command in the
 * primary sequencer.
 */
static inline void geni_se_abort_m_cmd(struct geni_se *se)
{
	writel_relaxed(M_GENI_CMD_ABORT, se->base + SE_GENI_M_CMD_CTRL_REG);
}

/**
 * geni_se_abort_s_cmd() - Abort the command configured in the secondary
 *                         sequencer
 * @se:	Pointer to the concerned serial engine.
 *
 * This function is used to force abort the currently configured command in the
 * secondary sequencer.
 */
static inline void geni_se_abort_s_cmd(struct geni_se *se)
{
	writel_relaxed(S_GENI_CMD_ABORT, se->base + SE_GENI_S_CMD_CTRL_REG);
}

/**
 * geni_se_get_tx_fifo_depth() - Get the TX fifo depth of the serial engine
 * @se:	Pointer to the concerned serial engine.
 *
 * This function is used to get the depth i.e. number of elements in the
 * TX fifo of the serial engine.
 *
 * Return: TX fifo depth in units of FIFO words.
 */
static inline u32 geni_se_get_tx_fifo_depth(struct geni_se *se)
{
	u32 val;

	val = readl_relaxed(se->base + SE_HW_PARAM_0);

	return (val & TX_FIFO_DEPTH_MSK) >> TX_FIFO_DEPTH_SHFT;
}

/**
 * geni_se_get_tx_fifo_width() - Get the TX fifo width of the serial engine
 * @se:	Pointer to the concerned serial engine.
 *
 * This function is used to get the width i.e. word size per element in the
 * TX fifo of the serial engine.
 *
 * Return: TX fifo width in bits
 */
static inline u32 geni_se_get_tx_fifo_width(struct geni_se *se)
{
	u32 val;

	val = readl_relaxed(se->base + SE_HW_PARAM_0);

	return (val & TX_FIFO_WIDTH_MSK) >> TX_FIFO_WIDTH_SHFT;
}

/**
 * geni_se_get_rx_fifo_depth() - Get the RX fifo depth of the serial engine
 * @se:	Pointer to the concerned serial engine.
 *
 * This function is used to get the depth i.e. number of elements in the
 * RX fifo of the serial engine.
 *
 * Return: RX fifo depth in units of FIFO words
 */
static inline u32 geni_se_get_rx_fifo_depth(struct geni_se *se)
{
	u32 val;

	val = readl_relaxed(se->base + SE_HW_PARAM_1);

	return (val & RX_FIFO_DEPTH_MSK) >> RX_FIFO_DEPTH_SHFT;
}

void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr);

void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode);

void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words,
			    bool msb_to_lsb, bool tx_cfg, bool rx_cfg);

int geni_se_resources_off(struct geni_se *se);

int geni_se_resources_on(struct geni_se *se);

int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl);

int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq,
			   unsigned int *index, unsigned long *res_freq,
			   bool exact);

int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len,
			dma_addr_t *iova);

int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len,
			dma_addr_t *iova);

void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);

void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);
#endif
#endif
Commit	Line	Data
eddac5af KR	1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
	2	/*
	3	* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
	4	*/
	5
	6	#ifndef _LINUX_QCOM_GENI_SE
	7	#define _LINUX_QCOM_GENI_SE
	8
	9	/* Transfer mode supported by GENI Serial Engines */
	10	enum geni_se_xfer_mode {
	11	GENI_SE_INVALID,
	12	GENI_SE_FIFO,
	13	GENI_SE_DMA,
	14	};
	15
	16	/* Protocols supported by GENI Serial Engines */
	17	enum geni_se_protocol_type {
	18	GENI_SE_NONE,
	19	GENI_SE_SPI,
	20	GENI_SE_UART,
	21	GENI_SE_I2C,
	22	GENI_SE_I3C,
	23	};
	24
	25	struct geni_wrapper;
	26	struct clk;
	27
	28	/**
	29	* struct geni_se - GENI Serial Engine
	30	* @base: Base Address of the Serial Engine's register block
	31	* @dev: Pointer to the Serial Engine device
	32	* @wrapper: Pointer to the parent QUP Wrapper core
	33	* @clk: Handle to the core serial engine clock
	34	* @num_clk_levels: Number of valid clock levels in clk_perf_tbl
	35	* @clk_perf_tbl: Table of clock frequency input to serial engine clock
	36	*/
	37	struct geni_se {
	38	void __iomem *base;
	39	struct device *dev;
	40	struct geni_wrapper *wrapper;
	41	struct clk *clk;
	42	unsigned int num_clk_levels;
	43	unsigned long *clk_perf_tbl;
	44	};
	45
	46	/* Common SE registers */
	47	#define GENI_FORCE_DEFAULT_REG 0x20
	48	#define SE_GENI_STATUS 0x40
	49	#define GENI_SER_M_CLK_CFG 0x48
	50	#define GENI_SER_S_CLK_CFG 0x4c
	51	#define GENI_FW_REVISION_RO 0x68
	52	#define SE_GENI_CLK_SEL 0x7c
	53	#define SE_GENI_DMA_MODE_EN 0x258
	54	#define SE_GENI_M_CMD0 0x600
	55	#define SE_GENI_M_CMD_CTRL_REG 0x604
	56	#define SE_GENI_M_IRQ_STATUS 0x610
	57	#define SE_GENI_M_IRQ_EN 0x614
	58	#define SE_GENI_M_IRQ_CLEAR 0x618
	59	#define SE_GENI_S_CMD0 0x630
	60	#define SE_GENI_S_CMD_CTRL_REG 0x634
	61	#define SE_GENI_S_IRQ_STATUS 0x640
	62	#define SE_GENI_S_IRQ_EN 0x644
	63	#define SE_GENI_S_IRQ_CLEAR 0x648
	64	#define SE_GENI_TX_FIFOn 0x700
65	#define SE_GENI_RX_FIFOn 0x780
66	#define SE_GENI_TX_FIFO_STATUS 0x800
67	#define SE_GENI_RX_FIFO_STATUS 0x804
68	#define SE_GENI_TX_WATERMARK_REG 0x80c
69	#define SE_GENI_RX_WATERMARK_REG 0x810
70	#define SE_GENI_RX_RFR_WATERMARK_REG 0x814
71	#define SE_GENI_IOS 0x908
72	#define SE_DMA_TX_IRQ_STAT 0xc40
73	#define SE_DMA_TX_IRQ_CLR 0xc44
74	#define SE_DMA_TX_FSM_RST 0xc58
75	#define SE_DMA_RX_IRQ_STAT 0xd40
76	#define SE_DMA_RX_IRQ_CLR 0xd44
77	#define SE_DMA_RX_FSM_RST 0xd58
78	#define SE_HW_PARAM_0 0xe24
79	#define SE_HW_PARAM_1 0xe28
80
81	/* GENI_FORCE_DEFAULT_REG fields */
82	#define FORCE_DEFAULT BIT(0)
83
84	/* GENI_STATUS fields */
85	#define M_GENI_CMD_ACTIVE BIT(0)
86	#define S_GENI_CMD_ACTIVE BIT(12)
87
88	/* GENI_SER_M_CLK_CFG/GENI_SER_S_CLK_CFG */
89	#define SER_CLK_EN BIT(0)
90	#define CLK_DIV_MSK GENMASK(15, 4)
91	#define CLK_DIV_SHFT 4
92
93	/* GENI_FW_REVISION_RO fields */
94	#define FW_REV_PROTOCOL_MSK GENMASK(15, 8)
95	#define FW_REV_PROTOCOL_SHFT 8
96
97	/* GENI_CLK_SEL fields */
98	#define CLK_SEL_MSK GENMASK(2, 0)
99
100	/* SE_GENI_DMA_MODE_EN */
101	#define GENI_DMA_MODE_EN BIT(0)
102
103	/* GENI_M_CMD0 fields */
104	#define M_OPCODE_MSK GENMASK(31, 27)
105	#define M_OPCODE_SHFT 27
106	#define M_PARAMS_MSK GENMASK(26, 0)
107
108	/* GENI_M_CMD_CTRL_REG */
109	#define M_GENI_CMD_CANCEL BIT(2)
110	#define M_GENI_CMD_ABORT BIT(1)
111	#define M_GENI_DISABLE BIT(0)
112
113	/* GENI_S_CMD0 fields */
114	#define S_OPCODE_MSK GENMASK(31, 27)
115	#define S_OPCODE_SHFT 27
116	#define S_PARAMS_MSK GENMASK(26, 0)
117
118	/* GENI_S_CMD_CTRL_REG */
119	#define S_GENI_CMD_CANCEL BIT(2)
120	#define S_GENI_CMD_ABORT BIT(1)
121	#define S_GENI_DISABLE BIT(0)
122
123	/* GENI_M_IRQ_EN fields */
124	#define M_CMD_DONE_EN BIT(0)
125	#define M_CMD_OVERRUN_EN BIT(1)
126	#define M_ILLEGAL_CMD_EN BIT(2)
127	#define M_CMD_FAILURE_EN BIT(3)
128	#define M_CMD_CANCEL_EN BIT(4)
129	#define M_CMD_ABORT_EN BIT(5)
130	#define M_TIMESTAMP_EN BIT(6)
131	#define M_RX_IRQ_EN BIT(7)
132	#define M_GP_SYNC_IRQ_0_EN BIT(8)
133	#define M_GP_IRQ_0_EN BIT(9)
134	#define M_GP_IRQ_1_EN BIT(10)
135	#define M_GP_IRQ_2_EN BIT(11)
136	#define M_GP_IRQ_3_EN BIT(12)
137	#define M_GP_IRQ_4_EN BIT(13)
138	#define M_GP_IRQ_5_EN BIT(14)
139	#define M_IO_DATA_DEASSERT_EN BIT(22)
140	#define M_IO_DATA_ASSERT_EN BIT(23)
141	#define M_RX_FIFO_RD_ERR_EN BIT(24)
142	#define M_RX_FIFO_WR_ERR_EN BIT(25)
143	#define M_RX_FIFO_WATERMARK_EN BIT(26)
144	#define M_RX_FIFO_LAST_EN BIT(27)
145	#define M_TX_FIFO_RD_ERR_EN BIT(28)
146	#define M_TX_FIFO_WR_ERR_EN BIT(29)
147	#define M_TX_FIFO_WATERMARK_EN BIT(30)
148	#define M_SEC_IRQ_EN BIT(31)
149	#define M_COMMON_GENI_M_IRQ_EN (GENMASK(6, 1) \| \
150	M_IO_DATA_DEASSERT_EN \| \
151	M_IO_DATA_ASSERT_EN \| M_RX_FIFO_RD_ERR_EN \| \
152	M_RX_FIFO_WR_ERR_EN \| M_TX_FIFO_RD_ERR_EN \| \
153	M_TX_FIFO_WR_ERR_EN)
154
155	/* GENI_S_IRQ_EN fields */
156	#define S_CMD_DONE_EN BIT(0)
157	#define S_CMD_OVERRUN_EN BIT(1)
158	#define S_ILLEGAL_CMD_EN BIT(2)
159	#define S_CMD_FAILURE_EN BIT(3)
160	#define S_CMD_CANCEL_EN BIT(4)
161	#define S_CMD_ABORT_EN BIT(5)
162	#define S_GP_SYNC_IRQ_0_EN BIT(8)
163	#define S_GP_IRQ_0_EN BIT(9)
164	#define S_GP_IRQ_1_EN BIT(10)
165	#define S_GP_IRQ_2_EN BIT(11)
166	#define S_GP_IRQ_3_EN BIT(12)
167	#define S_GP_IRQ_4_EN BIT(13)
168	#define S_GP_IRQ_5_EN BIT(14)
169	#define S_IO_DATA_DEASSERT_EN BIT(22)
170	#define S_IO_DATA_ASSERT_EN BIT(23)
171	#define S_RX_FIFO_RD_ERR_EN BIT(24)
172	#define S_RX_FIFO_WR_ERR_EN BIT(25)
173	#define S_RX_FIFO_WATERMARK_EN BIT(26)
174	#define S_RX_FIFO_LAST_EN BIT(27)
175	#define S_COMMON_GENI_S_IRQ_EN (GENMASK(5, 1) \| GENMASK(13, 9) \| \
176	S_RX_FIFO_RD_ERR_EN \| S_RX_FIFO_WR_ERR_EN)
177
178	/* GENI_/TX/RX/RX_RFR/_WATERMARK_REG fields */
179	#define WATERMARK_MSK GENMASK(5, 0)
180
181	/* GENI_TX_FIFO_STATUS fields */
182	#define TX_FIFO_WC GENMASK(27, 0)
183
184	/* GENI_RX_FIFO_STATUS fields */
185	#define RX_LAST BIT(31)
186	#define RX_LAST_BYTE_VALID_MSK GENMASK(30, 28)
187	#define RX_LAST_BYTE_VALID_SHFT 28
188	#define RX_FIFO_WC_MSK GENMASK(24, 0)
189
190	/* SE_GENI_IOS fields */
191	#define IO2_DATA_IN BIT(1)
192	#define RX_DATA_IN BIT(0)
193
194	/* SE_DMA_TX_IRQ_STAT Register fields */
195	#define TX_DMA_DONE BIT(0)
196	#define TX_EOT BIT(1)
197	#define TX_SBE BIT(2)
198	#define TX_RESET_DONE BIT(3)
199
200	/* SE_DMA_RX_IRQ_STAT Register fields */
201	#define RX_DMA_DONE BIT(0)
202	#define RX_EOT BIT(1)
203	#define RX_SBE BIT(2)
204	#define RX_RESET_DONE BIT(3)
205	#define RX_FLUSH_DONE BIT(4)
206	#define RX_GENI_GP_IRQ GENMASK(10, 5)
207	#define RX_GENI_CANCEL_IRQ BIT(11)
208	#define RX_GENI_GP_IRQ_EXT GENMASK(13, 12)
209
210	/* SE_HW_PARAM_0 fields */
211	#define TX_FIFO_WIDTH_MSK GENMASK(29, 24)
212	#define TX_FIFO_WIDTH_SHFT 24
213	#define TX_FIFO_DEPTH_MSK GENMASK(21, 16)
214	#define TX_FIFO_DEPTH_SHFT 16
215
216	/* SE_HW_PARAM_1 fields */
217	#define RX_FIFO_WIDTH_MSK GENMASK(29, 24)
218	#define RX_FIFO_WIDTH_SHFT 24
219	#define RX_FIFO_DEPTH_MSK GENMASK(21, 16)
220	#define RX_FIFO_DEPTH_SHFT 16
221
222	#define HW_VER_MAJOR_MASK GENMASK(31, 28)
223	#define HW_VER_MAJOR_SHFT 28
224	#define HW_VER_MINOR_MASK GENMASK(27, 16)
225	#define HW_VER_MINOR_SHFT 16
226	#define HW_VER_STEP_MASK GENMASK(15, 0)
227
65a27264 SB	228	#define GENI_SE_VERSION_MAJOR(ver) ((ver & HW_VER_MAJOR_MASK) >> HW_VER_MAJOR_SHFT)
	229	#define GENI_SE_VERSION_MINOR(ver) ((ver & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT)
	230	#define GENI_SE_VERSION_STEP(ver) (ver & HW_VER_STEP_MASK)
	231
eddac5af KR	232	#if IS_ENABLED(CONFIG_QCOM_GENI_SE)
	233
	234	u32 geni_se_get_qup_hw_version(struct geni_se *se);
	235
eddac5af KR	236	/**
	237	* geni_se_read_proto() - Read the protocol configured for a serial engine
	238	* @se: Pointer to the concerned serial engine.
	239	*
	240	* Return: Protocol value as configured in the serial engine.
	241	*/
	242	static inline u32 geni_se_read_proto(struct geni_se *se)
	243	{
	244	u32 val;
	245
	246	val = readl_relaxed(se->base + GENI_FW_REVISION_RO);
	247
	248	return (val & FW_REV_PROTOCOL_MSK) >> FW_REV_PROTOCOL_SHFT;
	249	}
	250
	251	/**
	252	* geni_se_setup_m_cmd() - Setup the primary sequencer
	253	* @se: Pointer to the concerned serial engine.
	254	* @cmd: Command/Operation to setup in the primary sequencer.
	255	* @params: Parameter for the sequencer command.
	256	*
	257	* This function is used to configure the primary sequencer with the
	258	* command and its associated parameters.
	259	*/
	260	static inline void geni_se_setup_m_cmd(struct geni_se *se, u32 cmd, u32 params)
	261	{
	262	u32 m_cmd;
	263
	264	m_cmd = (cmd << M_OPCODE_SHFT) \| (params & M_PARAMS_MSK);
	265	writel_relaxed(m_cmd, se->base + SE_GENI_M_CMD0);
	266	}
	267
	268	/**
	269	* geni_se_setup_s_cmd() - Setup the secondary sequencer
	270	* @se: Pointer to the concerned serial engine.
	271	* @cmd: Command/Operation to setup in the secondary sequencer.
	272	* @params: Parameter for the sequencer command.
	273	*
	274	* This function is used to configure the secondary sequencer with the
	275	* command and its associated parameters.
	276	*/
	277	static inline void geni_se_setup_s_cmd(struct geni_se *se, u32 cmd, u32 params)
	278	{
	279	u32 s_cmd;
	280
	281	s_cmd = readl_relaxed(se->base + SE_GENI_S_CMD0);
	282	s_cmd &= ~(S_OPCODE_MSK \| S_PARAMS_MSK);
	283	s_cmd \|= (cmd << S_OPCODE_SHFT);
	284	s_cmd \|= (params & S_PARAMS_MSK);
	285	writel_relaxed(s_cmd, se->base + SE_GENI_S_CMD0);
	286	}
	287
	288	/**
	289	* geni_se_cancel_m_cmd() - Cancel the command configured in the primary
	290	* sequencer
	291	* @se: Pointer to the concerned serial engine.
	292	*
	293	* This function is used to cancel the currently configured command in the
	294	* primary sequencer.
	295	*/
	296	static inline void geni_se_cancel_m_cmd(struct geni_se *se)
	297	{
	298	writel_relaxed(M_GENI_CMD_CANCEL, se->base + SE_GENI_M_CMD_CTRL_REG);
	299	}
300
301	/**
302	* geni_se_cancel_s_cmd() - Cancel the command configured in the secondary
303	* sequencer
304	* @se: Pointer to the concerned serial engine.
305	*
306	* This function is used to cancel the currently configured command in the
307	* secondary sequencer.
308	*/
309	static inline void geni_se_cancel_s_cmd(struct geni_se *se)
310	{
311	writel_relaxed(S_GENI_CMD_CANCEL, se->base + SE_GENI_S_CMD_CTRL_REG);
312	}
313
314	/**
315	* geni_se_abort_m_cmd() - Abort the command configured in the primary sequencer
316	* @se: Pointer to the concerned serial engine.
317	*
318	* This function is used to force abort the currently configured command in the
319	* primary sequencer.
320	*/
321	static inline void geni_se_abort_m_cmd(struct geni_se *se)
322	{
323	writel_relaxed(M_GENI_CMD_ABORT, se->base + SE_GENI_M_CMD_CTRL_REG);
324	}
325
326	/**
327	* geni_se_abort_s_cmd() - Abort the command configured in the secondary
328	* sequencer
329	* @se: Pointer to the concerned serial engine.
330	*
331	* This function is used to force abort the currently configured command in the
332	* secondary sequencer.
333	*/
334	static inline void geni_se_abort_s_cmd(struct geni_se *se)
335	{
336	writel_relaxed(S_GENI_CMD_ABORT, se->base + SE_GENI_S_CMD_CTRL_REG);
337	}
338
339	/**
340	* geni_se_get_tx_fifo_depth() - Get the TX fifo depth of the serial engine
341	* @se: Pointer to the concerned serial engine.
342	*
343	* This function is used to get the depth i.e. number of elements in the
344	* TX fifo of the serial engine.
345	*
346	* Return: TX fifo depth in units of FIFO words.
347	*/
348	static inline u32 geni_se_get_tx_fifo_depth(struct geni_se *se)
349	{
350	u32 val;
351
352	val = readl_relaxed(se->base + SE_HW_PARAM_0);
353
354	return (val & TX_FIFO_DEPTH_MSK) >> TX_FIFO_DEPTH_SHFT;
355	}
356
357	/**
358	* geni_se_get_tx_fifo_width() - Get the TX fifo width of the serial engine
359	* @se: Pointer to the concerned serial engine.
360	*
361	* This function is used to get the width i.e. word size per element in the
362	* TX fifo of the serial engine.
363	*
364	* Return: TX fifo width in bits
365	*/
366	static inline u32 geni_se_get_tx_fifo_width(struct geni_se *se)
367	{
368	u32 val;
369
370	val = readl_relaxed(se->base + SE_HW_PARAM_0);
371
372	return (val & TX_FIFO_WIDTH_MSK) >> TX_FIFO_WIDTH_SHFT;
373	}
374
375	/**
376	* geni_se_get_rx_fifo_depth() - Get the RX fifo depth of the serial engine
377	* @se: Pointer to the concerned serial engine.
378	*
379	* This function is used to get the depth i.e. number of elements in the
380	* RX fifo of the serial engine.
381	*
382	* Return: RX fifo depth in units of FIFO words
383	*/
384	static inline u32 geni_se_get_rx_fifo_depth(struct geni_se *se)
385	{
386	u32 val;
387
388	val = readl_relaxed(se->base + SE_HW_PARAM_1);
389
390	return (val & RX_FIFO_DEPTH_MSK) >> RX_FIFO_DEPTH_SHFT;
391	}
392
393	void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr);
394
395	void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode);
396
397	void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words,
398	bool msb_to_lsb, bool tx_cfg, bool rx_cfg);
399
400	int geni_se_resources_off(struct geni_se *se);
401
402	int geni_se_resources_on(struct geni_se *se);
403
404	int geni_se_clk_tbl_get(struct geni_se se, unsigned long *tbl);
405
406	int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq,
407	unsigned int index, unsigned long res_freq,
408	bool exact);
409
410	int geni_se_tx_dma_prep(struct geni_se se, void buf, size_t len,
411	dma_addr_t *iova);
412
413	int geni_se_rx_dma_prep(struct geni_se se, void buf, size_t len,
414	dma_addr_t *iova);
415
416	void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);
417
418	void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);
419	#endif
420	#endif