Commit | Line | Data |
---|---|---|
d2912cb1 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
1da177e4 | 2 | /* |
8083d6b8 | 3 | * Copyright (C) 2003 Russell King, All Rights Reserved. |
1da177e4 | 4 | * |
1da177e4 LT |
5 | * This driver supports the following PXA CPU/SSP ports:- |
6 | * | |
7 | * PXA250 SSP | |
8 | * PXA255 SSP, NSSP | |
9 | * PXA26x SSP, NSSP, ASSP | |
10 | * PXA27x SSP1, SSP2, SSP3 | |
88286450 | 11 | * PXA3xx SSP1, SSP2, SSP3, SSP4 |
1da177e4 LT |
12 | */ |
13 | ||
5edc2490 AS |
14 | #ifndef __LINUX_PXA2XX_SSP_H |
15 | #define __LINUX_PXA2XX_SSP_H | |
88286450 | 16 | |
410f4cf7 | 17 | #include <linux/bits.h> |
e7aaf874 | 18 | #include <linux/compiler_types.h> |
63bef547 | 19 | #include <linux/io.h> |
e7aaf874 AS |
20 | #include <linux/kconfig.h> |
21 | #include <linux/list.h> | |
22 | #include <linux/types.h> | |
6446221c | 23 | |
e7aaf874 AS |
24 | struct clk; |
25 | struct device; | |
26 | struct device_node; | |
88286450 | 27 | |
83f28896 EM |
28 | /* |
29 | * SSP Serial Port Registers | |
30 | * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different. | |
31 | * PXA255, PXA26x and PXA27x have extra ports, registers and bits. | |
32 | */ | |
33 | ||
34 | #define SSCR0 (0x00) /* SSP Control Register 0 */ | |
35 | #define SSCR1 (0x04) /* SSP Control Register 1 */ | |
36 | #define SSSR (0x08) /* SSP Status Register */ | |
37 | #define SSITR (0x0C) /* SSP Interrupt Test Register */ | |
38 | #define SSDR (0x10) /* SSP Data Write/Data Read Register */ | |
39 | ||
40 | #define SSTO (0x28) /* SSP Time Out Register */ | |
41 | #define SSPSP (0x2C) /* SSP Programmable Serial Protocol */ | |
42 | #define SSTSA (0x30) /* SSP Tx Timeslot Active */ | |
43 | #define SSRSA (0x34) /* SSP Rx Timeslot Active */ | |
44 | #define SSTSS (0x38) /* SSP Timeslot Status */ | |
45 | #define SSACD (0x3C) /* SSP Audio Clock Divider */ | |
83f28896 | 46 | #define SSACDD (0x40) /* SSP Audio Clock Dither Divider */ |
83f28896 EM |
47 | |
48 | /* Common PXA2xx bits first */ | |
410f4cf7 | 49 | #define SSCR0_DSS GENMASK(3, 0) /* Data Size Select (mask) */ |
83f28896 | 50 | #define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */ |
410f4cf7 | 51 | #define SSCR0_FRF GENMASK(5, 4) /* FRame Format (mask) */ |
83f28896 EM |
52 | #define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */ |
53 | #define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */ | |
54 | #define SSCR0_National (0x2 << 4) /* National Microwire */ | |
410f4cf7 AS |
55 | #define SSCR0_ECS BIT(6) /* External clock select */ |
56 | #define SSCR0_SSE BIT(7) /* Synchronous Serial Port Enable */ | |
83f28896 EM |
57 | #define SSCR0_SCR(x) ((x) << 8) /* Serial Clock Rate (mask) */ |
58 | ||
004690f0 | 59 | /* PXA27x, PXA3xx */ |
410f4cf7 AS |
60 | #define SSCR0_EDSS BIT(20) /* Extended data size select */ |
61 | #define SSCR0_NCS BIT(21) /* Network clock select */ | |
8083d6b8 | 62 | #define SSCR0_RIM BIT(22) /* Receive FIFO overrun interrupt mask */ |
410f4cf7 AS |
63 | #define SSCR0_TUM BIT(23) /* Transmit FIFO underrun interrupt mask */ |
64 | #define SSCR0_FRDC GENMASK(26, 24) /* Frame rate divider control (mask) */ | |
83f28896 | 65 | #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */ |
410f4cf7 AS |
66 | #define SSCR0_FPCKE BIT(29) /* FIFO packing enable */ |
67 | #define SSCR0_ACS BIT(30) /* Audio clock select */ | |
68 | #define SSCR0_MOD BIT(31) /* Mode (normal or network) */ | |
69 | ||
70 | #define SSCR1_RIE BIT(0) /* Receive FIFO Interrupt Enable */ | |
71 | #define SSCR1_TIE BIT(1) /* Transmit FIFO Interrupt Enable */ | |
72 | #define SSCR1_LBM BIT(2) /* Loop-Back Mode */ | |
73 | #define SSCR1_SPO BIT(3) /* Motorola SPI SSPSCLK polarity setting */ | |
74 | #define SSCR1_SPH BIT(4) /* Motorola SPI SSPSCLK phase setting */ | |
75 | #define SSCR1_MWDS BIT(5) /* Microwire Transmit Data Size */ | |
76 | ||
77 | #define SSSR_ALT_FRM_MASK GENMASK(1, 0) /* Masks the SFRM signal number */ | |
78 | #define SSSR_TNF BIT(2) /* Transmit FIFO Not Full */ | |
79 | #define SSSR_RNE BIT(3) /* Receive FIFO Not Empty */ | |
80 | #define SSSR_BSY BIT(4) /* SSP Busy */ | |
81 | #define SSSR_TFS BIT(5) /* Transmit FIFO Service Request */ | |
82 | #define SSSR_RFS BIT(6) /* Receive FIFO Service Request */ | |
83 | #define SSSR_ROR BIT(7) /* Receive FIFO Overrun */ | |
d0777f2c | 84 | |
d0777f2c SAS |
85 | #define RX_THRESH_DFLT 8 |
86 | #define TX_THRESH_DFLT 8 | |
87 | ||
410f4cf7 AS |
88 | #define SSSR_TFL_MASK GENMASK(11, 8) /* Transmit FIFO Level mask */ |
89 | #define SSSR_RFL_MASK GENMASK(15, 12) /* Receive FIFO Level mask */ | |
d0777f2c | 90 | |
410f4cf7 | 91 | #define SSCR1_TFT GENMASK(9, 6) /* Transmit FIFO Threshold (mask) */ |
63971c56 | 92 | #define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */ |
410f4cf7 | 93 | #define SSCR1_RFT GENMASK(13, 10) /* Receive FIFO Threshold (mask) */ |
63971c56 | 94 | #define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */ |
d0777f2c | 95 | |
7c7289a4 AS |
96 | #define RX_THRESH_CE4100_DFLT 2 |
97 | #define TX_THRESH_CE4100_DFLT 2 | |
d0777f2c | 98 | |
410f4cf7 AS |
99 | #define CE4100_SSSR_TFL_MASK GENMASK(9, 8) /* Transmit FIFO Level mask */ |
100 | #define CE4100_SSSR_RFL_MASK GENMASK(13, 12) /* Receive FIFO Level mask */ | |
d0777f2c | 101 | |
410f4cf7 | 102 | #define CE4100_SSCR1_TFT GENMASK(7, 6) /* Transmit FIFO Threshold (mask) */ |
7c7289a4 | 103 | #define CE4100_SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..4] */ |
410f4cf7 | 104 | #define CE4100_SSCR1_RFT GENMASK(11, 10) /* Receive FIFO Threshold (mask) */ |
7c7289a4 | 105 | #define CE4100_SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..4] */ |
83f28896 | 106 | |
1beb37b0 AS |
107 | /* Intel Quark X1000 */ |
108 | #define DDS_RATE 0x28 /* SSP DDS Clock Rate Register */ | |
109 | ||
e5262d05 | 110 | /* QUARK_X1000 SSCR0 bit definition */ |
410f4cf7 | 111 | #define QUARK_X1000_SSCR0_DSS GENMASK(4, 0) /* Data Size Select (mask) */ |
63971c56 | 112 | #define QUARK_X1000_SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..32] */ |
410f4cf7 | 113 | #define QUARK_X1000_SSCR0_FRF GENMASK(6, 5) /* FRame Format (mask) */ |
e5262d05 WC |
114 | #define QUARK_X1000_SSCR0_Motorola (0x0 << 5) /* Motorola's Serial Peripheral Interface (SPI) */ |
115 | ||
116 | #define RX_THRESH_QUARK_X1000_DFLT 1 | |
117 | #define TX_THRESH_QUARK_X1000_DFLT 16 | |
118 | ||
410f4cf7 AS |
119 | #define QUARK_X1000_SSSR_TFL_MASK GENMASK(12, 8) /* Transmit FIFO Level mask */ |
120 | #define QUARK_X1000_SSSR_RFL_MASK GENMASK(17, 13) /* Receive FIFO Level mask */ | |
e5262d05 | 121 | |
410f4cf7 | 122 | #define QUARK_X1000_SSCR1_TFT GENMASK(10, 6) /* Transmit FIFO Threshold (mask) */ |
e5262d05 | 123 | #define QUARK_X1000_SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..32] */ |
410f4cf7 | 124 | #define QUARK_X1000_SSCR1_RFT GENMASK(15, 11) /* Receive FIFO Threshold (mask) */ |
e5262d05 | 125 | #define QUARK_X1000_SSCR1_RxTresh(x) (((x) - 1) << 11) /* level [1..32] */ |
410f4cf7 AS |
126 | #define QUARK_X1000_SSCR1_EFWR BIT(16) /* Enable FIFO Write/Read */ |
127 | #define QUARK_X1000_SSCR1_STRF BIT(17) /* Select FIFO or EFWR */ | |
e5262d05 | 128 | |
8083d6b8 | 129 | /* Extra bits in PXA255, PXA26x and PXA27x SSP ports */ |
83f28896 EM |
130 | #define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */ |
131 | #define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */ | |
83f28896 | 132 | |
410f4cf7 AS |
133 | #define SSCR1_EFWR BIT(14) /* Enable FIFO Write/Read */ |
134 | #define SSCR1_STRF BIT(15) /* Select FIFO or EFWR */ | |
135 | #define SSCR1_IFS BIT(16) /* Invert Frame Signal */ | |
136 | #define SSCR1_PINTE BIT(18) /* Peripheral Trailing Byte Interrupt Enable */ | |
137 | #define SSCR1_TINTE BIT(19) /* Receiver Time-out Interrupt enable */ | |
138 | #define SSCR1_RSRE BIT(20) /* Receive Service Request Enable */ | |
139 | #define SSCR1_TSRE BIT(21) /* Transmit Service Request Enable */ | |
140 | #define SSCR1_TRAIL BIT(22) /* Trailing Byte */ | |
141 | #define SSCR1_RWOT BIT(23) /* Receive Without Transmit */ | |
142 | #define SSCR1_SFRMDIR BIT(24) /* Frame Direction */ | |
143 | #define SSCR1_SCLKDIR BIT(25) /* Serial Bit Rate Clock Direction */ | |
144 | #define SSCR1_ECRB BIT(26) /* Enable Clock request B */ | |
145 | #define SSCR1_ECRA BIT(27) /* Enable Clock Request A */ | |
146 | #define SSCR1_SCFR BIT(28) /* Slave Clock free Running */ | |
147 | #define SSCR1_EBCEI BIT(29) /* Enable Bit Count Error interrupt */ | |
148 | #define SSCR1_TTE BIT(30) /* TXD Tristate Enable */ | |
149 | #define SSCR1_TTELP BIT(31) /* TXD Tristate Enable Last Phase */ | |
150 | ||
151 | #define SSSR_PINT BIT(18) /* Peripheral Trailing Byte Interrupt */ | |
152 | #define SSSR_TINT BIT(19) /* Receiver Time-out Interrupt */ | |
153 | #define SSSR_EOC BIT(20) /* End Of Chain */ | |
154 | #define SSSR_TUR BIT(21) /* Transmit FIFO Under Run */ | |
155 | #define SSSR_CSS BIT(22) /* Clock Synchronisation Status */ | |
156 | #define SSSR_BCE BIT(23) /* Bit Count Error */ | |
83f28896 | 157 | |
83f28896 | 158 | #define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */ |
410f4cf7 AS |
159 | #define SSPSP_SFRMP BIT(2) /* Serial Frame Polarity */ |
160 | #define SSPSP_ETDS BIT(3) /* End of Transfer data State */ | |
004690f0 HZ |
161 | #define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */ |
162 | #define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */ | |
163 | #define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */ | |
164 | #define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */ | |
165 | #define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */ | |
410f4cf7 | 166 | #define SSPSP_FSRT BIT(25) /* Frame Sync Relative Timing */ |
004690f0 HZ |
167 | |
168 | /* PXA3xx */ | |
169 | #define SSPSP_EDMYSTRT(x) ((x) << 26) /* Extended Dummy Start */ | |
170 | #define SSPSP_EDMYSTOP(x) ((x) << 28) /* Extended Dummy Stop */ | |
171 | #define SSPSP_TIMING_MASK (0x7f8001f0) | |
83f28896 | 172 | |
83f28896 | 173 | #define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */ |
05739375 DM |
174 | #define SSACD_ACDS_1 (0) |
175 | #define SSACD_ACDS_2 (1) | |
176 | #define SSACD_ACDS_4 (2) | |
177 | #define SSACD_ACDS_8 (3) | |
178 | #define SSACD_ACDS_16 (4) | |
179 | #define SSACD_ACDS_32 (5) | |
410f4cf7 | 180 | #define SSACD_SCDB BIT(3) /* SSPSYSCLK Divider Bypass */ |
05739375 DM |
181 | #define SSACD_SCDB_4X (0) |
182 | #define SSACD_SCDB_1X (1) | |
410f4cf7 AS |
183 | #define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */ |
184 | #define SSACD_SCDX8 BIT(7) /* SYSCLK division ratio select */ | |
83f28896 | 185 | |
3fdb59cf AS |
186 | /* Intel Merrifield SSP */ |
187 | #define SFIFOL 0x68 /* FIFO level */ | |
188 | #define SFIFOTT 0x6c /* FIFO trigger threshold */ | |
189 | ||
190 | #define RX_THRESH_MRFLD_DFLT 16 | |
191 | #define TX_THRESH_MRFLD_DFLT 16 | |
192 | ||
193 | #define SFIFOL_TFL_MASK GENMASK(15, 0) /* Transmit FIFO Level mask */ | |
194 | #define SFIFOL_RFL_MASK GENMASK(31, 16) /* Receive FIFO Level mask */ | |
195 | ||
196 | #define SFIFOTT_TFT GENMASK(15, 0) /* Transmit FIFO Threshold (mask) */ | |
197 | #define SFIFOTT_TxThresh(x) (((x) - 1) << 0) /* TX FIFO trigger threshold / level */ | |
198 | #define SFIFOTT_RFT GENMASK(31, 16) /* Receive FIFO Threshold (mask) */ | |
199 | #define SFIFOTT_RxThresh(x) (((x) - 1) << 16) /* RX FIFO trigger threshold / level */ | |
200 | ||
a0d2642e MW |
201 | /* LPSS SSP */ |
202 | #define SSITF 0x44 /* TX FIFO trigger level */ | |
410f4cf7 | 203 | #define SSITF_TxHiThresh(x) (((x) - 1) << 0) |
a0d2642e | 204 | #define SSITF_TxLoThresh(x) (((x) - 1) << 8) |
a0d2642e MW |
205 | |
206 | #define SSIRF 0x48 /* RX FIFO trigger level */ | |
207 | #define SSIRF_RxThresh(x) ((x) - 1) | |
208 | ||
a2bee00c CR |
209 | /* LPT/WPT SSP */ |
210 | #define SSCR2 (0x40) /* SSP Command / Status 2 */ | |
211 | #define SSPSP2 (0x44) /* SSP Programmable Serial Protocol 2 */ | |
212 | ||
88286450 | 213 | enum pxa_ssp_type { |
214 | SSP_UNDEFINED = 0, | |
215 | PXA25x_SSP, /* pxa 210, 250, 255, 26x */ | |
216 | PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */ | |
217 | PXA27x_SSP, | |
972a55b6 | 218 | PXA3xx_SSP, |
7e499228 | 219 | PXA168_SSP, |
87ae1d2d | 220 | MMP2_SSP, |
60172215 | 221 | PXA910_SSP, |
2a8626a9 | 222 | CE4100_SSP, |
3fdb59cf | 223 | MRFLD_SSP, |
e5262d05 | 224 | QUARK_X1000_SSP, |
8083d6b8 AS |
225 | /* Keep LPSS types sorted with lpss_platforms[] */ |
226 | LPSS_LPT_SSP, | |
03fbf488 | 227 | LPSS_BYT_SSP, |
30f3a6ab | 228 | LPSS_BSW_SSP, |
34cadd9c | 229 | LPSS_SPT_SSP, |
b7c08cf8 | 230 | LPSS_BXT_SSP, |
fc0b2acc | 231 | LPSS_CNL_SSP, |
88286450 | 232 | }; |
233 | ||
234 | struct ssp_device { | |
4f3d9577 | 235 | struct device *dev; |
88286450 | 236 | struct list_head node; |
237 | ||
238 | struct clk *clk; | |
239 | void __iomem *mmio_base; | |
240 | unsigned long phys_base; | |
241 | ||
242 | const char *label; | |
243 | int port_id; | |
55ef8262 | 244 | enum pxa_ssp_type type; |
88286450 | 245 | int use_count; |
246 | int irq; | |
6446221c DM |
247 | |
248 | struct device_node *of_node; | |
88286450 | 249 | }; |
1da177e4 | 250 | |
63bef547 | 251 | /** |
baffe169 | 252 | * pxa_ssp_write_reg - Write to a SSP register |
63bef547 MB |
253 | * |
254 | * @dev: SSP device to access | |
255 | * @reg: Register to write to | |
256 | * @val: Value to be written. | |
257 | */ | |
baffe169 | 258 | static inline void pxa_ssp_write_reg(struct ssp_device *dev, u32 reg, u32 val) |
63bef547 MB |
259 | { |
260 | __raw_writel(val, dev->mmio_base + reg); | |
261 | } | |
262 | ||
263 | /** | |
baffe169 | 264 | * pxa_ssp_read_reg - Read from a SSP register |
63bef547 MB |
265 | * |
266 | * @dev: SSP device to access | |
267 | * @reg: Register to read from | |
268 | */ | |
baffe169 | 269 | static inline u32 pxa_ssp_read_reg(struct ssp_device *dev, u32 reg) |
63bef547 MB |
270 | { |
271 | return __raw_readl(dev->mmio_base + reg); | |
272 | } | |
273 | ||
0c8ccd8b AS |
274 | static inline void pxa_ssp_enable(struct ssp_device *ssp) |
275 | { | |
276 | u32 sscr0; | |
277 | ||
278 | sscr0 = pxa_ssp_read_reg(ssp, SSCR0) | SSCR0_SSE; | |
279 | pxa_ssp_write_reg(ssp, SSCR0, sscr0); | |
280 | } | |
281 | ||
282 | static inline void pxa_ssp_disable(struct ssp_device *ssp) | |
283 | { | |
284 | u32 sscr0; | |
285 | ||
286 | sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & ~SSCR0_SSE; | |
287 | pxa_ssp_write_reg(ssp, SSCR0, sscr0); | |
288 | } | |
289 | ||
1ced9a5b | 290 | #if IS_ENABLED(CONFIG_PXA_SSP) |
baffe169 HZ |
291 | struct ssp_device *pxa_ssp_request(int port, const char *label); |
292 | void pxa_ssp_free(struct ssp_device *); | |
6446221c DM |
293 | struct ssp_device *pxa_ssp_request_of(const struct device_node *of_node, |
294 | const char *label); | |
851bacf5 MW |
295 | #else |
296 | static inline struct ssp_device *pxa_ssp_request(int port, const char *label) | |
297 | { | |
298 | return NULL; | |
299 | } | |
6446221c DM |
300 | static inline struct ssp_device *pxa_ssp_request_of(const struct device_node *n, |
301 | const char *name) | |
302 | { | |
303 | return NULL; | |
304 | } | |
851bacf5 MW |
305 | static inline void pxa_ssp_free(struct ssp_device *ssp) {} |
306 | #endif | |
307 | ||
5edc2490 | 308 | #endif /* __LINUX_PXA2XX_SSP_H */ |