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e8db0be1 JP |
1 | #ifndef _LINUX_PM_QOS_H |
2 | #define _LINUX_PM_QOS_H | |
d82b3518 MG |
3 | /* interface for the pm_qos_power infrastructure of the linux kernel. |
4 | * | |
bf1db69f | 5 | * Mark Gross <mgross@linux.intel.com> |
d82b3518 | 6 | */ |
82f68251 | 7 | #include <linux/plist.h> |
d82b3518 MG |
8 | #include <linux/notifier.h> |
9 | #include <linux/miscdevice.h> | |
1a9a9152 | 10 | #include <linux/device.h> |
c4772d19 | 11 | #include <linux/workqueue.h> |
d82b3518 | 12 | |
d031e1de AF |
13 | enum { |
14 | PM_QOS_RESERVED = 0, | |
15 | PM_QOS_CPU_DMA_LATENCY, | |
16 | PM_QOS_NETWORK_LATENCY, | |
17 | PM_QOS_NETWORK_THROUGHPUT, | |
18 | ||
19 | /* insert new class ID */ | |
20 | PM_QOS_NUM_CLASSES, | |
21 | }; | |
d82b3518 | 22 | |
ae0fb4b7 RW |
23 | enum pm_qos_flags_status { |
24 | PM_QOS_FLAGS_UNDEFINED = -1, | |
25 | PM_QOS_FLAGS_NONE, | |
26 | PM_QOS_FLAGS_SOME, | |
27 | PM_QOS_FLAGS_ALL, | |
28 | }; | |
29 | ||
d82b3518 MG |
30 | #define PM_QOS_DEFAULT_VALUE -1 |
31 | ||
333c5ae9 TC |
32 | #define PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE (2000 * USEC_PER_SEC) |
33 | #define PM_QOS_NETWORK_LAT_DEFAULT_VALUE (2000 * USEC_PER_SEC) | |
34 | #define PM_QOS_NETWORK_THROUGHPUT_DEFAULT_VALUE 0 | |
91ff4cb8 | 35 | #define PM_QOS_DEV_LAT_DEFAULT_VALUE 0 |
333c5ae9 | 36 | |
e39473d0 RW |
37 | #define PM_QOS_FLAG_NO_POWER_OFF (1 << 0) |
38 | #define PM_QOS_FLAG_REMOTE_WAKEUP (1 << 1) | |
39 | ||
cc749986 JP |
40 | struct pm_qos_request { |
41 | struct plist_node node; | |
82f68251 | 42 | int pm_qos_class; |
c4772d19 | 43 | struct delayed_work work; /* for pm_qos_update_request_timeout */ |
82f68251 | 44 | }; |
d82b3518 | 45 | |
5efbe427 RW |
46 | struct pm_qos_flags_request { |
47 | struct list_head node; | |
48 | s32 flags; /* Do not change to 64 bit */ | |
49 | }; | |
50 | ||
ae0fb4b7 RW |
51 | enum dev_pm_qos_req_type { |
52 | DEV_PM_QOS_LATENCY = 1, | |
53 | DEV_PM_QOS_FLAGS, | |
54 | }; | |
55 | ||
91ff4cb8 | 56 | struct dev_pm_qos_request { |
ae0fb4b7 | 57 | enum dev_pm_qos_req_type type; |
021c870b RW |
58 | union { |
59 | struct plist_node pnode; | |
ae0fb4b7 | 60 | struct pm_qos_flags_request flr; |
021c870b | 61 | } data; |
91ff4cb8 JP |
62 | struct device *dev; |
63 | }; | |
64 | ||
4e1779ba JP |
65 | enum pm_qos_type { |
66 | PM_QOS_UNITIALIZED, | |
67 | PM_QOS_MAX, /* return the largest value */ | |
68 | PM_QOS_MIN /* return the smallest value */ | |
69 | }; | |
70 | ||
71 | /* | |
5efbe427 RW |
72 | * Note: The lockless read path depends on the CPU accessing target_value |
73 | * or effective_flags atomically. Atomic access is only guaranteed on all CPU | |
4e1779ba JP |
74 | * types linux supports for 32 bit quantites |
75 | */ | |
76 | struct pm_qos_constraints { | |
77 | struct plist_head list; | |
78 | s32 target_value; /* Do not change to 64 bit */ | |
79 | s32 default_value; | |
80 | enum pm_qos_type type; | |
81 | struct blocking_notifier_head *notifiers; | |
82 | }; | |
83 | ||
5efbe427 RW |
84 | struct pm_qos_flags { |
85 | struct list_head list; | |
86 | s32 effective_flags; /* Do not change to 64 bit */ | |
87 | }; | |
88 | ||
5f986c59 RW |
89 | struct dev_pm_qos { |
90 | struct pm_qos_constraints latency; | |
ae0fb4b7 | 91 | struct pm_qos_flags flags; |
e39473d0 RW |
92 | struct dev_pm_qos_request *latency_req; |
93 | struct dev_pm_qos_request *flags_req; | |
5f986c59 RW |
94 | }; |
95 | ||
abe98ec2 JP |
96 | /* Action requested to pm_qos_update_target */ |
97 | enum pm_qos_req_action { | |
98 | PM_QOS_ADD_REQ, /* Add a new request */ | |
99 | PM_QOS_UPDATE_REQ, /* Update an existing request */ | |
100 | PM_QOS_REMOVE_REQ /* Remove an existing request */ | |
101 | }; | |
102 | ||
91ff4cb8 JP |
103 | static inline int dev_pm_qos_request_active(struct dev_pm_qos_request *req) |
104 | { | |
83618092 | 105 | return req->dev != NULL; |
91ff4cb8 JP |
106 | } |
107 | ||
abe98ec2 JP |
108 | int pm_qos_update_target(struct pm_qos_constraints *c, struct plist_node *node, |
109 | enum pm_qos_req_action action, int value); | |
5efbe427 RW |
110 | bool pm_qos_update_flags(struct pm_qos_flags *pqf, |
111 | struct pm_qos_flags_request *req, | |
112 | enum pm_qos_req_action action, s32 val); | |
cc749986 JP |
113 | void pm_qos_add_request(struct pm_qos_request *req, int pm_qos_class, |
114 | s32 value); | |
115 | void pm_qos_update_request(struct pm_qos_request *req, | |
e8db0be1 | 116 | s32 new_value); |
c4772d19 MH |
117 | void pm_qos_update_request_timeout(struct pm_qos_request *req, |
118 | s32 new_value, unsigned long timeout_us); | |
cc749986 | 119 | void pm_qos_remove_request(struct pm_qos_request *req); |
d82b3518 | 120 | |
ed77134b MG |
121 | int pm_qos_request(int pm_qos_class); |
122 | int pm_qos_add_notifier(int pm_qos_class, struct notifier_block *notifier); | |
123 | int pm_qos_remove_notifier(int pm_qos_class, struct notifier_block *notifier); | |
cc749986 | 124 | int pm_qos_request_active(struct pm_qos_request *req); |
b66213cd | 125 | s32 pm_qos_read_value(struct pm_qos_constraints *c); |
91ff4cb8 | 126 | |
a9b542ee | 127 | #ifdef CONFIG_PM |
ae0fb4b7 RW |
128 | enum pm_qos_flags_status __dev_pm_qos_flags(struct device *dev, s32 mask); |
129 | enum pm_qos_flags_status dev_pm_qos_flags(struct device *dev, s32 mask); | |
00dc9ad1 | 130 | s32 __dev_pm_qos_read_value(struct device *dev); |
1a9a9152 | 131 | s32 dev_pm_qos_read_value(struct device *dev); |
91ff4cb8 | 132 | int dev_pm_qos_add_request(struct device *dev, struct dev_pm_qos_request *req, |
ae0fb4b7 | 133 | enum dev_pm_qos_req_type type, s32 value); |
91ff4cb8 JP |
134 | int dev_pm_qos_update_request(struct dev_pm_qos_request *req, s32 new_value); |
135 | int dev_pm_qos_remove_request(struct dev_pm_qos_request *req); | |
136 | int dev_pm_qos_add_notifier(struct device *dev, | |
137 | struct notifier_block *notifier); | |
138 | int dev_pm_qos_remove_notifier(struct device *dev, | |
139 | struct notifier_block *notifier); | |
b66213cd JP |
140 | int dev_pm_qos_add_global_notifier(struct notifier_block *notifier); |
141 | int dev_pm_qos_remove_global_notifier(struct notifier_block *notifier); | |
91ff4cb8 JP |
142 | void dev_pm_qos_constraints_init(struct device *dev); |
143 | void dev_pm_qos_constraints_destroy(struct device *dev); | |
40a5f8be RW |
144 | int dev_pm_qos_add_ancestor_request(struct device *dev, |
145 | struct dev_pm_qos_request *req, s32 value); | |
e8db0be1 | 146 | #else |
ae0fb4b7 RW |
147 | static inline enum pm_qos_flags_status __dev_pm_qos_flags(struct device *dev, |
148 | s32 mask) | |
149 | { return PM_QOS_FLAGS_UNDEFINED; } | |
150 | static inline enum pm_qos_flags_status dev_pm_qos_flags(struct device *dev, | |
151 | s32 mask) | |
152 | { return PM_QOS_FLAGS_UNDEFINED; } | |
00dc9ad1 RW |
153 | static inline s32 __dev_pm_qos_read_value(struct device *dev) |
154 | { return 0; } | |
1a9a9152 RW |
155 | static inline s32 dev_pm_qos_read_value(struct device *dev) |
156 | { return 0; } | |
91ff4cb8 JP |
157 | static inline int dev_pm_qos_add_request(struct device *dev, |
158 | struct dev_pm_qos_request *req, | |
ae0fb4b7 | 159 | enum dev_pm_qos_req_type type, |
91ff4cb8 JP |
160 | s32 value) |
161 | { return 0; } | |
162 | static inline int dev_pm_qos_update_request(struct dev_pm_qos_request *req, | |
163 | s32 new_value) | |
164 | { return 0; } | |
165 | static inline int dev_pm_qos_remove_request(struct dev_pm_qos_request *req) | |
166 | { return 0; } | |
167 | static inline int dev_pm_qos_add_notifier(struct device *dev, | |
168 | struct notifier_block *notifier) | |
169 | { return 0; } | |
170 | static inline int dev_pm_qos_remove_notifier(struct device *dev, | |
171 | struct notifier_block *notifier) | |
172 | { return 0; } | |
b66213cd JP |
173 | static inline int dev_pm_qos_add_global_notifier( |
174 | struct notifier_block *notifier) | |
175 | { return 0; } | |
176 | static inline int dev_pm_qos_remove_global_notifier( | |
177 | struct notifier_block *notifier) | |
178 | { return 0; } | |
91ff4cb8 | 179 | static inline void dev_pm_qos_constraints_init(struct device *dev) |
1a9a9152 RW |
180 | { |
181 | dev->power.power_state = PMSG_ON; | |
182 | } | |
91ff4cb8 | 183 | static inline void dev_pm_qos_constraints_destroy(struct device *dev) |
1a9a9152 RW |
184 | { |
185 | dev->power.power_state = PMSG_INVALID; | |
186 | } | |
40a5f8be RW |
187 | static inline int dev_pm_qos_add_ancestor_request(struct device *dev, |
188 | struct dev_pm_qos_request *req, s32 value) | |
189 | { return 0; } | |
e8db0be1 | 190 | #endif |
d82b3518 | 191 | |
85dc0b8a RW |
192 | #ifdef CONFIG_PM_RUNTIME |
193 | int dev_pm_qos_expose_latency_limit(struct device *dev, s32 value); | |
194 | void dev_pm_qos_hide_latency_limit(struct device *dev); | |
e39473d0 RW |
195 | int dev_pm_qos_expose_flags(struct device *dev, s32 value); |
196 | void dev_pm_qos_hide_flags(struct device *dev); | |
197 | int dev_pm_qos_update_flags(struct device *dev, s32 mask, bool set); | |
198 | ||
199 | static inline s32 dev_pm_qos_requested_latency(struct device *dev) | |
200 | { | |
201 | return dev->power.qos->latency_req->data.pnode.prio; | |
202 | } | |
203 | ||
204 | static inline s32 dev_pm_qos_requested_flags(struct device *dev) | |
205 | { | |
206 | return dev->power.qos->flags_req->data.flr.flags; | |
207 | } | |
85dc0b8a RW |
208 | #else |
209 | static inline int dev_pm_qos_expose_latency_limit(struct device *dev, s32 value) | |
210 | { return 0; } | |
211 | static inline void dev_pm_qos_hide_latency_limit(struct device *dev) {} | |
e39473d0 RW |
212 | static inline int dev_pm_qos_expose_flags(struct device *dev, s32 value) |
213 | { return 0; } | |
214 | static inline void dev_pm_qos_hide_flags(struct device *dev) {} | |
215 | static inline int dev_pm_qos_update_flags(struct device *dev, s32 m, bool set) | |
216 | { return 0; } | |
217 | ||
218 | static inline s32 dev_pm_qos_requested_latency(struct device *dev) { return 0; } | |
219 | static inline s32 dev_pm_qos_requested_flags(struct device *dev) { return 0; } | |
85dc0b8a RW |
220 | #endif |
221 | ||
82f68251 | 222 | #endif |