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e8db0be1 JP |
1 | #ifndef _LINUX_PM_QOS_H |
2 | #define _LINUX_PM_QOS_H | |
d82b3518 MG |
3 | /* interface for the pm_qos_power infrastructure of the linux kernel. |
4 | * | |
bf1db69f | 5 | * Mark Gross <mgross@linux.intel.com> |
d82b3518 | 6 | */ |
82f68251 | 7 | #include <linux/plist.h> |
d82b3518 | 8 | #include <linux/notifier.h> |
1a9a9152 | 9 | #include <linux/device.h> |
c4772d19 | 10 | #include <linux/workqueue.h> |
d82b3518 | 11 | |
d031e1de AF |
12 | enum { |
13 | PM_QOS_RESERVED = 0, | |
14 | PM_QOS_CPU_DMA_LATENCY, | |
15 | PM_QOS_NETWORK_LATENCY, | |
16 | PM_QOS_NETWORK_THROUGHPUT, | |
7990da71 | 17 | PM_QOS_MEMORY_BANDWIDTH, |
d031e1de AF |
18 | |
19 | /* insert new class ID */ | |
20 | PM_QOS_NUM_CLASSES, | |
21 | }; | |
d82b3518 | 22 | |
ae0fb4b7 RW |
23 | enum pm_qos_flags_status { |
24 | PM_QOS_FLAGS_UNDEFINED = -1, | |
25 | PM_QOS_FLAGS_NONE, | |
26 | PM_QOS_FLAGS_SOME, | |
27 | PM_QOS_FLAGS_ALL, | |
28 | }; | |
29 | ||
d82b3518 MG |
30 | #define PM_QOS_DEFAULT_VALUE -1 |
31 | ||
333c5ae9 TC |
32 | #define PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE (2000 * USEC_PER_SEC) |
33 | #define PM_QOS_NETWORK_LAT_DEFAULT_VALUE (2000 * USEC_PER_SEC) | |
34 | #define PM_QOS_NETWORK_THROUGHPUT_DEFAULT_VALUE 0 | |
7990da71 | 35 | #define PM_QOS_MEMORY_BANDWIDTH_DEFAULT_VALUE 0 |
b02f6695 | 36 | #define PM_QOS_RESUME_LATENCY_DEFAULT_VALUE 0 |
2d984ad1 RW |
37 | #define PM_QOS_LATENCY_TOLERANCE_DEFAULT_VALUE 0 |
38 | #define PM_QOS_LATENCY_TOLERANCE_NO_CONSTRAINT (-1) | |
39 | #define PM_QOS_LATENCY_ANY ((s32)(~(__u32)0 >> 1)) | |
333c5ae9 | 40 | |
e39473d0 RW |
41 | #define PM_QOS_FLAG_NO_POWER_OFF (1 << 0) |
42 | #define PM_QOS_FLAG_REMOTE_WAKEUP (1 << 1) | |
43 | ||
cc749986 JP |
44 | struct pm_qos_request { |
45 | struct plist_node node; | |
82f68251 | 46 | int pm_qos_class; |
c4772d19 | 47 | struct delayed_work work; /* for pm_qos_update_request_timeout */ |
82f68251 | 48 | }; |
d82b3518 | 49 | |
5efbe427 RW |
50 | struct pm_qos_flags_request { |
51 | struct list_head node; | |
52 | s32 flags; /* Do not change to 64 bit */ | |
53 | }; | |
54 | ||
ae0fb4b7 | 55 | enum dev_pm_qos_req_type { |
b02f6695 | 56 | DEV_PM_QOS_RESUME_LATENCY = 1, |
2d984ad1 | 57 | DEV_PM_QOS_LATENCY_TOLERANCE, |
ae0fb4b7 RW |
58 | DEV_PM_QOS_FLAGS, |
59 | }; | |
60 | ||
91ff4cb8 | 61 | struct dev_pm_qos_request { |
ae0fb4b7 | 62 | enum dev_pm_qos_req_type type; |
021c870b RW |
63 | union { |
64 | struct plist_node pnode; | |
ae0fb4b7 | 65 | struct pm_qos_flags_request flr; |
021c870b | 66 | } data; |
91ff4cb8 JP |
67 | struct device *dev; |
68 | }; | |
69 | ||
4e1779ba JP |
70 | enum pm_qos_type { |
71 | PM_QOS_UNITIALIZED, | |
72 | PM_QOS_MAX, /* return the largest value */ | |
7990da71 TV |
73 | PM_QOS_MIN, /* return the smallest value */ |
74 | PM_QOS_SUM /* return the sum */ | |
4e1779ba JP |
75 | }; |
76 | ||
77 | /* | |
5efbe427 RW |
78 | * Note: The lockless read path depends on the CPU accessing target_value |
79 | * or effective_flags atomically. Atomic access is only guaranteed on all CPU | |
4e1779ba JP |
80 | * types linux supports for 32 bit quantites |
81 | */ | |
82 | struct pm_qos_constraints { | |
83 | struct plist_head list; | |
84 | s32 target_value; /* Do not change to 64 bit */ | |
85 | s32 default_value; | |
327adaed | 86 | s32 no_constraint_value; |
4e1779ba JP |
87 | enum pm_qos_type type; |
88 | struct blocking_notifier_head *notifiers; | |
89 | }; | |
90 | ||
5efbe427 RW |
91 | struct pm_qos_flags { |
92 | struct list_head list; | |
93 | s32 effective_flags; /* Do not change to 64 bit */ | |
94 | }; | |
95 | ||
5f986c59 | 96 | struct dev_pm_qos { |
b02f6695 | 97 | struct pm_qos_constraints resume_latency; |
2d984ad1 | 98 | struct pm_qos_constraints latency_tolerance; |
ae0fb4b7 | 99 | struct pm_qos_flags flags; |
b02f6695 | 100 | struct dev_pm_qos_request *resume_latency_req; |
2d984ad1 | 101 | struct dev_pm_qos_request *latency_tolerance_req; |
e39473d0 | 102 | struct dev_pm_qos_request *flags_req; |
5f986c59 RW |
103 | }; |
104 | ||
abe98ec2 JP |
105 | /* Action requested to pm_qos_update_target */ |
106 | enum pm_qos_req_action { | |
107 | PM_QOS_ADD_REQ, /* Add a new request */ | |
108 | PM_QOS_UPDATE_REQ, /* Update an existing request */ | |
109 | PM_QOS_REMOVE_REQ /* Remove an existing request */ | |
110 | }; | |
111 | ||
91ff4cb8 JP |
112 | static inline int dev_pm_qos_request_active(struct dev_pm_qos_request *req) |
113 | { | |
83618092 | 114 | return req->dev != NULL; |
91ff4cb8 JP |
115 | } |
116 | ||
abe98ec2 JP |
117 | int pm_qos_update_target(struct pm_qos_constraints *c, struct plist_node *node, |
118 | enum pm_qos_req_action action, int value); | |
5efbe427 RW |
119 | bool pm_qos_update_flags(struct pm_qos_flags *pqf, |
120 | struct pm_qos_flags_request *req, | |
121 | enum pm_qos_req_action action, s32 val); | |
cc749986 JP |
122 | void pm_qos_add_request(struct pm_qos_request *req, int pm_qos_class, |
123 | s32 value); | |
124 | void pm_qos_update_request(struct pm_qos_request *req, | |
e8db0be1 | 125 | s32 new_value); |
c4772d19 MH |
126 | void pm_qos_update_request_timeout(struct pm_qos_request *req, |
127 | s32 new_value, unsigned long timeout_us); | |
cc749986 | 128 | void pm_qos_remove_request(struct pm_qos_request *req); |
d82b3518 | 129 | |
ed77134b MG |
130 | int pm_qos_request(int pm_qos_class); |
131 | int pm_qos_add_notifier(int pm_qos_class, struct notifier_block *notifier); | |
132 | int pm_qos_remove_notifier(int pm_qos_class, struct notifier_block *notifier); | |
cc749986 | 133 | int pm_qos_request_active(struct pm_qos_request *req); |
b66213cd | 134 | s32 pm_qos_read_value(struct pm_qos_constraints *c); |
91ff4cb8 | 135 | |
a9b542ee | 136 | #ifdef CONFIG_PM |
ae0fb4b7 RW |
137 | enum pm_qos_flags_status __dev_pm_qos_flags(struct device *dev, s32 mask); |
138 | enum pm_qos_flags_status dev_pm_qos_flags(struct device *dev, s32 mask); | |
00dc9ad1 | 139 | s32 __dev_pm_qos_read_value(struct device *dev); |
1a9a9152 | 140 | s32 dev_pm_qos_read_value(struct device *dev); |
91ff4cb8 | 141 | int dev_pm_qos_add_request(struct device *dev, struct dev_pm_qos_request *req, |
ae0fb4b7 | 142 | enum dev_pm_qos_req_type type, s32 value); |
91ff4cb8 JP |
143 | int dev_pm_qos_update_request(struct dev_pm_qos_request *req, s32 new_value); |
144 | int dev_pm_qos_remove_request(struct dev_pm_qos_request *req); | |
145 | int dev_pm_qos_add_notifier(struct device *dev, | |
146 | struct notifier_block *notifier); | |
147 | int dev_pm_qos_remove_notifier(struct device *dev, | |
148 | struct notifier_block *notifier); | |
149 | void dev_pm_qos_constraints_init(struct device *dev); | |
150 | void dev_pm_qos_constraints_destroy(struct device *dev); | |
40a5f8be | 151 | int dev_pm_qos_add_ancestor_request(struct device *dev, |
71d821fd RW |
152 | struct dev_pm_qos_request *req, |
153 | enum dev_pm_qos_req_type type, s32 value); | |
d30d819d RW |
154 | int dev_pm_qos_expose_latency_limit(struct device *dev, s32 value); |
155 | void dev_pm_qos_hide_latency_limit(struct device *dev); | |
156 | int dev_pm_qos_expose_flags(struct device *dev, s32 value); | |
157 | void dev_pm_qos_hide_flags(struct device *dev); | |
158 | int dev_pm_qos_update_flags(struct device *dev, s32 mask, bool set); | |
159 | s32 dev_pm_qos_get_user_latency_tolerance(struct device *dev); | |
160 | int dev_pm_qos_update_user_latency_tolerance(struct device *dev, s32 val); | |
13b2c4a0 MW |
161 | int dev_pm_qos_expose_latency_tolerance(struct device *dev); |
162 | void dev_pm_qos_hide_latency_tolerance(struct device *dev); | |
d30d819d RW |
163 | |
164 | static inline s32 dev_pm_qos_requested_resume_latency(struct device *dev) | |
165 | { | |
166 | return dev->power.qos->resume_latency_req->data.pnode.prio; | |
167 | } | |
168 | ||
169 | static inline s32 dev_pm_qos_requested_flags(struct device *dev) | |
170 | { | |
171 | return dev->power.qos->flags_req->data.flr.flags; | |
172 | } | |
6dbf5cea RW |
173 | |
174 | static inline s32 dev_pm_qos_raw_read_value(struct device *dev) | |
175 | { | |
176 | return IS_ERR_OR_NULL(dev->power.qos) ? | |
177 | 0 : pm_qos_read_value(&dev->power.qos->resume_latency); | |
178 | } | |
e8db0be1 | 179 | #else |
ae0fb4b7 RW |
180 | static inline enum pm_qos_flags_status __dev_pm_qos_flags(struct device *dev, |
181 | s32 mask) | |
182 | { return PM_QOS_FLAGS_UNDEFINED; } | |
183 | static inline enum pm_qos_flags_status dev_pm_qos_flags(struct device *dev, | |
184 | s32 mask) | |
185 | { return PM_QOS_FLAGS_UNDEFINED; } | |
00dc9ad1 RW |
186 | static inline s32 __dev_pm_qos_read_value(struct device *dev) |
187 | { return 0; } | |
1a9a9152 RW |
188 | static inline s32 dev_pm_qos_read_value(struct device *dev) |
189 | { return 0; } | |
91ff4cb8 JP |
190 | static inline int dev_pm_qos_add_request(struct device *dev, |
191 | struct dev_pm_qos_request *req, | |
ae0fb4b7 | 192 | enum dev_pm_qos_req_type type, |
91ff4cb8 JP |
193 | s32 value) |
194 | { return 0; } | |
195 | static inline int dev_pm_qos_update_request(struct dev_pm_qos_request *req, | |
196 | s32 new_value) | |
197 | { return 0; } | |
198 | static inline int dev_pm_qos_remove_request(struct dev_pm_qos_request *req) | |
199 | { return 0; } | |
200 | static inline int dev_pm_qos_add_notifier(struct device *dev, | |
201 | struct notifier_block *notifier) | |
202 | { return 0; } | |
203 | static inline int dev_pm_qos_remove_notifier(struct device *dev, | |
204 | struct notifier_block *notifier) | |
205 | { return 0; } | |
206 | static inline void dev_pm_qos_constraints_init(struct device *dev) | |
1a9a9152 RW |
207 | { |
208 | dev->power.power_state = PMSG_ON; | |
209 | } | |
91ff4cb8 | 210 | static inline void dev_pm_qos_constraints_destroy(struct device *dev) |
1a9a9152 RW |
211 | { |
212 | dev->power.power_state = PMSG_INVALID; | |
213 | } | |
40a5f8be | 214 | static inline int dev_pm_qos_add_ancestor_request(struct device *dev, |
71d821fd RW |
215 | struct dev_pm_qos_request *req, |
216 | enum dev_pm_qos_req_type type, | |
217 | s32 value) | |
40a5f8be | 218 | { return 0; } |
85dc0b8a RW |
219 | static inline int dev_pm_qos_expose_latency_limit(struct device *dev, s32 value) |
220 | { return 0; } | |
221 | static inline void dev_pm_qos_hide_latency_limit(struct device *dev) {} | |
e39473d0 RW |
222 | static inline int dev_pm_qos_expose_flags(struct device *dev, s32 value) |
223 | { return 0; } | |
224 | static inline void dev_pm_qos_hide_flags(struct device *dev) {} | |
225 | static inline int dev_pm_qos_update_flags(struct device *dev, s32 m, bool set) | |
226 | { return 0; } | |
2d984ad1 RW |
227 | static inline s32 dev_pm_qos_get_user_latency_tolerance(struct device *dev) |
228 | { return PM_QOS_LATENCY_TOLERANCE_NO_CONSTRAINT; } | |
229 | static inline int dev_pm_qos_update_user_latency_tolerance(struct device *dev, s32 val) | |
230 | { return 0; } | |
13b2c4a0 MW |
231 | static inline int dev_pm_qos_expose_latency_tolerance(struct device *dev) |
232 | { return 0; } | |
233 | static inline void dev_pm_qos_hide_latency_tolerance(struct device *dev) {} | |
e39473d0 | 234 | |
b02f6695 | 235 | static inline s32 dev_pm_qos_requested_resume_latency(struct device *dev) { return 0; } |
e39473d0 | 236 | static inline s32 dev_pm_qos_requested_flags(struct device *dev) { return 0; } |
6dbf5cea | 237 | static inline s32 dev_pm_qos_raw_read_value(struct device *dev) { return 0; } |
85dc0b8a RW |
238 | #endif |
239 | ||
82f68251 | 240 | #endif |