[linux-block.git] / include / linux / platform_data / ti-sysc.h

#ifndef __TI_SYSC_DATA_H__
#define __TI_SYSC_DATA_H__

enum ti_sysc_module_type {
	TI_SYSC_OMAP2,
	TI_SYSC_OMAP2_TIMER,
	TI_SYSC_OMAP3_SHAM,
	TI_SYSC_OMAP3_AES,
	TI_SYSC_OMAP4,
	TI_SYSC_OMAP4_TIMER,
	TI_SYSC_OMAP4_SIMPLE,
	TI_SYSC_OMAP34XX_SR,
	TI_SYSC_OMAP36XX_SR,
	TI_SYSC_OMAP4_SR,
	TI_SYSC_OMAP4_MCASP,
	TI_SYSC_OMAP4_USB_HOST_FS,
	TI_SYSC_DRA7_MCAN,
};

struct ti_sysc_cookie {
	void *data;
};

/**
 * struct sysc_regbits - TI OCP_SYSCONFIG register field offsets
 * @midle_shift: Offset of the midle bit
 * @clkact_shift: Offset of the clockactivity bit
 * @sidle_shift: Offset of the sidle bit
 * @enwkup_shift: Offset of the enawakeup bit
 * @srst_shift: Offset of the softreset bit
 * @autoidle_shift: Offset of the autoidle bit
 * @dmadisable_shift: Offset of the dmadisable bit
 * @emufree_shift; Offset of the emufree bit
 *
 * Note that 0 is a valid shift, and for ti-sysc.c -ENODEV can be used if a
 * feature is not available.
 */
struct sysc_regbits {
	s8 midle_shift;
	s8 clkact_shift;
	s8 sidle_shift;
	s8 enwkup_shift;
	s8 srst_shift;
	s8 autoidle_shift;
	s8 dmadisable_shift;
	s8 emufree_shift;
};

#define SYSC_QUIRK_LEGACY_IDLE		BIT(8)
#define SYSC_QUIRK_RESET_STATUS		BIT(7)
#define SYSC_QUIRK_NO_IDLE_ON_INIT	BIT(6)
#define SYSC_QUIRK_NO_RESET_ON_INIT	BIT(5)
#define SYSC_QUIRK_OPT_CLKS_NEEDED	BIT(4)
#define SYSC_QUIRK_OPT_CLKS_IN_RESET	BIT(3)
#define SYSC_QUIRK_16BIT		BIT(2)
#define SYSC_QUIRK_UNCACHED		BIT(1)
#define SYSC_QUIRK_USE_CLOCKACT		BIT(0)

#define SYSC_NR_IDLEMODES		4

/**
 * struct sysc_capabilities - capabilities for an interconnect target module
 *
 * @sysc_mask: bitmask of supported SYSCONFIG register bits
 * @regbits: bitmask of SYSCONFIG register bits
 * @mod_quirks: bitmask of module specific quirks
 */
struct sysc_capabilities {
	const enum ti_sysc_module_type type;
	const u32 sysc_mask;
	const struct sysc_regbits *regbits;
	const u32 mod_quirks;
};

/**
 * struct sysc_config - configuration for an interconnect target module
 * @sysc_val: configured value for sysc register
 * @midlemodes: bitmask of supported master idle modes
 * @sidlemodes: bitmask of supported master idle modes
 * @srst_udelay: optional delay needed after OCP soft reset
 * @quirks: bitmask of enabled quirks
 */
struct sysc_config {
	u32 sysc_val;
	u32 syss_mask;
	u8 midlemodes;
	u8 sidlemodes;
	u8 srst_udelay;
	u32 quirks;
};

enum sysc_registers {
	SYSC_REVISION,
	SYSC_SYSCONFIG,
	SYSC_SYSSTATUS,
	SYSC_MAX_REGS,
};

/**
 * struct ti_sysc_module_data - ti-sysc to hwmod translation data for a module
 * @name: legacy "ti,hwmods" module name
 * @module_pa: physical address of the interconnect target module
 * @module_size: size of the interconnect target module
 * @offsets: array of register offsets as listed in enum sysc_registers
 * @nr_offsets: number of registers
 * @cap: interconnect target module capabilities
 * @cfg: interconnect target module configuration
 *
 * This data is enough to allocate a new struct omap_hwmod_class_sysconfig
 * based on device tree data parsed by ti-sysc driver.
 */
struct ti_sysc_module_data {
	const char *name;
	u64 module_pa;
	u32 module_size;
	int *offsets;
	int nr_offsets;
	const struct sysc_capabilities *cap;
	struct sysc_config *cfg;
};

struct device;

struct ti_sysc_platform_data {
	struct of_dev_auxdata *auxdata;
	int (*init_module)(struct device *dev,
			   const struct ti_sysc_module_data *data,
			   struct ti_sysc_cookie *cookie);
	int (*enable_module)(struct device *dev,
			     const struct ti_sysc_cookie *cookie);
	int (*idle_module)(struct device *dev,
			   const struct ti_sysc_cookie *cookie);
	int (*shutdown_module)(struct device *dev,
			       const struct ti_sysc_cookie *cookie);
};

#endif	/* __TI_SYSC_DATA_H__ */
Commit	Line	Data
49a0a3d8 TL	1	#ifndef __TI_SYSC_DATA_H__
	2	#define __TI_SYSC_DATA_H__
	3
70a65240 TL	4	enum ti_sysc_module_type {
	5	TI_SYSC_OMAP2,
	6	TI_SYSC_OMAP2_TIMER,
	7	TI_SYSC_OMAP3_SHAM,
	8	TI_SYSC_OMAP3_AES,
	9	TI_SYSC_OMAP4,
	10	TI_SYSC_OMAP4_TIMER,
	11	TI_SYSC_OMAP4_SIMPLE,
	12	TI_SYSC_OMAP34XX_SR,
	13	TI_SYSC_OMAP36XX_SR,
	14	TI_SYSC_OMAP4_SR,
	15	TI_SYSC_OMAP4_MCASP,
	16	TI_SYSC_OMAP4_USB_HOST_FS,
7f35e63d	17	TI_SYSC_DRA7_MCAN,
70a65240 TL	18	};
70a65240 TL	19
ef70b0bd TL	20	struct ti_sysc_cookie {
	21	void *data;
	22	};
	23
49a0a3d8 TL	24	/**
	25	* struct sysc_regbits - TI OCP_SYSCONFIG register field offsets
	26	* @midle_shift: Offset of the midle bit
	27	* @clkact_shift: Offset of the clockactivity bit
	28	* @sidle_shift: Offset of the sidle bit
	29	* @enwkup_shift: Offset of the enawakeup bit
	30	* @srst_shift: Offset of the softreset bit
	31	* @autoidle_shift: Offset of the autoidle bit
	32	* @dmadisable_shift: Offset of the dmadisable bit
	33	* @emufree_shift; Offset of the emufree bit
	34	*
	35	* Note that 0 is a valid shift, and for ti-sysc.c -ENODEV can be used if a
	36	* feature is not available.
	37	*/
	38	struct sysc_regbits {
	39	s8 midle_shift;
	40	s8 clkact_shift;
	41	s8 sidle_shift;
	42	s8 enwkup_shift;
	43	s8 srst_shift;
	44	s8 autoidle_shift;
	45	s8 dmadisable_shift;
	46	s8 emufree_shift;
	47	};
	48
a885f0fe	49	#define SYSC_QUIRK_LEGACY_IDLE BIT(8)
c5a2de97	50	#define SYSC_QUIRK_RESET_STATUS BIT(7)
566a9b05 TL	51	#define SYSC_QUIRK_NO_IDLE_ON_INIT BIT(6)
	52	#define SYSC_QUIRK_NO_RESET_ON_INIT BIT(5)
	53	#define SYSC_QUIRK_OPT_CLKS_NEEDED BIT(4)
	54	#define SYSC_QUIRK_OPT_CLKS_IN_RESET BIT(3)
a7199e2b	55	#define SYSC_QUIRK_16BIT BIT(2)
70a65240 TL	56	#define SYSC_QUIRK_UNCACHED BIT(1)
	57	#define SYSC_QUIRK_USE_CLOCKACT BIT(0)
	58
c5a2de97 TL	59	#define SYSC_NR_IDLEMODES 4
c5a2de97 TL	60
70a65240 TL	61	/**
	62	* struct sysc_capabilities - capabilities for an interconnect target module
	63	*
	64	* @sysc_mask: bitmask of supported SYSCONFIG register bits
	65	* @regbits: bitmask of SYSCONFIG register bits
	66	* @mod_quirks: bitmask of module specific quirks
	67	*/
	68	struct sysc_capabilities {
	69	const enum ti_sysc_module_type type;
	70	const u32 sysc_mask;
	71	const struct sysc_regbits *regbits;
	72	const u32 mod_quirks;
	73	};
	74
	75	/**
	76	* struct sysc_config - configuration for an interconnect target module
c5a2de97 TL	77	* @sysc_val: configured value for sysc register
	78	* @midlemodes: bitmask of supported master idle modes
	79	* @sidlemodes: bitmask of supported master idle modes
566a9b05	80	* @srst_udelay: optional delay needed after OCP soft reset
70a65240 TL	81	* @quirks: bitmask of enabled quirks
	82	*/
	83	struct sysc_config {
c5a2de97 TL	84	u32 sysc_val;
	85	u32 syss_mask;
	86	u8 midlemodes;
	87	u8 sidlemodes;
566a9b05	88	u8 srst_udelay;
70a65240 TL	89	u32 quirks;
	90	};
	91
ef70b0bd TL	92	enum sysc_registers {
	93	SYSC_REVISION,
	94	SYSC_SYSCONFIG,
	95	SYSC_SYSSTATUS,
	96	SYSC_MAX_REGS,
	97	};
	98
	99	/**
	100	* struct ti_sysc_module_data - ti-sysc to hwmod translation data for a module
	101	* @name: legacy "ti,hwmods" module name
	102	* @module_pa: physical address of the interconnect target module
	103	* @module_size: size of the interconnect target module
	104	* @offsets: array of register offsets as listed in enum sysc_registers
	105	* @nr_offsets: number of registers
	106	* @cap: interconnect target module capabilities
	107	* @cfg: interconnect target module configuration
	108	*
	109	* This data is enough to allocate a new struct omap_hwmod_class_sysconfig
	110	* based on device tree data parsed by ti-sysc driver.
	111	*/
	112	struct ti_sysc_module_data {
	113	const char *name;
	114	u64 module_pa;
	115	u32 module_size;
	116	int *offsets;
	117	int nr_offsets;
	118	const struct sysc_capabilities *cap;
	119	struct sysc_config *cfg;
	120	};
	121
	122	struct device;
	123
	124	struct ti_sysc_platform_data {
	125	struct of_dev_auxdata *auxdata;
	126	int (init_module)(struct device dev,
	127	const struct ti_sysc_module_data *data,
	128	struct ti_sysc_cookie *cookie);
	129	int (enable_module)(struct device dev,
	130	const struct ti_sysc_cookie *cookie);
	131	int (idle_module)(struct device dev,
	132	const struct ti_sysc_cookie *cookie);
	133	int (shutdown_module)(struct device dev,
	134	const struct ti_sysc_cookie *cookie);
	135	};
	136
49a0a3d8	137	#endif /* __TI_SYSC_DATA_H__ */