[linux-block.git] / include / linux / platform_data / spi-s3c64xx.h

/* SPDX-License-Identifier: GPL-2.0 */

/*
 * Copyright (C) 2009 Samsung Electronics Ltd.
 *	Jaswinder Singh <jassi.brar@samsung.com>
 */

#ifndef __SPI_S3C64XX_H
#define __SPI_S3C64XX_H

#include <linux/dmaengine.h>

struct platform_device;

/**
 * struct s3c64xx_spi_csinfo - ChipSelect description
 * @fb_delay: Slave specific feedback delay.
 *            Refer to FB_CLK_SEL register definition in SPI chapter.
 *
 * This is per SPI-Slave Chipselect information.
 * Allocate and initialize one in machine init code and make the
 * spi_board_info.controller_data point to it.
 */
struct s3c64xx_spi_csinfo {
	u8 fb_delay;
};

/**
 * struct s3c64xx_spi_info - SPI Controller defining structure
 * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field.
 * @num_cs: Number of CS this controller emulates.
 * @cfg_gpio: Configure pins for this SPI controller.
 */
struct s3c64xx_spi_info {
	int src_clk_nr;
	int num_cs;
	bool no_cs;
	int (*cfg_gpio)(void);
};

/**
 * s3c64xx_spi_set_platdata - SPI Controller configure callback by the board
 *				initialization code.
 * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks.
 * @num_cs: Number of elements in the 'cs' array.
 *
 * Call this from machine init code for each SPI Controller that
 * has some chips attached to it.
 */
extern void s3c64xx_spi0_set_platdata(int src_clk_nr, int num_cs);

/* defined by architecture to configure gpio */
extern int s3c64xx_spi0_cfg_gpio(void);

extern struct s3c64xx_spi_info s3c64xx_spi0_pdata;
#endif /*__SPI_S3C64XX_H */
Commit	Line	Data
78b5d705 AS	1	/* SPDX-License-Identifier: GPL-2.0 */
78b5d705 AS	2
963eb4b8	3	/*
398ccccb JB	4	* Copyright (C) 2009 Samsung Electronics Ltd.
398ccccb JB	5	* Jaswinder Singh <jassi.brar@samsung.com>
398ccccb JB	6	*/
398ccccb JB	7
963eb4b8 SK	8	#ifndef __SPI_S3C64XX_H
963eb4b8 SK	9	#define __SPI_S3C64XX_H
398ccccb	10
78843727 AB	11	#include <linux/dmaengine.h>
78843727 AB	12
5b0b34ea MB	13	struct platform_device;
5b0b34ea MB	14
398ccccb JB	15	/**
	16	* struct s3c64xx_spi_csinfo - ChipSelect description
	17	* @fb_delay: Slave specific feedback delay.
	18	* Refer to FB_CLK_SEL register definition in SPI chapter.
398ccccb JB	19	*
	20	* This is per SPI-Slave Chipselect information.
	21	* Allocate and initialize one in machine init code and make the
	22	* spi_board_info.controller_data point to it.
	23	*/
	24	struct s3c64xx_spi_csinfo {
	25	u8 fb_delay;
398ccccb JB	26	};
	27
	28	/**
	29	* struct s3c64xx_spi_info - SPI Controller defining structure
	30	* @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field.
398ccccb JB	31	* @num_cs: Number of CS this controller emulates.
398ccccb JB	32	* @cfg_gpio: Configure pins for this SPI controller.
398ccccb JB	33	*/
	34	struct s3c64xx_spi_info {
	35	int src_clk_nr;
398ccccb	36	int num_cs;
a92e7c3d	37	bool no_cs;
868dee91	38	int (*cfg_gpio)(void);
398ccccb JB	39	};
	40
	41	/**
875a5937	42	* s3c64xx_spi_set_platdata - SPI Controller configure callback by the board
398ccccb	43	* initialization code.
398ccccb JB	44	* @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks.
	45	* @num_cs: Number of elements in the 'cs' array.
	46	*
	47	* Call this from machine init code for each SPI Controller that
	48	* has some chips attached to it.
	49	*/
3b5529ae	50	extern void s3c64xx_spi0_set_platdata(int src_clk_nr, int num_cs);
4566c7f7 PV	51
4566c7f7 PV	52	/* defined by architecture to configure gpio */
868dee91	53	extern int s3c64xx_spi0_cfg_gpio(void);
4566c7f7 PV	54
4566c7f7 PV	55	extern struct s3c64xx_spi_info s3c64xx_spi0_pdata;
963eb4b8	56	#endif /__SPI_S3C64XX_H /