[linux-block.git] / include / linux / platform_data / dma-ste-dma40.h

/*
 * Copyright (C) ST-Ericsson SA 2007-2010
 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
 * License terms: GNU General Public License (GPL) version 2
 */


#ifndef STE_DMA40_H
#define STE_DMA40_H

#include <linux/dmaengine.h>
#include <linux/scatterlist.h>
#include <linux/workqueue.h>
#include <linux/interrupt.h>

/*
 * Maxium size for a single dma descriptor
 * Size is limited to 16 bits.
 * Size is in the units of addr-widths (1,2,4,8 bytes)
 * Larger transfers will be split up to multiple linked desc
 */
#define STEDMA40_MAX_SEG_SIZE 0xFFFF

/* dev types for memcpy */
#define STEDMA40_DEV_DST_MEMORY (-1)
#define	STEDMA40_DEV_SRC_MEMORY (-1)

enum stedma40_mode {
	STEDMA40_MODE_LOGICAL = 0,
	STEDMA40_MODE_PHYSICAL,
	STEDMA40_MODE_OPERATION,
};

enum stedma40_mode_opt {
	STEDMA40_PCHAN_BASIC_MODE = 0,
	STEDMA40_LCHAN_SRC_LOG_DST_LOG = 0,
	STEDMA40_PCHAN_MODULO_MODE,
	STEDMA40_PCHAN_DOUBLE_DST_MODE,
	STEDMA40_LCHAN_SRC_PHY_DST_LOG,
	STEDMA40_LCHAN_SRC_LOG_DST_PHY,
};

#define STEDMA40_ESIZE_8_BIT  0x0
#define STEDMA40_ESIZE_16_BIT 0x1
#define STEDMA40_ESIZE_32_BIT 0x2
#define STEDMA40_ESIZE_64_BIT 0x3

/* The value 4 indicates that PEN-reg shall be set to 0 */
#define STEDMA40_PSIZE_PHY_1  0x4
#define STEDMA40_PSIZE_PHY_2  0x0
#define STEDMA40_PSIZE_PHY_4  0x1
#define STEDMA40_PSIZE_PHY_8  0x2
#define STEDMA40_PSIZE_PHY_16 0x3

/*
 * The number of elements differ in logical and
 * physical mode
 */
#define STEDMA40_PSIZE_LOG_1  STEDMA40_PSIZE_PHY_2
#define STEDMA40_PSIZE_LOG_4  STEDMA40_PSIZE_PHY_4
#define STEDMA40_PSIZE_LOG_8  STEDMA40_PSIZE_PHY_8
#define STEDMA40_PSIZE_LOG_16 STEDMA40_PSIZE_PHY_16

/* Maximum number of possible physical channels */
#define STEDMA40_MAX_PHYS 32

enum stedma40_flow_ctrl {
	STEDMA40_NO_FLOW_CTRL,
	STEDMA40_FLOW_CTRL,
};

enum stedma40_periph_data_width {
	STEDMA40_BYTE_WIDTH = STEDMA40_ESIZE_8_BIT,
	STEDMA40_HALFWORD_WIDTH = STEDMA40_ESIZE_16_BIT,
	STEDMA40_WORD_WIDTH = STEDMA40_ESIZE_32_BIT,
	STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT
};

enum stedma40_xfer_dir {
	STEDMA40_MEM_TO_MEM = 1,
	STEDMA40_MEM_TO_PERIPH,
	STEDMA40_PERIPH_TO_MEM,
	STEDMA40_PERIPH_TO_PERIPH
};


/**
 * struct stedma40_chan_cfg - dst/src channel configuration
 *
 * @big_endian: true if the src/dst should be read as big endian
 * @data_width: Data width of the src/dst hardware
 * @p_size: Burst size
 * @flow_ctrl: Flow control on/off.
 */
struct stedma40_half_channel_info {
	bool big_endian;
	enum stedma40_periph_data_width data_width;
	int psize;
	enum stedma40_flow_ctrl flow_ctrl;
};

/**
 * struct stedma40_chan_cfg - Structure to be filled by client drivers.
 *
 * @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH
 * @high_priority: true if high-priority
 * @realtime: true if realtime mode is to be enabled.  Only available on DMA40
 * version 3+, i.e DB8500v2+
 * @mode: channel mode: physical, logical, or operation
 * @mode_opt: options for the chosen channel mode
 * @src_dev_type: Src device type
 * @dst_dev_type: Dst device type
 * @src_info: Parameters for dst half channel
 * @dst_info: Parameters for dst half channel
 * @use_fixed_channel: if true, use physical channel specified by phy_channel
 * @phy_channel: physical channel to use, only if use_fixed_channel is true
 *
 * This structure has to be filled by the client drivers.
 * It is recommended to do all dma configurations for clients in the machine.
 *
 */
struct stedma40_chan_cfg {
	enum stedma40_xfer_dir			 dir;
	bool					 high_priority;
	bool					 realtime;
	enum stedma40_mode			 mode;
	enum stedma40_mode_opt			 mode_opt;
	int					 src_dev_type;
	int					 dst_dev_type;
	struct stedma40_half_channel_info	 src_info;
	struct stedma40_half_channel_info	 dst_info;

	bool					 use_fixed_channel;
	int					 phy_channel;
};

/**
 * struct stedma40_platform_data - Configuration struct for the dma device.
 *
 * @dev_len: length of dev_tx and dev_rx
 * @dev_tx: mapping between destination event line and io address
 * @dev_rx: mapping between source event line and io address
 * @disabled_channels: A vector, ending with -1, that marks physical channels
 * that are for different reasons not available for the driver.
 * @soft_lli_chans: A vector, that marks physical channels will use LLI by SW
 * which avoids HW bug that exists in some versions of the controller.
 * SoftLLI introduces relink overhead that could impact performace for
 * certain use cases.
 * @num_of_soft_lli_chans: The number of channels that needs to be configured
 * to use SoftLLI.
 * @use_esram_lcla: flag for mapping the lcla into esram region
 * @num_of_phy_chans: The number of physical channels implemented in HW.
 * 0 means reading the number of channels from DMA HW but this is only valid
 * for 'multiple of 4' channels, like 8.
 */
struct stedma40_platform_data {
	u32				 dev_len;
	const dma_addr_t		*dev_tx;
	const dma_addr_t		*dev_rx;
	int				 disabled_channels[STEDMA40_MAX_PHYS];
	int				*soft_lli_chans;
	int				 num_of_soft_lli_chans;
	bool				 use_esram_lcla;
	int				 num_of_phy_chans;
};

#ifdef CONFIG_STE_DMA40

/**
 * stedma40_filter() - Provides stedma40_chan_cfg to the
 * ste_dma40 dma driver via the dmaengine framework.
 * does some checking of what's provided.
 *
 * Never directly called by client. It used by dmaengine.
 * @chan: dmaengine handle.
 * @data: Must be of type: struct stedma40_chan_cfg and is
 * the configuration of the framework.
 *
 *
 */

bool stedma40_filter(struct dma_chan *chan, void *data);

/**
 * stedma40_slave_mem() - Transfers a raw data buffer to or from a slave
 * (=device)
 *
 * @chan: dmaengine handle
 * @addr: source or destination physicall address.
 * @size: bytes to transfer
 * @direction: direction of transfer
 * @flags: is actually enum dma_ctrl_flags. See dmaengine.h
 */

static inline struct
dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan,
					    dma_addr_t addr,
					    unsigned int size,
					    enum dma_transfer_direction direction,
					    unsigned long flags)
{
	struct scatterlist sg;
	sg_init_table(&sg, 1);
	sg.dma_address = addr;
	sg.length = size;

	return dmaengine_prep_slave_sg(chan, &sg, 1, direction, flags);
}

#else
static inline bool stedma40_filter(struct dma_chan *chan, void *data)
{
	return false;
}

static inline struct
dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan,
					    dma_addr_t addr,
					    unsigned int size,
					    enum dma_transfer_direction direction,
					    unsigned long flags)
{
	return NULL;
}
#endif

#endif
Commit	Line	Data
8d318a50	1	/*
767a9675	2	* Copyright (C) ST-Ericsson SA 2007-2010
661385f9	3	* Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
767a9675	4	* Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
8d318a50	5	* License terms: GNU General Public License (GPL) version 2
8d318a50 LW	6	*/
	7
	8
	9	#ifndef STE_DMA40_H
	10	#define STE_DMA40_H
	11
	12	#include <linux/dmaengine.h>
b7f080cf	13	#include <linux/scatterlist.h>
8d318a50 LW	14	#include <linux/workqueue.h>
8d318a50 LW	15	#include <linux/interrupt.h>
8d318a50	16
d49278e3 PF	17	/*
	18	* Maxium size for a single dma descriptor
	19	* Size is limited to 16 bits.
	20	* Size is in the units of addr-widths (1,2,4,8 bytes)
	21	* Larger transfers will be split up to multiple linked desc
	22	*/
	23	#define STEDMA40_MAX_SEG_SIZE 0xFFFF
	24
8d318a50 LW	25	/* dev types for memcpy */
	26	#define STEDMA40_DEV_DST_MEMORY (-1)
	27	#define STEDMA40_DEV_SRC_MEMORY (-1)
	28
38bdbf02 RV	29	enum stedma40_mode {
	30	STEDMA40_MODE_LOGICAL = 0,
	31	STEDMA40_MODE_PHYSICAL,
	32	STEDMA40_MODE_OPERATION,
	33	};
8d318a50	34
20a5b6d0 RV	35	enum stedma40_mode_opt {
	36	STEDMA40_PCHAN_BASIC_MODE = 0,
	37	STEDMA40_LCHAN_SRC_LOG_DST_LOG = 0,
	38	STEDMA40_PCHAN_MODULO_MODE,
	39	STEDMA40_PCHAN_DOUBLE_DST_MODE,
	40	STEDMA40_LCHAN_SRC_PHY_DST_LOG,
	41	STEDMA40_LCHAN_SRC_LOG_DST_PHY,
	42	};
8d318a50 LW	43
	44	#define STEDMA40_ESIZE_8_BIT 0x0
	45	#define STEDMA40_ESIZE_16_BIT 0x1
	46	#define STEDMA40_ESIZE_32_BIT 0x2
	47	#define STEDMA40_ESIZE_64_BIT 0x3
	48
	49	/* The value 4 indicates that PEN-reg shall be set to 0 */
	50	#define STEDMA40_PSIZE_PHY_1 0x4
	51	#define STEDMA40_PSIZE_PHY_2 0x0
	52	#define STEDMA40_PSIZE_PHY_4 0x1
	53	#define STEDMA40_PSIZE_PHY_8 0x2
	54	#define STEDMA40_PSIZE_PHY_16 0x3
	55
	56	/*
	57	* The number of elements differ in logical and
	58	* physical mode
	59	*/
	60	#define STEDMA40_PSIZE_LOG_1 STEDMA40_PSIZE_PHY_2
	61	#define STEDMA40_PSIZE_LOG_4 STEDMA40_PSIZE_PHY_4
	62	#define STEDMA40_PSIZE_LOG_8 STEDMA40_PSIZE_PHY_8
	63	#define STEDMA40_PSIZE_LOG_16 STEDMA40_PSIZE_PHY_16
	64
767a9675 JA	65	/* Maximum number of possible physical channels */
	66	#define STEDMA40_MAX_PHYS 32
	67
8d318a50 LW	68	enum stedma40_flow_ctrl {
	69	STEDMA40_NO_FLOW_CTRL,
	70	STEDMA40_FLOW_CTRL,
	71	};
	72
8d318a50 LW	73	enum stedma40_periph_data_width {
	74	STEDMA40_BYTE_WIDTH = STEDMA40_ESIZE_8_BIT,
	75	STEDMA40_HALFWORD_WIDTH = STEDMA40_ESIZE_16_BIT,
	76	STEDMA40_WORD_WIDTH = STEDMA40_ESIZE_32_BIT,
	77	STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT
	78	};
	79
8d318a50	80	enum stedma40_xfer_dir {
0747c7ba	81	STEDMA40_MEM_TO_MEM = 1,
8d318a50 LW	82	STEDMA40_MEM_TO_PERIPH,
	83	STEDMA40_PERIPH_TO_MEM,
	84	STEDMA40_PERIPH_TO_PERIPH
	85	};
	86
	87
3c0f2401 JA	88	/**
	89	* struct stedma40_chan_cfg - dst/src channel configuration
	90	*
51f5d744	91	* @big_endian: true if the src/dst should be read as big endian
3c0f2401 JA	92	* @data_width: Data width of the src/dst hardware
	93	* @p_size: Burst size
	94	* @flow_ctrl: Flow control on/off.
	95	*/
	96	struct stedma40_half_channel_info {
51f5d744	97	bool big_endian;
3c0f2401 JA	98	enum stedma40_periph_data_width data_width;
	99	int psize;
	100	enum stedma40_flow_ctrl flow_ctrl;
	101	};
	102
8d318a50 LW	103	/**
	104	* struct stedma40_chan_cfg - Structure to be filled by client drivers.
	105	*
	106	* @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH
730c1871	107	* @high_priority: true if high-priority
ac2c0a38 RV	108	* @realtime: true if realtime mode is to be enabled. Only available on DMA40
ac2c0a38 RV	109	* version 3+, i.e DB8500v2+
38bdbf02	110	* @mode: channel mode: physical, logical, or operation
20a5b6d0	111	* @mode_opt: options for the chosen channel mode
8d318a50 LW	112	* @src_dev_type: Src device type
	113	* @dst_dev_type: Dst device type
	114	* @src_info: Parameters for dst half channel
	115	* @dst_info: Parameters for dst half channel
5cd326fd N	116	* @use_fixed_channel: if true, use physical channel specified by phy_channel
5cd326fd N	117	* @phy_channel: physical channel to use, only if use_fixed_channel is true
8d318a50 LW	118	*
	119	* This structure has to be filled by the client drivers.
	120	* It is recommended to do all dma configurations for clients in the machine.
	121	*
	122	*/
	123	struct stedma40_chan_cfg {
	124	enum stedma40_xfer_dir dir;
730c1871	125	bool high_priority;
ac2c0a38	126	bool realtime;
38bdbf02	127	enum stedma40_mode mode;
20a5b6d0	128	enum stedma40_mode_opt mode_opt;
8d318a50 LW	129	int src_dev_type;
	130	int dst_dev_type;
	131	struct stedma40_half_channel_info src_info;
	132	struct stedma40_half_channel_info dst_info;
5cd326fd N	133
	134	bool use_fixed_channel;
	135	int phy_channel;
8d318a50 LW	136	};
	137
	138	/**
	139	* struct stedma40_platform_data - Configuration struct for the dma device.
	140	*
	141	* @dev_len: length of dev_tx and dev_rx
	142	* @dev_tx: mapping between destination event line and io address
	143	* @dev_rx: mapping between source event line and io address
59516725 JA	144	* @disabled_channels: A vector, ending with -1, that marks physical channels
59516725 JA	145	* that are for different reasons not available for the driver.
7407048b FB	146	* @soft_lli_chans: A vector, that marks physical channels will use LLI by SW
	147	* which avoids HW bug that exists in some versions of the controller.
	148	* SoftLLI introduces relink overhead that could impact performace for
	149	* certain use cases.
	150	* @num_of_soft_lli_chans: The number of channels that needs to be configured
	151	* to use SoftLLI.
762eb33f	152	* @use_esram_lcla: flag for mapping the lcla into esram region
47db92f4 GB	153	* @num_of_phy_chans: The number of physical channels implemented in HW.
	154	* 0 means reading the number of channels from DMA HW but this is only valid
	155	* for 'multiple of 4' channels, like 8.
8d318a50 LW	156	*/
	157	struct stedma40_platform_data {
	158	u32 dev_len;
	159	const dma_addr_t *dev_tx;
	160	const dma_addr_t *dev_rx;
767a9675	161	int disabled_channels[STEDMA40_MAX_PHYS];
7407048b FB	162	int *soft_lli_chans;
7407048b FB	163	int num_of_soft_lli_chans;
28c7a19d	164	bool use_esram_lcla;
47db92f4	165	int num_of_phy_chans;
8d318a50 LW	166	};
8d318a50 LW	167
9646b798	168	#ifdef CONFIG_STE_DMA40
8d318a50 LW	169
	170	/**
	171	* stedma40_filter() - Provides stedma40_chan_cfg to the
	172	* ste_dma40 dma driver via the dmaengine framework.
	173	* does some checking of what's provided.
	174	*
	175	* Never directly called by client. It used by dmaengine.
	176	* @chan: dmaengine handle.
	177	* @data: Must be of type: struct stedma40_chan_cfg and is
	178	* the configuration of the framework.
	179	*
	180	*
	181	*/
	182
	183	bool stedma40_filter(struct dma_chan chan, void data);
	184
8d318a50 LW	185	/**
	186	* stedma40_slave_mem() - Transfers a raw data buffer to or from a slave
	187	* (=device)
	188	*
	189	* @chan: dmaengine handle
	190	* @addr: source or destination physicall address.
	191	* @size: bytes to transfer
	192	* @direction: direction of transfer
	193	* @flags: is actually enum dma_ctrl_flags. See dmaengine.h
	194	*/
	195
	196	static inline struct
	197	dma_async_tx_descriptor stedma40_slave_mem(struct dma_chan chan,
	198	dma_addr_t addr,
	199	unsigned int size,
db8196df	200	enum dma_transfer_direction direction,
8d318a50 LW	201	unsigned long flags)
	202	{
	203	struct scatterlist sg;
	204	sg_init_table(&sg, 1);
	205	sg.dma_address = addr;
	206	sg.length = size;
	207
16052827	208	return dmaengine_prep_slave_sg(chan, &sg, 1, direction, flags);
8d318a50 LW	209	}
8d318a50 LW	210
9646b798 LW	211	#else
	212	static inline bool stedma40_filter(struct dma_chan chan, void data)
	213	{
	214	return false;
	215	}
	216
	217	static inline struct
	218	dma_async_tx_descriptor stedma40_slave_mem(struct dma_chan chan,
	219	dma_addr_t addr,
	220	unsigned int size,
db8196df	221	enum dma_transfer_direction direction,
9646b798 LW	222	unsigned long flags)
	223	{
	224	return NULL;
	225	}
	226	#endif
	227
8d318a50	228	#endif