Merge tag 'pci-v6.16-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
[linux-2.6-block.git] / include / linux / phy.h
CommitLineData
2874c5fd 1/* SPDX-License-Identifier: GPL-2.0-or-later */
00db8189 2/*
00db8189 3 * Framework and drivers for configuring and reading different PHYs
d8de01b7 4 * Based on code in sungem_phy.c and (long-removed) gianfar_phy.c
00db8189
AF
5 *
6 * Author: Andy Fleming
7 *
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
00db8189
AF
9 */
10
11#ifndef __PHY_H
12#define __PHY_H
13
2220943a 14#include <linux/compiler.h>
00db8189 15#include <linux/spinlock.h>
13df29f6 16#include <linux/ethtool.h>
01e5b728 17#include <linux/leds.h>
b31cdffa 18#include <linux/linkmode.h>
a68a8138 19#include <linux/netlink.h>
bac83c65 20#include <linux/mdio.h>
13df29f6 21#include <linux/mii.h>
4715f65f 22#include <linux/mii_timestamper.h>
3e3aaf64 23#include <linux/module.h>
13df29f6
MR
24#include <linux/timer.h>
25#include <linux/workqueue.h>
8626d3b4 26#include <linux/mod_devicetable.h>
080bb352 27#include <linux/u64_stats_sync.h>
9010f9de 28#include <linux/irqreturn.h>
bd971ff0 29#include <linux/iopoll.h>
63490847 30#include <linux/refcount.h>
00db8189 31
60063497 32#include <linux/atomic.h>
fe0d4fd9 33#include <net/eee.h>
0ac49527 34
719655a1
AL
35extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_features) __ro_after_init;
36extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_t1_features) __ro_after_init;
16178c8e 37extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_t1s_p2mp_features) __ro_after_init;
719655a1
AL
38extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_features) __ro_after_init;
39extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_fibre_features) __ro_after_init;
719655a1 40extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_features) __ro_after_init;
14e47d1f 41extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_eee_cap1_features) __ro_after_init;
ef6ee3a3 42extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_eee_cap2_features) __ro_after_init;
719655a1
AL
43
44#define PHY_BASIC_FEATURES ((unsigned long *)&phy_basic_features)
45#define PHY_BASIC_T1_FEATURES ((unsigned long *)&phy_basic_t1_features)
16178c8e 46#define PHY_BASIC_T1S_P2MP_FEATURES ((unsigned long *)&phy_basic_t1s_p2mp_features)
719655a1
AL
47#define PHY_GBIT_FEATURES ((unsigned long *)&phy_gbit_features)
48#define PHY_GBIT_FIBRE_FEATURES ((unsigned long *)&phy_gbit_fibre_features)
719655a1 49#define PHY_10GBIT_FEATURES ((unsigned long *)&phy_10gbit_features)
14e47d1f 50#define PHY_EEE_CAP1_FEATURES ((unsigned long *)&phy_eee_cap1_features)
ef6ee3a3 51#define PHY_EEE_CAP2_FEATURES ((unsigned long *)&phy_eee_cap2_features)
e9fbdf17 52
54638c6e 53extern const int phy_basic_ports_array[3];
3c1bcc86 54
c5e38a94
AF
55/*
56 * Set phydev->irq to PHY_POLL if interrupts are not supported,
93e8990c
HK
57 * or not desired for this PHY. Set to PHY_MAC_INTERRUPT if
58 * the attached MAC driver handles the interrupt
00db8189
AF
59 */
60#define PHY_POLL -1
93e8990c 61#define PHY_MAC_INTERRUPT -2
00db8189 62
a4307c0e
HK
63#define PHY_IS_INTERNAL 0x00000001
64#define PHY_RST_AFTER_CLK_EN 0x00000002
97c22438 65#define PHY_POLL_CABLE_TEST 0x00000004
a7e34480 66#define PHY_ALWAYS_CALL_SUSPEND 0x00000008
a9049e0c 67#define MDIO_DEVICE_IS_PHY 0x80000000
00db8189 68
4069a572
AL
69/**
70 * enum phy_interface_t - Interface Mode definitions
71 *
72 * @PHY_INTERFACE_MODE_NA: Not Applicable - don't touch
73 * @PHY_INTERFACE_MODE_INTERNAL: No interface, MAC and PHY combined
26183cfe
CF
74 * @PHY_INTERFACE_MODE_MII: Media-independent interface
75 * @PHY_INTERFACE_MODE_GMII: Gigabit media-independent interface
4069a572
AL
76 * @PHY_INTERFACE_MODE_SGMII: Serial gigabit media-independent interface
77 * @PHY_INTERFACE_MODE_TBI: Ten Bit Interface
78 * @PHY_INTERFACE_MODE_REVMII: Reverse Media Independent Interface
79 * @PHY_INTERFACE_MODE_RMII: Reduced Media Independent Interface
c858d436 80 * @PHY_INTERFACE_MODE_REVRMII: Reduced Media Independent Interface in PHY role
4069a572
AL
81 * @PHY_INTERFACE_MODE_RGMII: Reduced gigabit media-independent interface
82 * @PHY_INTERFACE_MODE_RGMII_ID: RGMII with Internal RX+TX delay
83 * @PHY_INTERFACE_MODE_RGMII_RXID: RGMII with Internal RX delay
ca1914a3 84 * @PHY_INTERFACE_MODE_RGMII_TXID: RGMII with Internal TX delay
4069a572 85 * @PHY_INTERFACE_MODE_RTBI: Reduced TBI
b9241f54 86 * @PHY_INTERFACE_MODE_SMII: Serial MII
4069a572
AL
87 * @PHY_INTERFACE_MODE_XGMII: 10 gigabit media-independent interface
88 * @PHY_INTERFACE_MODE_XLGMII:40 gigabit media-independent interface
89 * @PHY_INTERFACE_MODE_MOCA: Multimedia over Coax
83b5f025 90 * @PHY_INTERFACE_MODE_PSGMII: Penta SGMII
4069a572
AL
91 * @PHY_INTERFACE_MODE_QSGMII: Quad SGMII
92 * @PHY_INTERFACE_MODE_TRGMII: Turbo RGMII
b1ae3587 93 * @PHY_INTERFACE_MODE_100BASEX: 100 BaseX
4069a572
AL
94 * @PHY_INTERFACE_MODE_1000BASEX: 1000 BaseX
95 * @PHY_INTERFACE_MODE_2500BASEX: 2500 BaseX
7331d1d4 96 * @PHY_INTERFACE_MODE_5GBASER: 5G BaseR
4069a572
AL
97 * @PHY_INTERFACE_MODE_RXAUI: Reduced XAUI
98 * @PHY_INTERFACE_MODE_XAUI: 10 Gigabit Attachment Unit Interface
99 * @PHY_INTERFACE_MODE_10GBASER: 10G BaseR
a56c2868 100 * @PHY_INTERFACE_MODE_25GBASER: 25G BaseR
4069a572
AL
101 * @PHY_INTERFACE_MODE_USXGMII: Universal Serial 10GE MII
102 * @PHY_INTERFACE_MODE_10GKR: 10GBASE-KR - with Clause 73 AN
5e61fe15 103 * @PHY_INTERFACE_MODE_QUSGMII: Quad Universal SGMII
05ad5d45 104 * @PHY_INTERFACE_MODE_1000BASEKX: 1000Base-KX - with Clause 73 AN
777b8afb 105 * @PHY_INTERFACE_MODE_10G_QXGMII: 10G-QXGMII - 4 ports over 10G USXGMII
4069a572
AL
106 * @PHY_INTERFACE_MODE_MAX: Book keeping
107 *
108 * Describes the interface between the MAC and PHY.
109 */
e8a2b6a4 110typedef enum {
4157ef1b 111 PHY_INTERFACE_MODE_NA,
735d8a18 112 PHY_INTERFACE_MODE_INTERNAL,
e8a2b6a4
AF
113 PHY_INTERFACE_MODE_MII,
114 PHY_INTERFACE_MODE_GMII,
115 PHY_INTERFACE_MODE_SGMII,
116 PHY_INTERFACE_MODE_TBI,
2cc70ba4 117 PHY_INTERFACE_MODE_REVMII,
e8a2b6a4 118 PHY_INTERFACE_MODE_RMII,
c858d436 119 PHY_INTERFACE_MODE_REVRMII,
e8a2b6a4 120 PHY_INTERFACE_MODE_RGMII,
a999589c 121 PHY_INTERFACE_MODE_RGMII_ID,
7d400a4c
KP
122 PHY_INTERFACE_MODE_RGMII_RXID,
123 PHY_INTERFACE_MODE_RGMII_TXID,
4157ef1b
SG
124 PHY_INTERFACE_MODE_RTBI,
125 PHY_INTERFACE_MODE_SMII,
898dd0bd 126 PHY_INTERFACE_MODE_XGMII,
58b05e58 127 PHY_INTERFACE_MODE_XLGMII,
fd70f72c 128 PHY_INTERFACE_MODE_MOCA,
83b5f025 129 PHY_INTERFACE_MODE_PSGMII,
b9d12085 130 PHY_INTERFACE_MODE_QSGMII,
572de608 131 PHY_INTERFACE_MODE_TRGMII,
b1ae3587 132 PHY_INTERFACE_MODE_100BASEX,
55601a88
AL
133 PHY_INTERFACE_MODE_1000BASEX,
134 PHY_INTERFACE_MODE_2500BASEX,
7331d1d4 135 PHY_INTERFACE_MODE_5GBASER,
55601a88 136 PHY_INTERFACE_MODE_RXAUI,
c125ca09 137 PHY_INTERFACE_MODE_XAUI,
c114574e
RK
138 /* 10GBASE-R, XFI, SFI - single lane 10G Serdes */
139 PHY_INTERFACE_MODE_10GBASER,
a56c2868 140 PHY_INTERFACE_MODE_25GBASER,
4618d671 141 PHY_INTERFACE_MODE_USXGMII,
c114574e
RK
142 /* 10GBASE-KR - with Clause 73 AN */
143 PHY_INTERFACE_MODE_10GKR,
5e61fe15 144 PHY_INTERFACE_MODE_QUSGMII,
05ad5d45 145 PHY_INTERFACE_MODE_1000BASEKX,
777b8afb 146 PHY_INTERFACE_MODE_10G_QXGMII,
8a2fe56e 147 PHY_INTERFACE_MODE_MAX,
e8a2b6a4
AF
148} phy_interface_t;
149
8e20f591
RKO
150/* PHY interface mode bitmap handling */
151#define DECLARE_PHY_INTERFACE_MASK(name) \
152 DECLARE_BITMAP(name, PHY_INTERFACE_MODE_MAX)
153
154static inline void phy_interface_zero(unsigned long *intf)
155{
156 bitmap_zero(intf, PHY_INTERFACE_MODE_MAX);
157}
158
159static inline bool phy_interface_empty(const unsigned long *intf)
160{
161 return bitmap_empty(intf, PHY_INTERFACE_MODE_MAX);
162}
163
164static inline void phy_interface_and(unsigned long *dst, const unsigned long *a,
165 const unsigned long *b)
166{
167 bitmap_and(dst, a, b, PHY_INTERFACE_MODE_MAX);
168}
169
170static inline void phy_interface_or(unsigned long *dst, const unsigned long *a,
171 const unsigned long *b)
172{
173 bitmap_or(dst, a, b, PHY_INTERFACE_MODE_MAX);
174}
175
176static inline void phy_interface_set_rgmii(unsigned long *intf)
177{
178 __set_bit(PHY_INTERFACE_MODE_RGMII, intf);
179 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, intf);
180 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, intf);
181 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, intf);
182}
183
8a2fe56e 184/**
d8de01b7
RD
185 * phy_modes - map phy_interface_t enum to device tree binding of phy-mode
186 * @interface: enum phy_interface_t value
187 *
4069a572 188 * Description: maps enum &phy_interface_t defined in this file
8a2fe56e 189 * into the device tree binding of 'phy-mode', so that Ethernet
4069a572 190 * device driver can get PHY interface from device tree.
8a2fe56e
FF
191 */
192static inline const char *phy_modes(phy_interface_t interface)
193{
194 switch (interface) {
195 case PHY_INTERFACE_MODE_NA:
196 return "";
735d8a18
FF
197 case PHY_INTERFACE_MODE_INTERNAL:
198 return "internal";
8a2fe56e
FF
199 case PHY_INTERFACE_MODE_MII:
200 return "mii";
201 case PHY_INTERFACE_MODE_GMII:
202 return "gmii";
203 case PHY_INTERFACE_MODE_SGMII:
204 return "sgmii";
205 case PHY_INTERFACE_MODE_TBI:
206 return "tbi";
207 case PHY_INTERFACE_MODE_REVMII:
208 return "rev-mii";
209 case PHY_INTERFACE_MODE_RMII:
210 return "rmii";
c858d436
VO
211 case PHY_INTERFACE_MODE_REVRMII:
212 return "rev-rmii";
8a2fe56e
FF
213 case PHY_INTERFACE_MODE_RGMII:
214 return "rgmii";
215 case PHY_INTERFACE_MODE_RGMII_ID:
216 return "rgmii-id";
217 case PHY_INTERFACE_MODE_RGMII_RXID:
218 return "rgmii-rxid";
219 case PHY_INTERFACE_MODE_RGMII_TXID:
220 return "rgmii-txid";
221 case PHY_INTERFACE_MODE_RTBI:
222 return "rtbi";
223 case PHY_INTERFACE_MODE_SMII:
224 return "smii";
225 case PHY_INTERFACE_MODE_XGMII:
226 return "xgmii";
58b05e58
JA
227 case PHY_INTERFACE_MODE_XLGMII:
228 return "xlgmii";
fd70f72c
FF
229 case PHY_INTERFACE_MODE_MOCA:
230 return "moca";
83b5f025
GJ
231 case PHY_INTERFACE_MODE_PSGMII:
232 return "psgmii";
b9d12085
TP
233 case PHY_INTERFACE_MODE_QSGMII:
234 return "qsgmii";
572de608
SW
235 case PHY_INTERFACE_MODE_TRGMII:
236 return "trgmii";
55601a88
AL
237 case PHY_INTERFACE_MODE_1000BASEX:
238 return "1000base-x";
05ad5d45
SA
239 case PHY_INTERFACE_MODE_1000BASEKX:
240 return "1000base-kx";
55601a88
AL
241 case PHY_INTERFACE_MODE_2500BASEX:
242 return "2500base-x";
7331d1d4
PS
243 case PHY_INTERFACE_MODE_5GBASER:
244 return "5gbase-r";
55601a88
AL
245 case PHY_INTERFACE_MODE_RXAUI:
246 return "rxaui";
c125ca09
RK
247 case PHY_INTERFACE_MODE_XAUI:
248 return "xaui";
c114574e
RK
249 case PHY_INTERFACE_MODE_10GBASER:
250 return "10gbase-r";
a56c2868
SH
251 case PHY_INTERFACE_MODE_25GBASER:
252 return "25gbase-r";
4618d671
HK
253 case PHY_INTERFACE_MODE_USXGMII:
254 return "usxgmii";
c114574e
RK
255 case PHY_INTERFACE_MODE_10GKR:
256 return "10gbase-kr";
b1ae3587
BJ
257 case PHY_INTERFACE_MODE_100BASEX:
258 return "100base-x";
5e61fe15
MC
259 case PHY_INTERFACE_MODE_QUSGMII:
260 return "qusgmii";
777b8afb
VO
261 case PHY_INTERFACE_MODE_10G_QXGMII:
262 return "10g-qxgmii";
8a2fe56e
FF
263 default:
264 return "unknown";
265 }
266}
267
386aa60a
JPO
268/**
269 * rgmii_clock - map link speed to the clock rate
270 * @speed: link speed value
271 *
272 * Description: maps RGMII supported link speeds
273 * into the clock rates.
274 *
275 * Returns: clock rate or negative errno
276 */
277static inline long rgmii_clock(int speed)
278{
279 switch (speed) {
280 case SPEED_10:
281 return 2500000;
282 case SPEED_100:
283 return 25000000;
284 case SPEED_1000:
285 return 125000000;
286 default:
287 return -EINVAL;
288 }
289}
290
e8a2b6a4 291#define PHY_MAX_ADDR 32
00db8189 292
a4d00f17 293/* Used when trying to connect to a specific phy (mii bus id:phy device id) */
9d9326d3 294#define PHY_ID_FMT "%s:%02x"
2c5ac026 295#define PHY_ID_SIZE (MII_BUS_ID_SIZE + 3)
9d9326d3 296
4567d686 297#define MII_BUS_ID_SIZE 61
a4d00f17 298
313162d0 299struct device;
60495b66 300struct kernel_hwtstamp_config;
9525ae83 301struct phylink;
298e54fa
RK
302struct sfp_bus;
303struct sfp_upstream_ops;
313162d0
PG
304struct sk_buff;
305
4069a572
AL
306/**
307 * struct mdio_bus_stats - Statistics counters for MDIO busses
308 * @transfers: Total number of transfers, i.e. @writes + @reads
309 * @errors: Number of MDIO transfers that returned an error
310 * @writes: Number of write transfers
311 * @reads: Number of read transfers
312 * @syncp: Synchronisation for incrementing statistics
313 */
080bb352
FF
314struct mdio_bus_stats {
315 u64_stats_t transfers;
316 u64_stats_t errors;
317 u64_stats_t writes;
318 u64_stats_t reads;
319 /* Must be last, add new statistics above */
320 struct u64_stats_sync syncp;
321};
322
4069a572
AL
323/**
324 * struct mii_bus - Represents an MDIO bus
325 *
326 * @owner: Who owns this device
327 * @name: User friendly name for this MDIO device, or driver name
328 * @id: Unique identifier for this bus, typical from bus hierarchy
329 * @priv: Driver private data
330 *
c5e38a94
AF
331 * The Bus class for PHYs. Devices which provide access to
332 * PHYs should register using this structure
333 */
00db8189 334struct mii_bus {
3e3aaf64 335 struct module *owner;
00db8189 336 const char *name;
9d9326d3 337 char id[MII_BUS_ID_SIZE];
00db8189 338 void *priv;
4069a572 339 /** @read: Perform a read transfer on the bus */
ccaa953e 340 int (*read)(struct mii_bus *bus, int addr, int regnum);
4069a572 341 /** @write: Perform a write transfer on the bus */
ccaa953e 342 int (*write)(struct mii_bus *bus, int addr, int regnum, u16 val);
4e4aafcd
AL
343 /** @read_c45: Perform a C45 read transfer on the bus */
344 int (*read_c45)(struct mii_bus *bus, int addr, int devnum, int regnum);
345 /** @write_c45: Perform a C45 write transfer on the bus */
346 int (*write_c45)(struct mii_bus *bus, int addr, int devnum,
347 int regnum, u16 val);
4069a572 348 /** @reset: Perform a reset of the bus */
00db8189 349 int (*reset)(struct mii_bus *bus);
4069a572
AL
350
351 /** @stats: Statistic counters per device on the bus */
080bb352 352 struct mdio_bus_stats stats[PHY_MAX_ADDR];
00db8189 353
4069a572
AL
354 /**
355 * @mdio_lock: A lock to ensure that only one thing can read/write
c5e38a94
AF
356 * the MDIO bus at a time
357 */
35b5f6b1 358 struct mutex mdio_lock;
00db8189 359
4069a572 360 /** @parent: Parent device of this bus */
18ee49dd 361 struct device *parent;
4069a572 362 /** @state: State of bus structure */
46abc021
LB
363 enum {
364 MDIOBUS_ALLOCATED = 1,
365 MDIOBUS_REGISTERED,
366 MDIOBUS_UNREGISTERED,
367 MDIOBUS_RELEASED,
368 } state;
4069a572
AL
369
370 /** @dev: Kernel device representation */
46abc021 371 struct device dev;
00db8189 372
4069a572 373 /** @mdio_map: list of all MDIO devices on bus */
7f854420 374 struct mdio_device *mdio_map[PHY_MAX_ADDR];
00db8189 375
4069a572 376 /** @phy_mask: PHY addresses to be ignored when probing */
f896424c
MP
377 u32 phy_mask;
378
4069a572 379 /** @phy_ignore_ta_mask: PHY addresses to ignore the TA/read failure */
922f2dd1
FF
380 u32 phy_ignore_ta_mask;
381
4069a572
AL
382 /**
383 * @irq: An array of interrupts, each PHY's interrupt at the index
e7f4dc35 384 * matching its address
c5e38a94 385 */
e7f4dc35 386 int irq[PHY_MAX_ADDR];
69226896 387
4069a572 388 /** @reset_delay_us: GPIO reset pulse width in microseconds */
69226896 389 int reset_delay_us;
4069a572 390 /** @reset_post_delay_us: GPIO reset deassert delay in microseconds */
bb383129 391 int reset_post_delay_us;
4069a572 392 /** @reset_gpiod: Reset GPIO descriptor pointer */
d396e84c 393 struct gpio_desc *reset_gpiod;
63490847 394
4069a572 395 /** @shared_lock: protect access to the shared element */
63490847
MW
396 struct mutex shared_lock;
397
4069a572 398 /** @shared: shared state across different PHYs */
63490847 399 struct phy_package_shared *shared[PHY_MAX_ADDR];
00db8189 400};
46abc021 401#define to_mii_bus(d) container_of(d, struct mii_bus, dev)
00db8189 402
4069a572
AL
403struct mii_bus *mdiobus_alloc_size(size_t size);
404
405/**
406 * mdiobus_alloc - Allocate an MDIO bus structure
407 *
408 * The internal state of the MDIO bus will be set of MDIOBUS_ALLOCATED ready
409 * for the driver to register the bus.
410 */
eb8a54a7
TT
411static inline struct mii_bus *mdiobus_alloc(void)
412{
413 return mdiobus_alloc_size(0);
414}
415
3e3aaf64 416int __mdiobus_register(struct mii_bus *bus, struct module *owner);
ac3a68d5
BG
417int __devm_mdiobus_register(struct device *dev, struct mii_bus *bus,
418 struct module *owner);
3e3aaf64 419#define mdiobus_register(bus) __mdiobus_register(bus, THIS_MODULE)
ac3a68d5
BG
420#define devm_mdiobus_register(dev, bus) \
421 __devm_mdiobus_register(dev, bus, THIS_MODULE)
38f961e7 422
2e888103
LB
423void mdiobus_unregister(struct mii_bus *bus);
424void mdiobus_free(struct mii_bus *bus);
6d48f44b
GS
425struct mii_bus *devm_mdiobus_alloc_size(struct device *dev, int sizeof_priv);
426static inline struct mii_bus *devm_mdiobus_alloc(struct device *dev)
427{
428 return devm_mdiobus_alloc_size(dev, 0);
429}
430
ce69e216 431struct mii_bus *mdio_find_bus(const char *mdio_name);
d41e1277 432struct phy_device *mdiobus_scan_c22(struct mii_bus *bus, int addr);
2e888103 433
695bce8f
HK
434#define PHY_INTERRUPT_DISABLED false
435#define PHY_INTERRUPT_ENABLED true
00db8189 436
4069a572
AL
437/**
438 * enum phy_state - PHY state machine states:
00db8189 439 *
4069a572 440 * @PHY_DOWN: PHY device and driver are not ready for anything. probe
00db8189
AF
441 * should be called if and only if the PHY is in this state,
442 * given that the PHY device exists.
4069a572 443 * - PHY driver probe function will set the state to @PHY_READY
00db8189 444 *
4069a572 445 * @PHY_READY: PHY is ready to send and receive packets, but the
00db8189 446 * controller is not. By default, PHYs which do not implement
899a3cbb 447 * probe will be set to this state by phy_probe().
00db8189
AF
448 * - start will set the state to UP
449 *
4069a572 450 * @PHY_UP: The PHY and attached device are ready to do work.
00db8189 451 * Interrupts should be started here.
4069a572 452 * - timer moves to @PHY_NOLINK or @PHY_RUNNING
00db8189 453 *
4069a572
AL
454 * @PHY_NOLINK: PHY is up, but not currently plugged in.
455 * - irq or timer will set @PHY_RUNNING if link comes back
456 * - phy_stop moves to @PHY_HALTED
00db8189 457 *
4069a572 458 * @PHY_RUNNING: PHY is currently up, running, and possibly sending
00db8189 459 * and/or receiving packets
4069a572
AL
460 * - irq or timer will set @PHY_NOLINK if link goes down
461 * - phy_stop moves to @PHY_HALTED
00db8189 462 *
4069a572 463 * @PHY_CABLETEST: PHY is performing a cable test. Packet reception/sending
a68a8138
AL
464 * is not expected to work, carrier will be indicated as down. PHY will be
465 * poll once per second, or on interrupt for it current state.
466 * Once complete, move to UP to restart the PHY.
4069a572 467 * - phy_stop aborts the running test and moves to @PHY_HALTED
a68a8138 468 *
59088b5a 469 * @PHY_HALTED: PHY is up, but no polling or interrupts are done.
4069a572 470 * - phy_start moves to @PHY_UP
59088b5a
RKO
471 *
472 * @PHY_ERROR: PHY is up, but is in an error state.
473 * - phy_stop moves to @PHY_HALTED
00db8189
AF
474 */
475enum phy_state {
4017b4d3 476 PHY_DOWN = 0,
00db8189 477 PHY_READY,
2b3e88ea 478 PHY_HALTED,
59088b5a 479 PHY_ERROR,
00db8189 480 PHY_UP,
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481 PHY_RUNNING,
482 PHY_NOLINK,
a68a8138 483 PHY_CABLETEST,
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484};
485
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486#define MDIO_MMD_NUM 32
487
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488/**
489 * struct phy_c45_device_ids - 802.3-c45 Device Identifiers
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490 * @devices_in_package: IEEE 802.3 devices in package register value.
491 * @mmds_present: bit vector of MMDs present.
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492 * @device_ids: The device identifer for each present device.
493 */
494struct phy_c45_device_ids {
495 u32 devices_in_package;
320ed3bf 496 u32 mmds_present;
389a3389 497 u32 device_ids[MDIO_MMD_NUM];
ac28b9f8 498};
c1f19b51 499
76564261 500struct macsec_context;
2e181358 501struct macsec_ops;
76564261 502
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503/**
504 * struct phy_device - An instance of a PHY
00db8189 505 *
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506 * @mdio: MDIO bus this PHY is on
507 * @drv: Pointer to the driver for this PHY instance
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508 * @devlink: Create a link between phy dev and mac dev, if the external phy
509 * used by current mac interface is managed by another mac interface.
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510 * @phyindex: Unique id across the phy's parent tree of phys to address the PHY
511 * from userspace, similar to ifindex. A zero index means the PHY
512 * wasn't assigned an id yet.
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513 * @phy_id: UID for this device found during discovery
514 * @c45_ids: 802.3-c45 Device Identifiers if is_c45.
515 * @is_c45: Set to true if this PHY uses clause 45 addressing.
516 * @is_internal: Set to true if this PHY is internal to a MAC.
517 * @is_pseudo_fixed_link: Set to true if this PHY is an Ethernet switch, etc.
518 * @is_gigabit_capable: Set to true if PHY supports 1000Mbps
519 * @has_fixups: Set to true if this PHY has fixups/quirks.
520 * @suspended: Set to true if this PHY has been suspended successfully.
521 * @suspended_by_mdio_bus: Set to true if this PHY was suspended by MDIO bus.
522 * @sysfs_links: Internal boolean tracking sysfs symbolic links setup/removal.
523 * @loopback_enabled: Set true if this PHY has been loopbacked successfully.
524 * @downshifted_rate: Set true if link speed has been downshifted.
b834489b 525 * @is_on_sfp_module: Set true if PHY is located on an SFP module.
fba863b8 526 * @mac_managed_pm: Set true if MAC driver takes of suspending/resuming PHY
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527 * @wol_enabled: Set to true if the PHY or the attached MAC have Wake-on-LAN
528 * enabled.
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529 * @state: State of the PHY for management purposes
530 * @dev_flags: Device-specific flags used by the PHY driver.
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531 *
532 * - Bits [15:0] are free to use by the PHY driver to communicate
533 * driver specific behavior.
534 * - Bits [23:16] are currently reserved for future use.
535 * - Bits [31:24] are reserved for defining generic
536 * PHY driver behavior.
4069a572 537 * @irq: IRQ number of the PHY's interrupt (-1 if none)
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538 * @phylink: Pointer to phylink instance for this PHY
539 * @sfp_bus_attached: Flag indicating whether the SFP bus has been attached
540 * @sfp_bus: SFP bus attached to this PHY's fiber port
541 * @attached_dev: The attached enet driver's device instance ptr
542 * @adjust_link: Callback for the enet controller to respond to changes: in the
543 * link state.
544 * @phy_link_change: Callback for phylink for notification of link change
545 * @macsec_ops: MACsec offloading ops.
00db8189 546 *
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547 * @speed: Current link speed
548 * @duplex: Current duplex
4217a64e 549 * @port: Current port
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550 * @pause: Current pause
551 * @asym_pause: Current asymmetric pause
552 * @supported: Combined MAC/PHY supported linkmodes
553 * @advertising: Currently advertised linkmodes
554 * @adv_old: Saved advertised while power saving for WoL
14e47d1f 555 * @supported_eee: supported PHY EEE linkmodes
3eeca4e1 556 * @advertising_eee: Currently advertised EEE linkmodes
e3b6876a 557 * @enable_tx_lpi: When True, MAC should transmit LPI to PHY
e2668c34 558 * @eee_active: phylib private state, indicating that EEE has been negotiated
fe0d4fd9 559 * @eee_cfg: User configuration of EEE
4069a572 560 * @lp_advertising: Current link partner advertised linkmodes
eca68a3c 561 * @host_interfaces: PHY interface modes supported by host
8eb0d381 562 * @eee_disabled_modes: Energy efficient ethernet modes not to be advertised
4069a572 563 * @autoneg: Flag autoneg being used
0c3e10cb 564 * @rate_matching: Current rate matching mode
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565 * @link: Current link state
566 * @autoneg_complete: Flag auto negotiation of the link has completed
567 * @mdix: Current crossover
568 * @mdix_ctrl: User setting of crossover
3da8ffd8 569 * @pma_extable: Cached value of PMA/PMD Extended Abilities Register
4069a572 570 * @interrupts: Flag interrupts have been enabled
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571 * @irq_suspended: Flag indicating PHY is suspended and therefore interrupt
572 * handling shall be postponed until PHY has resumed
573 * @irq_rerun: Flag indicating interrupts occurred while PHY was suspended,
574 * requiring a rerun of the interrupt handler after resume
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575 * @default_timestamp: Flag indicating whether we are using the phy
576 * timestamp as the default one
4069a572 577 * @interface: enum phy_interface_t value
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578 * @possible_interfaces: bitmap if interface modes that the attached PHY
579 * will switch between depending on media speed.
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580 * @skb: Netlink message for cable diagnostics
581 * @nest: Netlink nest used for cable diagnostics
582 * @ehdr: nNtlink header for cable diagnostics
583 * @phy_led_triggers: Array of LED triggers
584 * @phy_num_led_triggers: Number of triggers in @phy_led_triggers
585 * @led_link_trigger: LED trigger for link up/down
586 * @last_triggered: last LED trigger for link speed
01e5b728 587 * @leds: list of PHY LED structures
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588 * @master_slave_set: User requested master/slave configuration
589 * @master_slave_get: Current master/slave advertisement
590 * @master_slave_state: Current master/slave configuration
591 * @mii_ts: Pointer to time stamper callbacks
5e82147d 592 * @psec: Pointer to Power Sourcing Equipment control struct
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593 * @lock: Mutex for serialization access to PHY
594 * @state_queue: Work queue for state machine
9a0f830f 595 * @link_down_events: Number of times link was lost
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596 * @shared: Pointer to private data shared by phys in one package
597 * @priv: Pointer to driver private data
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598 *
599 * interrupts currently only supports enabled or disabled,
600 * but could be changed in the future to support enabling
601 * and disabling specific interrupts
602 *
603 * Contains some infrastructure for polling and interrupt
604 * handling, as well as handling shifts in PHY hardware state
605 */
606struct phy_device {
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607 struct mdio_device mdio;
608
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609 /* Information about the PHY type */
610 /* And management functions */
0bd199fd 611 const struct phy_driver *drv;
00db8189 612
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613 struct device_link *devlink;
614
38496878 615 u32 phyindex;
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616 u32 phy_id;
617
ac28b9f8 618 struct phy_c45_device_ids c45_ids;
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619 unsigned is_c45:1;
620 unsigned is_internal:1;
621 unsigned is_pseudo_fixed_link:1;
3b8b11f9 622 unsigned is_gigabit_capable:1;
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623 unsigned has_fixups:1;
624 unsigned suspended:1;
611d779a 625 unsigned suspended_by_mdio_bus:1;
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626 unsigned sysfs_links:1;
627 unsigned loopback_enabled:1;
5eee3bb7 628 unsigned downshifted_rate:1;
b834489b 629 unsigned is_on_sfp_module:1;
fba863b8 630 unsigned mac_managed_pm:1;
a7e34480 631 unsigned wol_enabled:1;
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632
633 unsigned autoneg:1;
634 /* The most recently read link state */
635 unsigned link:1;
4950c2ba 636 unsigned autoneg_complete:1;
ac28b9f8 637
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638 /* Interrupts are enabled */
639 unsigned interrupts:1;
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640 unsigned irq_suspended:1;
641 unsigned irq_rerun:1;
695bce8f 642
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643 unsigned default_timestamp:1;
644
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645 int rate_matching;
646
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647 enum phy_state state;
648
649 u32 dev_flags;
650
e8a2b6a4 651 phy_interface_t interface;
243ad8df 652 DECLARE_PHY_INTERFACE_MASK(possible_interfaces);
e8a2b6a4 653
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654 /*
655 * forced speed & duplex (no autoneg)
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656 * partner speed & duplex & pause (autoneg)
657 */
658 int speed;
659 int duplex;
4217a64e 660 int port;
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661 int pause;
662 int asym_pause;
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663 u8 master_slave_get;
664 u8 master_slave_set;
665 u8 master_slave_state;
00db8189 666
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667 /* Union of PHY and Attached devices' supported link modes */
668 /* See ethtool.h for more info */
669 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
670 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
c0ec3c27 671 __ETHTOOL_DECLARE_LINK_MODE_MASK(lp_advertising);
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672 /* used with phy_speed_down */
673 __ETHTOOL_DECLARE_LINK_MODE_MASK(adv_old);
49168d19 674 /* used for eee validation and configuration*/
14e47d1f 675 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported_eee);
3eeca4e1 676 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising_eee);
d853d145 677 /* Energy efficient ethernet modes which should be prohibited */
8eb0d381 678 __ETHTOOL_DECLARE_LINK_MODE_MASK(eee_disabled_modes);
e3b6876a 679 bool enable_tx_lpi;
e2668c34 680 bool eee_active;
fe0d4fd9 681 struct eee_config eee_cfg;
d853d145 682
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683 /* Host supported PHY interface types. Should be ignored if empty. */
684 DECLARE_PHY_INTERFACE_MASK(host_interfaces);
685
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686#ifdef CONFIG_LED_TRIGGER_PHY
687 struct phy_led_trigger *phy_led_triggers;
688 unsigned int phy_num_led_triggers;
689 struct phy_led_trigger *last_triggered;
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690
691 struct phy_led_trigger *led_link_trigger;
2e0bc452 692#endif
01e5b728 693 struct list_head leds;
2e0bc452 694
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695 /*
696 * Interrupt number for this PHY
697 * -1 means no interrupt
698 */
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699 int irq;
700
701 /* private data pointer */
702 /* For use by PHYs to maintain extra state */
703 void *priv;
704
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705 /* shared data pointer */
706 /* For use by PHYs inside the same package that need a shared state. */
707 struct phy_package_shared *shared;
708
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709 /* Reporting cable test results */
710 struct sk_buff *skb;
711 void *ehdr;
712 struct nlattr *nest;
713
00db8189 714 /* Interrupt and Polling infrastructure */
a390d1f3 715 struct delayed_work state_queue;
00db8189 716
35b5f6b1 717 struct mutex lock;
00db8189 718
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719 /* This may be modified under the rtnl lock */
720 bool sfp_bus_attached;
721 struct sfp_bus *sfp_bus;
9525ae83 722 struct phylink *phylink;
00db8189 723 struct net_device *attached_dev;
4715f65f 724 struct mii_timestamper *mii_ts;
5e82147d 725 struct pse_control *psec;
00db8189 726
634ec36c 727 u8 mdix;
f4ed2fe3 728 u8 mdix_ctrl;
634ec36c 729
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AT
730 int pma_extable;
731
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732 unsigned int link_down_events;
733
a307593a 734 void (*phy_link_change)(struct phy_device *phydev, bool up);
00db8189 735 void (*adjust_link)(struct net_device *dev);
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736
737#if IS_ENABLED(CONFIG_MACSEC)
738 /* MACsec management functions */
739 const struct macsec_ops *macsec_ops;
740#endif
00db8189 741};
7eab14de 742
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743/* Generic phy_device::dev_flags */
744#define PHY_F_NO_IRQ 0x80000000
21d9ba5b 745#define PHY_F_RXC_ALWAYS_ON 0x40000000
7d885863 746
e9cb9296 747#define to_phy_device(__dev) container_of_const(to_mdio_device(__dev), struct phy_device, mdio)
00db8189 748
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749/**
750 * struct phy_tdr_config - Configuration of a TDR raw test
751 *
752 * @first: Distance for first data collection point
753 * @last: Distance for last data collection point
754 * @step: Step between data collection points
755 * @pair: Bitmap of cable pairs to collect data for
756 *
757 * A structure containing possible configuration parameters
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758 * for a TDR cable test. The driver does not need to implement
759 * all the parameters, but should report what is actually used.
4069a572 760 * All distances are in centimeters.
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761 */
762struct phy_tdr_config {
763 u32 first;
764 u32 last;
765 u32 step;
766 s8 pair;
767};
768#define PHY_PAIR_ALL -1
769
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770/**
771 * enum link_inband_signalling - in-band signalling modes that are supported
772 *
773 * @LINK_INBAND_DISABLE: in-band signalling can be disabled
774 * @LINK_INBAND_ENABLE: in-band signalling can be enabled without bypass
775 * @LINK_INBAND_BYPASS: in-band signalling can be enabled with bypass
776 *
777 * The possible and required bits can only be used if the valid bit is set.
778 * If possible is clear, that means inband signalling can not be used.
779 * Required is only valid when possible is set, and means that inband
780 * signalling must be used.
781 */
782enum link_inband_signalling {
783 LINK_INBAND_DISABLE = BIT(0),
784 LINK_INBAND_ENABLE = BIT(1),
785 LINK_INBAND_BYPASS = BIT(2),
786};
787
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788/**
789 * struct phy_plca_cfg - Configuration of the PLCA (Physical Layer Collision
790 * Avoidance) Reconciliation Sublayer.
791 *
792 * @version: read-only PLCA register map version. -1 = not available. Ignored
793 * when setting the configuration. Format is the same as reported by the PLCA
794 * IDVER register (31.CA00). -1 = not available.
795 * @enabled: PLCA configured mode (enabled/disabled). -1 = not available / don't
796 * set. 0 = disabled, anything else = enabled.
797 * @node_id: the PLCA local node identifier. -1 = not available / don't set.
798 * Allowed values [0 .. 254]. 255 = node disabled.
799 * @node_cnt: the PLCA node count (maximum number of nodes having a TO). Only
800 * meaningful for the coordinator (node_id = 0). -1 = not available / don't
801 * set. Allowed values [1 .. 255].
802 * @to_tmr: The value of the PLCA to_timer in bit-times, which determines the
803 * PLCA transmit opportunity window opening. See IEEE802.3 Clause 148 for
804 * more details. The to_timer shall be set equal over all nodes.
805 * -1 = not available / don't set. Allowed values [0 .. 255].
806 * @burst_cnt: controls how many additional frames a node is allowed to send in
807 * single transmit opportunity (TO). The default value of 0 means that the
808 * node is allowed exactly one frame per TO. A value of 1 allows two frames
809 * per TO, and so on. -1 = not available / don't set.
810 * Allowed values [0 .. 255].
811 * @burst_tmr: controls how many bit times to wait for the MAC to send a new
812 * frame before interrupting the burst. This value should be set to a value
813 * greater than the MAC inter-packet gap (which is typically 96 bits).
814 * -1 = not available / don't set. Allowed values [0 .. 255].
815 *
816 * A structure containing configuration parameters for setting/getting the PLCA
817 * RS configuration. The driver does not need to implement all the parameters,
818 * but should report what is actually used.
819 */
820struct phy_plca_cfg {
821 int version;
822 int enabled;
823 int node_id;
824 int node_cnt;
825 int to_tmr;
826 int burst_cnt;
827 int burst_tmr;
828};
829
830/**
831 * struct phy_plca_status - Status of the PLCA (Physical Layer Collision
832 * Avoidance) Reconciliation Sublayer.
833 *
834 * @pst: The PLCA status as reported by the PST bit in the PLCA STATUS
835 * register(31.CA03), indicating BEACON activity.
836 *
837 * A structure containing status information of the PLCA RS configuration.
838 * The driver does not need to implement all the parameters, but should report
839 * what is actually used.
840 */
841struct phy_plca_status {
842 bool pst;
843};
844
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845/* Modes for PHY LED configuration */
846enum phy_led_modes {
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DG
847 PHY_LED_ACTIVE_HIGH = 0,
848 PHY_LED_ACTIVE_LOW = 1,
849 PHY_LED_INACTIVE_HIGH_IMPEDANCE = 2,
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850
851 /* keep it last */
852 __PHY_LED_MODES_NUM,
853};
854
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855/**
856 * struct phy_led: An LED driven by the PHY
857 *
858 * @list: List of LEDs
68481818 859 * @phydev: PHY this LED is attached to
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860 * @led_cdev: Standard LED class structure
861 * @index: Number of the LED
862 */
863struct phy_led {
864 struct list_head list;
68481818 865 struct phy_device *phydev;
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866 struct led_classdev led_cdev;
867 u8 index;
868};
869
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870#define to_phy_led(d) container_of(d, struct phy_led, led_cdev)
871
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872/**
873 * struct phy_driver - Driver structure for a particular PHY type
00db8189 874 *
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875 * @mdiodrv: Data common to all MDIO devices
876 * @phy_id: The result of reading the UID registers of this PHY
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877 * type, and ANDing them with the phy_id_mask. This driver
878 * only works for PHYs with IDs which match this field
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879 * @name: The friendly name of this PHY type
880 * @phy_id_mask: Defines the important bits of the phy_id
881 * @features: A mandatory list of features (speed, duplex, etc)
3e64cf7a 882 * supported by this PHY
4069a572 883 * @flags: A bitfield defining certain other features this PHY
00db8189 884 * supports (like interrupts)
4069a572 885 * @driver_data: Static driver data
00db8189 886 *
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HK
887 * All functions are optional. If config_aneg or read_status
888 * are not implemented, the phy core uses the genphy versions.
889 * Note that none of these functions should be called from
890 * interrupt time. The goal is for the bus read/write functions
891 * to be able to block when the bus transaction is happening,
892 * and be freed up by an interrupt (The MPC85xx has this ability,
893 * though it is not currently supported in the driver).
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894 */
895struct phy_driver {
a9049e0c 896 struct mdio_driver_common mdiodrv;
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897 u32 phy_id;
898 char *name;
511e3036 899 u32 phy_id_mask;
719655a1 900 const unsigned long * const features;
00db8189 901 u32 flags;
860f6e9e 902 const void *driver_data;
00db8189 903
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904 /**
905 * @soft_reset: Called to issue a PHY software reset
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906 */
907 int (*soft_reset)(struct phy_device *phydev);
908
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909 /**
910 * @config_init: Called to initialize the PHY,
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911 * including after a reset
912 */
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913 int (*config_init)(struct phy_device *phydev);
914
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915 /**
916 * @probe: Called during discovery. Used to set
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917 * up device-specific structures, if any
918 */
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919 int (*probe)(struct phy_device *phydev);
920
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921 /**
922 * @get_features: Probe the hardware to determine what
923 * abilities it has. Should only set phydev->supported.
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924 */
925 int (*get_features)(struct phy_device *phydev);
926
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927 /**
928 * @inband_caps: query whether in-band is supported for the given PHY
929 * interface mode. Returns a bitmask of bits defined by enum
930 * link_inband_signalling.
931 */
932 unsigned int (*inband_caps)(struct phy_device *phydev,
933 phy_interface_t interface);
934
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935 /**
936 * @config_inband: configure in-band mode for the PHY
937 */
938 int (*config_inband)(struct phy_device *phydev, unsigned int modes);
939
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940 /**
941 * @get_rate_matching: Get the supported type of rate matching for a
942 * particular phy interface. This is used by phy consumers to determine
943 * whether to advertise lower-speed modes for that interface. It is
944 * assumed that if a rate matching mode is supported on an interface,
945 * then that interface's rate can be adapted to all slower link speeds
6d4cfcf9 946 * supported by the phy. If the interface is not supported, this should
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947 * return %RATE_MATCH_NONE.
948 */
949 int (*get_rate_matching)(struct phy_device *phydev,
950 phy_interface_t iface);
951
00db8189 952 /* PHY Power Management */
4069a572 953 /** @suspend: Suspend the hardware, saving state if needed */
00db8189 954 int (*suspend)(struct phy_device *phydev);
4069a572 955 /** @resume: Resume the hardware, restoring state if needed */
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956 int (*resume)(struct phy_device *phydev);
957
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958 /**
959 * @config_aneg: Configures the advertisement and resets
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960 * autonegotiation if phydev->autoneg is on,
961 * forces the speed to the current settings in phydev
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962 * if phydev->autoneg is off
963 */
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964 int (*config_aneg)(struct phy_device *phydev);
965
4069a572 966 /** @aneg_done: Determines the auto negotiation result */
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967 int (*aneg_done)(struct phy_device *phydev);
968
4069a572 969 /** @read_status: Determines the negotiated speed and duplex */
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970 int (*read_status)(struct phy_device *phydev);
971
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972 /**
973 * @config_intr: Enables or disables interrupts.
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974 * It should also clear any pending interrupts prior to enabling the
975 * IRQs and after disabling them.
a8729eb3 976 */
6527b938 977 int (*config_intr)(struct phy_device *phydev);
a8729eb3 978
4069a572 979 /** @handle_interrupt: Override default interrupt handling */
9010f9de 980 irqreturn_t (*handle_interrupt)(struct phy_device *phydev);
49644e68 981
4069a572 982 /** @remove: Clears up any memory if needed */
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983 void (*remove)(struct phy_device *phydev);
984
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985 /**
986 * @match_phy_device: Returns true if this is a suitable
987 * driver for the given phydev. If NULL, matching is based on
988 * phy_id and phy_id_mask.
a30e2c18 989 */
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990 int (*match_phy_device)(struct phy_device *phydev,
991 const struct phy_driver *phydrv);
a30e2c18 992
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993 /**
994 * @set_wol: Some devices (e.g. qnap TS-119P II) require PHY
995 * register changes to enable Wake on LAN, so set_wol is
996 * provided to be called in the ethernet driver's set_wol
997 * function.
998 */
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999 int (*set_wol)(struct phy_device *dev, struct ethtool_wolinfo *wol);
1000
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1001 /**
1002 * @get_wol: See set_wol, but for checking whether Wake on LAN
1003 * is enabled.
1004 */
42e836eb
MS
1005 void (*get_wol)(struct phy_device *dev, struct ethtool_wolinfo *wol);
1006
4069a572
AL
1007 /**
1008 * @link_change_notify: Called to inform a PHY device driver
1009 * when the core is about to change the link state. This
1010 * callback is supposed to be used as fixup hook for drivers
1011 * that need to take action when the link state
1012 * changes. Drivers are by no means allowed to mess with the
2b8f2a28
DM
1013 * PHY device structure in their implementations.
1014 */
1015 void (*link_change_notify)(struct phy_device *dev);
1016
4069a572
AL
1017 /**
1018 * @read_mmd: PHY specific driver override for reading a MMD
1019 * register. This function is optional for PHY specific
1020 * drivers. When not provided, the default MMD read function
1021 * will be used by phy_read_mmd(), which will use either a
1022 * direct read for Clause 45 PHYs or an indirect read for
1023 * Clause 22 PHYs. devnum is the MMD device number within the
1024 * PHY device, regnum is the register within the selected MMD
1025 * device.
1ee6b9bc
RK
1026 */
1027 int (*read_mmd)(struct phy_device *dev, int devnum, u16 regnum);
1028
4069a572
AL
1029 /**
1030 * @write_mmd: PHY specific driver override for writing a MMD
1031 * register. This function is optional for PHY specific
1032 * drivers. When not provided, the default MMD write function
1033 * will be used by phy_write_mmd(), which will use either a
1034 * direct write for Clause 45 PHYs, or an indirect write for
1035 * Clause 22 PHYs. devnum is the MMD device number within the
1036 * PHY device, regnum is the register within the selected MMD
1037 * device. val is the value to be written.
1ee6b9bc
RK
1038 */
1039 int (*write_mmd)(struct phy_device *dev, int devnum, u16 regnum,
1040 u16 val);
1041
4069a572 1042 /** @read_page: Return the current PHY register page number */
78ffc4ac 1043 int (*read_page)(struct phy_device *dev);
4069a572 1044 /** @write_page: Set the current PHY register page number */
78ffc4ac
RK
1045 int (*write_page)(struct phy_device *dev, int page);
1046
4069a572
AL
1047 /**
1048 * @module_info: Get the size and type of the eeprom contained
1049 * within a plug-in module
1050 */
2f438366
ES
1051 int (*module_info)(struct phy_device *dev,
1052 struct ethtool_modinfo *modinfo);
1053
4069a572
AL
1054 /**
1055 * @module_eeprom: Get the eeprom information from the plug-in
1056 * module
1057 */
2f438366
ES
1058 int (*module_eeprom)(struct phy_device *dev,
1059 struct ethtool_eeprom *ee, u8 *data);
1060
4069a572 1061 /** @cable_test_start: Start a cable test */
a68a8138 1062 int (*cable_test_start)(struct phy_device *dev);
1a644de2 1063
4069a572 1064 /** @cable_test_tdr_start: Start a raw TDR cable test */
f2bc8ad3
AL
1065 int (*cable_test_tdr_start)(struct phy_device *dev,
1066 const struct phy_tdr_config *config);
1a644de2 1067
4069a572
AL
1068 /**
1069 * @cable_test_get_status: Once per second, or on interrupt,
1070 * request the status of the test.
a68a8138
AL
1071 */
1072 int (*cable_test_get_status)(struct phy_device *dev, bool *finished);
1073
4069a572 1074 /* Get statistics from the PHY using ethtool */
b7a2c1fe
JK
1075 /**
1076 * @get_phy_stats: Retrieve PHY statistics.
1077 * @dev: The PHY device for which the statistics are retrieved.
1078 * @eth_stats: structure where Ethernet PHY stats will be stored.
1079 * @stats: structure where additional PHY-specific stats will be stored.
1080 *
1081 * Retrieves the supported PHY statistics and populates the provided
1082 * structures. The input structures are pre-initialized with
1083 * `ETHTOOL_STAT_NOT_SET`, and the driver must only modify members
1084 * corresponding to supported statistics. Unmodified members will remain
1085 * set to `ETHTOOL_STAT_NOT_SET` and will not be returned to userspace.
1086 */
1087 void (*get_phy_stats)(struct phy_device *dev,
1088 struct ethtool_eth_phy_stats *eth_stats,
1089 struct ethtool_phy_stats *stats);
1090
1091 /**
1092 * @get_link_stats: Retrieve link statistics.
1093 * @dev: The PHY device for which the statistics are retrieved.
1094 * @link_stats: structure where link-specific stats will be stored.
1095 *
1096 * Retrieves link-related statistics for the given PHY device. The input
1097 * structure is pre-initialized with `ETHTOOL_STAT_NOT_SET`, and the
1098 * driver must only modify members corresponding to supported
1099 * statistics. Unmodified members will remain set to
1100 * `ETHTOOL_STAT_NOT_SET` and will not be returned to userspace.
1101 */
1102 void (*get_link_stats)(struct phy_device *dev,
1103 struct ethtool_link_ext_stats *link_stats);
f2bc1c26
OR
1104
1105 /**
1106 * @update_stats: Trigger periodic statistics updates.
1107 * @dev: The PHY device for which statistics updates are triggered.
1108 *
1109 * Periodically gathers statistics from the PHY device to update locally
1110 * maintained 64-bit counters. This is necessary for PHYs that implement
1111 * reduced-width counters (e.g., 16-bit or 32-bit) which can overflow
1112 * more frequently compared to 64-bit counters. By invoking this
1113 * callback, drivers can fetch the current counter values, handle
1114 * overflow detection, and accumulate the results into local 64-bit
1115 * counters for accurate reporting through the `get_phy_stats` and
1116 * `get_link_stats` interfaces.
1117 *
1118 * Return: 0 on success or a negative error code on failure.
1119 */
1120 int (*update_stats)(struct phy_device *dev);
1121
4069a572 1122 /** @get_sset_count: Number of statistic counters */
f3a40945 1123 int (*get_sset_count)(struct phy_device *dev);
4069a572 1124 /** @get_strings: Names of the statistic counters */
f3a40945 1125 void (*get_strings)(struct phy_device *dev, u8 *data);
4069a572 1126 /** @get_stats: Return the statistic counter values */
f3a40945
AL
1127 void (*get_stats)(struct phy_device *dev,
1128 struct ethtool_stats *stats, u64 *data);
968ad9da
RL
1129
1130 /* Get and Set PHY tunables */
4069a572 1131 /** @get_tunable: Return the value of a tunable */
968ad9da
RL
1132 int (*get_tunable)(struct phy_device *dev,
1133 struct ethtool_tunable *tuna, void *data);
4069a572 1134 /** @set_tunable: Set the value of a tunable */
968ad9da
RL
1135 int (*set_tunable)(struct phy_device *dev,
1136 struct ethtool_tunable *tuna,
1137 const void *data);
45456e38
GE
1138 /**
1139 * @set_loopback: Set the loopback mode of the PHY
1140 * enable selects if the loopback mode is enabled or disabled. If the
1141 * loopback mode is enabled, then the speed of the loopback mode can be
1142 * requested with the speed argument. If the speed argument is zero,
1143 * then any speed can be selected. If the speed argument is > 0, then
1144 * this speed shall be selected for the loopback mode or EOPNOTSUPP
1145 * shall be returned if speed selection is not supported.
1146 */
1147 int (*set_loopback)(struct phy_device *dev, bool enable, int speed);
4069a572 1148 /** @get_sqi: Get the signal quality indication */
80660219 1149 int (*get_sqi)(struct phy_device *dev);
4069a572 1150 /** @get_sqi_max: Get the maximum signal quality indication */
80660219 1151 int (*get_sqi_max)(struct phy_device *dev);
16178c8e
PB
1152
1153 /* PLCA RS interface */
1154 /** @get_plca_cfg: Return the current PLCA configuration */
1155 int (*get_plca_cfg)(struct phy_device *dev,
1156 struct phy_plca_cfg *plca_cfg);
1157 /** @set_plca_cfg: Set the PLCA configuration */
1158 int (*set_plca_cfg)(struct phy_device *dev,
1159 const struct phy_plca_cfg *plca_cfg);
1160 /** @get_plca_status: Return the current PLCA status info */
1161 int (*get_plca_status)(struct phy_device *dev,
1162 struct phy_plca_status *plca_st);
68481818
AL
1163
1164 /**
1165 * @led_brightness_set: Set a PHY LED brightness. Index
1166 * indicates which of the PHYs led should be set. Value
1167 * follows the standard LED class meaning, e.g. LED_OFF,
1168 * LED_HALF, LED_FULL.
1169 */
1170 int (*led_brightness_set)(struct phy_device *dev,
1171 u8 index, enum led_brightness value);
4e901018
AL
1172
1173 /**
d3dcb084 1174 * @led_blink_set: Set a PHY LED blinking. Index indicates
4e901018
AL
1175 * which of the PHYs led should be configured to blink. Delays
1176 * are in milliseconds and if both are zero then a sensible
1177 * default should be chosen. The call should adjust the
1178 * timings in that case and if it can't match the values
1179 * specified exactly.
1180 */
1181 int (*led_blink_set)(struct phy_device *dev, u8 index,
1182 unsigned long *delay_on,
1183 unsigned long *delay_off);
1dcc03c9
AL
1184 /**
1185 * @led_hw_is_supported: Can the HW support the given rules.
1186 * @dev: PHY device which has the LED
1187 * @index: Which LED of the PHY device
1188 * @rules The core is interested in these rules
1189 *
1190 * Return 0 if yes, -EOPNOTSUPP if not, or an error code.
1191 */
1192 int (*led_hw_is_supported)(struct phy_device *dev, u8 index,
1193 unsigned long rules);
1194 /**
1195 * @led_hw_control_set: Set the HW to control the LED
1196 * @dev: PHY device which has the LED
1197 * @index: Which LED of the PHY device
1198 * @rules The rules used to control the LED
1199 *
1200 * Returns 0, or a an error code.
1201 */
1202 int (*led_hw_control_set)(struct phy_device *dev, u8 index,
1203 unsigned long rules);
1204 /**
1205 * @led_hw_control_get: Get how the HW is controlling the LED
1206 * @dev: PHY device which has the LED
1207 * @index: Which LED of the PHY device
1208 * @rules Pointer to the rules used to control the LED
1209 *
1210 * Set *@rules to how the HW is currently blinking. Returns 0
1211 * on success, or a error code if the current blinking cannot
1212 * be represented in rules, or some other error happens.
1213 */
1214 int (*led_hw_control_get)(struct phy_device *dev, u8 index,
1215 unsigned long *rules);
1216
7ae215ee
CM
1217 /**
1218 * @led_polarity_set: Set the LED polarity modes
1219 * @dev: PHY device which has the LED
1220 * @index: Which LED of the PHY device
1221 * @modes: bitmap of LED polarity modes
1222 *
1223 * Configure LED with all the required polarity modes in @modes
1224 * to make it correctly turn ON or OFF.
1225 *
1226 * Returns 0, or an error code.
1227 */
1228 int (*led_polarity_set)(struct phy_device *dev, int index,
1229 unsigned long modes);
8bf47e4d
OR
1230
1231 /**
1232 * @get_next_update_time: Get the time until the next update event
1233 * @dev: PHY device
1234 *
1235 * Callback to determine the time (in jiffies) until the next
1236 * update event for the PHY state machine. Allows PHY drivers to
1237 * dynamically adjust polling intervals based on link state or other
1238 * conditions.
1239 *
1240 * Returns the time in jiffies until the next update event.
1241 */
1242 unsigned int (*get_next_update_time)(struct phy_device *dev);
00db8189 1243};
d69d8048 1244#define to_phy_driver(d) container_of_const(to_mdio_common_driver(d), \
a9049e0c 1245 struct phy_driver, mdiodrv)
00db8189 1246
aa2af2eb
HK
1247#define PHY_ID_MATCH_EXACT(id) .phy_id = (id), .phy_id_mask = GENMASK(31, 0)
1248#define PHY_ID_MATCH_MODEL(id) .phy_id = (id), .phy_id_mask = GENMASK(31, 4)
1249#define PHY_ID_MATCH_VENDOR(id) .phy_id = (id), .phy_id_mask = GENMASK(31, 10)
1250
4b159f50
RK
1251/**
1252 * phy_id_compare - compare @id1 with @id2 taking account of @mask
1253 * @id1: first PHY ID
1254 * @id2: second PHY ID
1255 * @mask: the PHY ID mask, set bits are significant in matching
1256 *
1257 * Return true if the bits from @id1 and @id2 specified by @mask match.
1258 * This uses an equivalent test to (@id & @mask) == (@phy_id & @mask).
1259 */
1260static inline bool phy_id_compare(u32 id1, u32 id2, u32 mask)
1261{
1262 return !((id1 ^ id2) & mask);
1263}
1264
1265/**
1266 * phydev_id_compare - compare @id with the PHY's Clause 22 ID
1267 * @phydev: the PHY device
1268 * @id: the PHY ID to be matched
1269 *
1270 * Compare the @phydev clause 22 ID with the provided @id and return true or
1271 * false depending whether it matches, using the bound driver mask. The
1272 * @phydev must be bound to a driver.
1273 */
1274static inline bool phydev_id_compare(struct phy_device *phydev, u32 id)
1275{
1276 return phy_id_compare(id, phydev->phy_id, phydev->drv->phy_id_mask);
1277}
1278
da4625ac
RK
1279const char *phy_speed_to_str(int speed);
1280const char *phy_duplex_to_str(unsigned int duplex);
0c3e10cb 1281const char *phy_rate_matching_to_str(int rate_matching);
da4625ac 1282
c04ade27
MC
1283int phy_interface_num_ports(phy_interface_t interface);
1284
ed623fb8 1285/**
8a6a77bb 1286 * phy_is_started - Convenience function to check whether PHY is started
ed623fb8 1287 * @phydev: The phy_device struct
ed623fb8 1288 */
8a6a77bb 1289static inline bool phy_is_started(struct phy_device *phydev)
ed623fb8 1290{
8a6a77bb 1291 return phydev->state >= PHY_UP;
ed623fb8
HK
1292}
1293
2b3e88ea 1294/**
8a6a77bb 1295 * phy_disable_eee_mode - Don't advertise an EEE mode.
2b3e88ea 1296 * @phydev: The phy_device struct
8a6a77bb 1297 * @link_mode: The EEE mode to be disabled
2b3e88ea 1298 */
8a6a77bb 1299static inline void phy_disable_eee_mode(struct phy_device *phydev, u32 link_mode)
2b3e88ea 1300{
a9b6a860
HK
1301 WARN_ON(phy_is_started(phydev));
1302
8a6a77bb 1303 linkmode_set_bit(link_mode, phydev->eee_disabled_modes);
a9b6a860 1304 linkmode_clear_bit(link_mode, phydev->advertising_eee);
2b3e88ea
HK
1305}
1306
2d880b87 1307void phy_resolve_aneg_pause(struct phy_device *phydev);
8c5e850c
RK
1308void phy_resolve_aneg_linkmode(struct phy_device *phydev);
1309
2e888103
LB
1310/**
1311 * phy_read - Convenience function for reading a given PHY register
1312 * @phydev: the phy_device struct
1313 * @regnum: register number to read
1314 *
1315 * NOTE: MUST NOT be called from interrupt context,
1316 * because the bus read/write functions may wait for an interrupt
1317 * to conclude the operation.
1318 */
abf35df2 1319static inline int phy_read(struct phy_device *phydev, u32 regnum)
2e888103 1320{
e5a03bfd 1321 return mdiobus_read(phydev->mdio.bus, phydev->mdio.addr, regnum);
2e888103
LB
1322}
1323
fcbd30d0
DZ
1324#define phy_read_poll_timeout(phydev, regnum, val, cond, sleep_us, \
1325 timeout_us, sleep_before_read) \
1326({ \
4ec73295
RKO
1327 int __ret, __val; \
1328 __ret = read_poll_timeout(__val = phy_read, val, \
1329 __val < 0 || (cond), \
fcbd30d0 1330 sleep_us, timeout_us, sleep_before_read, phydev, regnum); \
4ec73295
RKO
1331 if (__val < 0) \
1332 __ret = __val; \
fcbd30d0
DZ
1333 if (__ret) \
1334 phydev_err(phydev, "%s failed: %d\n", __func__, __ret); \
1335 __ret; \
1336})
1337
788f9933
RK
1338/**
1339 * __phy_read - convenience function for reading a given PHY register
1340 * @phydev: the phy_device struct
1341 * @regnum: register number to read
1342 *
1343 * The caller must have taken the MDIO bus lock.
1344 */
1345static inline int __phy_read(struct phy_device *phydev, u32 regnum)
1346{
1347 return __mdiobus_read(phydev->mdio.bus, phydev->mdio.addr, regnum);
1348}
1349
2e888103
LB
1350/**
1351 * phy_write - Convenience function for writing a given PHY register
1352 * @phydev: the phy_device struct
1353 * @regnum: register number to write
1354 * @val: value to write to @regnum
1355 *
1356 * NOTE: MUST NOT be called from interrupt context,
1357 * because the bus read/write functions may wait for an interrupt
1358 * to conclude the operation.
1359 */
abf35df2 1360static inline int phy_write(struct phy_device *phydev, u32 regnum, u16 val)
2e888103 1361{
e5a03bfd 1362 return mdiobus_write(phydev->mdio.bus, phydev->mdio.addr, regnum, val);
2e888103
LB
1363}
1364
788f9933
RK
1365/**
1366 * __phy_write - Convenience function for writing a given PHY register
1367 * @phydev: the phy_device struct
1368 * @regnum: register number to write
1369 * @val: value to write to @regnum
1370 *
1371 * The caller must have taken the MDIO bus lock.
1372 */
1373static inline int __phy_write(struct phy_device *phydev, u32 regnum, u16 val)
1374{
1375 return __mdiobus_write(phydev->mdio.bus, phydev->mdio.addr, regnum,
1376 val);
1377}
1378
6cc7cf81
RK
1379/**
1380 * __phy_modify_changed() - Convenience function for modifying a PHY register
1381 * @phydev: a pointer to a &struct phy_device
1382 * @regnum: register number
1383 * @mask: bit mask of bits to clear
1384 * @set: bit mask of bits to set
1385 *
1386 * Unlocked helper function which allows a PHY register to be modified as
1387 * new register value = (old register value & ~mask) | set
1388 *
1389 * Returns negative errno, 0 if there was no change, and 1 in case of change
1390 */
1391static inline int __phy_modify_changed(struct phy_device *phydev, u32 regnum,
1392 u16 mask, u16 set)
1393{
1394 return __mdiobus_modify_changed(phydev->mdio.bus, phydev->mdio.addr,
1395 regnum, mask, set);
1396}
1397
e86c6569 1398/*
1878f0dc
NY
1399 * phy_read_mmd - Convenience function for reading a register
1400 * from an MMD on a given PHY.
1878f0dc
NY
1401 */
1402int phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum);
1403
4069a572
AL
1404/**
1405 * phy_read_mmd_poll_timeout - Periodically poll a PHY register until a
1406 * condition is met or a timeout occurs
1407 *
1408 * @phydev: The phy_device struct
1409 * @devaddr: The MMD to read from
1410 * @regnum: The register on the MMD to read
1411 * @val: Variable to read the register into
1412 * @cond: Break condition (usually involving @val)
89124747
AMB
1413 * @sleep_us: Maximum time to sleep between reads in us (0 tight-loops). Please
1414 * read usleep_range() function description for details and
1415 * limitations.
4069a572
AL
1416 * @timeout_us: Timeout in us, 0 means never timeout
1417 * @sleep_before_read: if it is true, sleep @sleep_us before read.
89124747
AMB
1418 *
1419 * Returns: 0 on success and -ETIMEDOUT upon a timeout. In either
4069a572
AL
1420 * case, the last read value at @args is stored in @val. Must not
1421 * be called from atomic context if sleep_us or timeout_us are used.
1422 */
bd971ff0
DZ
1423#define phy_read_mmd_poll_timeout(phydev, devaddr, regnum, val, cond, \
1424 sleep_us, timeout_us, sleep_before_read) \
1425({ \
4ec73295
RKO
1426 int __ret, __val; \
1427 __ret = read_poll_timeout(__val = phy_read_mmd, val, \
1428 __val < 0 || (cond), \
bd971ff0
DZ
1429 sleep_us, timeout_us, sleep_before_read, \
1430 phydev, devaddr, regnum); \
4ec73295
RKO
1431 if (__val < 0) \
1432 __ret = __val; \
bd971ff0
DZ
1433 if (__ret) \
1434 phydev_err(phydev, "%s failed: %d\n", __func__, __ret); \
1435 __ret; \
1436})
1437
e86c6569 1438/*
1878f0dc
NY
1439 * __phy_read_mmd - Convenience function for reading a register
1440 * from an MMD on a given PHY.
1878f0dc
NY
1441 */
1442int __phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum);
1443
e86c6569 1444/*
1878f0dc
NY
1445 * phy_write_mmd - Convenience function for writing a register
1446 * on an MMD on a given PHY.
1878f0dc
NY
1447 */
1448int phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val);
1449
e86c6569 1450/*
1878f0dc
NY
1451 * __phy_write_mmd - Convenience function for writing a register
1452 * on an MMD on a given PHY.
1878f0dc
NY
1453 */
1454int __phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val);
1455
b8554d4f
HK
1456int __phy_modify_changed(struct phy_device *phydev, u32 regnum, u16 mask,
1457 u16 set);
1458int phy_modify_changed(struct phy_device *phydev, u32 regnum, u16 mask,
1459 u16 set);
788f9933 1460int __phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set);
2b74e5be 1461int phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set);
788f9933 1462
b8554d4f
HK
1463int __phy_modify_mmd_changed(struct phy_device *phydev, int devad, u32 regnum,
1464 u16 mask, u16 set);
1465int phy_modify_mmd_changed(struct phy_device *phydev, int devad, u32 regnum,
1466 u16 mask, u16 set);
1878f0dc 1467int __phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum,
b8554d4f 1468 u16 mask, u16 set);
1878f0dc 1469int phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum,
b8554d4f 1470 u16 mask, u16 set);
1878f0dc 1471
ac8322d8
HK
1472/**
1473 * __phy_set_bits - Convenience function for setting bits in a PHY register
1474 * @phydev: the phy_device struct
1475 * @regnum: register number to write
1476 * @val: bits to set
1477 *
1478 * The caller must have taken the MDIO bus lock.
1479 */
1480static inline int __phy_set_bits(struct phy_device *phydev, u32 regnum, u16 val)
1481{
1482 return __phy_modify(phydev, regnum, 0, val);
1483}
1484
1485/**
1486 * __phy_clear_bits - Convenience function for clearing bits in a PHY register
1487 * @phydev: the phy_device struct
1488 * @regnum: register number to write
1489 * @val: bits to clear
1490 *
1491 * The caller must have taken the MDIO bus lock.
1492 */
1493static inline int __phy_clear_bits(struct phy_device *phydev, u32 regnum,
1494 u16 val)
1495{
1496 return __phy_modify(phydev, regnum, val, 0);
1497}
1498
1499/**
1500 * phy_set_bits - Convenience function for setting bits in a PHY register
1501 * @phydev: the phy_device struct
1502 * @regnum: register number to write
1503 * @val: bits to set
1504 */
1505static inline int phy_set_bits(struct phy_device *phydev, u32 regnum, u16 val)
1506{
1507 return phy_modify(phydev, regnum, 0, val);
1508}
1509
1510/**
1511 * phy_clear_bits - Convenience function for clearing bits in a PHY register
1512 * @phydev: the phy_device struct
1513 * @regnum: register number to write
1514 * @val: bits to clear
1515 */
1516static inline int phy_clear_bits(struct phy_device *phydev, u32 regnum, u16 val)
1517{
1518 return phy_modify(phydev, regnum, val, 0);
1519}
1520
1878f0dc
NY
1521/**
1522 * __phy_set_bits_mmd - Convenience function for setting bits in a register
1523 * on MMD
1524 * @phydev: the phy_device struct
1525 * @devad: the MMD containing register to modify
1526 * @regnum: register number to modify
1527 * @val: bits to set
1528 *
1529 * The caller must have taken the MDIO bus lock.
1530 */
1531static inline int __phy_set_bits_mmd(struct phy_device *phydev, int devad,
1532 u32 regnum, u16 val)
1533{
1534 return __phy_modify_mmd(phydev, devad, regnum, 0, val);
1535}
1536
1537/**
1538 * __phy_clear_bits_mmd - Convenience function for clearing bits in a register
1539 * on MMD
1540 * @phydev: the phy_device struct
1541 * @devad: the MMD containing register to modify
1542 * @regnum: register number to modify
1543 * @val: bits to clear
1544 *
1545 * The caller must have taken the MDIO bus lock.
1546 */
1547static inline int __phy_clear_bits_mmd(struct phy_device *phydev, int devad,
1548 u32 regnum, u16 val)
1549{
1550 return __phy_modify_mmd(phydev, devad, regnum, val, 0);
1551}
1552
1553/**
1554 * phy_set_bits_mmd - Convenience function for setting bits in a register
1555 * on MMD
1556 * @phydev: the phy_device struct
1557 * @devad: the MMD containing register to modify
1558 * @regnum: register number to modify
1559 * @val: bits to set
1560 */
1561static inline int phy_set_bits_mmd(struct phy_device *phydev, int devad,
1562 u32 regnum, u16 val)
1563{
1564 return phy_modify_mmd(phydev, devad, regnum, 0, val);
1565}
1566
1567/**
1568 * phy_clear_bits_mmd - Convenience function for clearing bits in a register
1569 * on MMD
1570 * @phydev: the phy_device struct
1571 * @devad: the MMD containing register to modify
1572 * @regnum: register number to modify
1573 * @val: bits to clear
1574 */
1575static inline int phy_clear_bits_mmd(struct phy_device *phydev, int devad,
1576 u32 regnum, u16 val)
1577{
1578 return phy_modify_mmd(phydev, devad, regnum, val, 0);
1579}
1580
2c7b4921
FF
1581/**
1582 * phy_interrupt_is_valid - Convenience function for testing a given PHY irq
1583 * @phydev: the phy_device struct
1584 *
1585 * NOTE: must be kept in sync with addition/removal of PHY_POLL and
93e8990c 1586 * PHY_MAC_INTERRUPT
2c7b4921
FF
1587 */
1588static inline bool phy_interrupt_is_valid(struct phy_device *phydev)
1589{
93e8990c 1590 return phydev->irq != PHY_POLL && phydev->irq != PHY_MAC_INTERRUPT;
2c7b4921
FF
1591}
1592
3c507b8a
HK
1593/**
1594 * phy_polling_mode - Convenience function for testing whether polling is
1595 * used to detect PHY status changes
1596 * @phydev: the phy_device struct
1597 */
1598static inline bool phy_polling_mode(struct phy_device *phydev)
1599{
97c22438
AL
1600 if (phydev->state == PHY_CABLETEST)
1601 if (phydev->drv->flags & PHY_POLL_CABLE_TEST)
1602 return true;
1603
f2bc1c26
OR
1604 if (phydev->drv->update_stats)
1605 return true;
1606
3c507b8a
HK
1607 return phydev->irq == PHY_POLL;
1608}
1609
0e5dafc8
RC
1610/**
1611 * phy_has_hwtstamp - Tests whether a PHY time stamp configuration.
1612 * @phydev: the phy_device struct
1613 */
1614static inline bool phy_has_hwtstamp(struct phy_device *phydev)
1615{
4715f65f 1616 return phydev && phydev->mii_ts && phydev->mii_ts->hwtstamp;
0e5dafc8
RC
1617}
1618
1619/**
1620 * phy_has_rxtstamp - Tests whether a PHY supports receive time stamping.
1621 * @phydev: the phy_device struct
1622 */
1623static inline bool phy_has_rxtstamp(struct phy_device *phydev)
1624{
4715f65f 1625 return phydev && phydev->mii_ts && phydev->mii_ts->rxtstamp;
0e5dafc8
RC
1626}
1627
1628/**
1629 * phy_has_tsinfo - Tests whether a PHY reports time stamping and/or
1630 * PTP hardware clock capabilities.
1631 * @phydev: the phy_device struct
1632 */
1633static inline bool phy_has_tsinfo(struct phy_device *phydev)
1634{
4715f65f 1635 return phydev && phydev->mii_ts && phydev->mii_ts->ts_info;
0e5dafc8
RC
1636}
1637
1638/**
1639 * phy_has_txtstamp - Tests whether a PHY supports transmit time stamping.
1640 * @phydev: the phy_device struct
1641 */
1642static inline bool phy_has_txtstamp(struct phy_device *phydev)
1643{
4715f65f 1644 return phydev && phydev->mii_ts && phydev->mii_ts->txtstamp;
0e5dafc8
RC
1645}
1646
446e2305
KM
1647static inline int phy_hwtstamp(struct phy_device *phydev,
1648 struct kernel_hwtstamp_config *cfg,
1649 struct netlink_ext_ack *extack)
0e5dafc8 1650{
446e2305 1651 return phydev->mii_ts->hwtstamp(phydev->mii_ts, cfg, extack);
0e5dafc8
RC
1652}
1653
1654static inline bool phy_rxtstamp(struct phy_device *phydev, struct sk_buff *skb,
1655 int type)
1656{
4715f65f 1657 return phydev->mii_ts->rxtstamp(phydev->mii_ts, skb, type);
0e5dafc8
RC
1658}
1659
1660static inline int phy_ts_info(struct phy_device *phydev,
2111375b 1661 struct kernel_ethtool_ts_info *tsinfo)
0e5dafc8 1662{
4715f65f 1663 return phydev->mii_ts->ts_info(phydev->mii_ts, tsinfo);
0e5dafc8
RC
1664}
1665
1666static inline void phy_txtstamp(struct phy_device *phydev, struct sk_buff *skb,
1667 int type)
1668{
4715f65f 1669 phydev->mii_ts->txtstamp(phydev->mii_ts, skb, type);
0e5dafc8
RC
1670}
1671
2dd35600
KM
1672/**
1673 * phy_is_default_hwtstamp - Is the PHY hwtstamp the default timestamp
1674 * @phydev: Pointer to phy_device
1675 *
1676 * This is used to get default timestamping device taking into account
1677 * the new API choice, which is selecting the timestamping from MAC by
1678 * default if the phydev does not have default_timestamp flag enabled.
1679 *
1680 * Return: True if phy is the default hw timestamp, false otherwise.
1681 */
1682static inline bool phy_is_default_hwtstamp(struct phy_device *phydev)
1683{
1684 return phy_has_hwtstamp(phydev) && phydev->default_timestamp;
1685}
1686
b834489b
RH
1687/**
1688 * phy_on_sfp - Convenience function for testing if a PHY is on an SFP module
1689 * @phydev: the phy_device struct
1690 */
1691static inline bool phy_on_sfp(struct phy_device *phydev)
1692{
1693 return phydev->is_on_sfp_module;
1694}
1695
32d0f783
IS
1696/**
1697 * phy_interface_mode_is_rgmii - Convenience function for testing if a
1698 * PHY interface mode is RGMII (all variants)
4069a572 1699 * @mode: the &phy_interface_t enum
32d0f783
IS
1700 */
1701static inline bool phy_interface_mode_is_rgmii(phy_interface_t mode)
1702{
1703 return mode >= PHY_INTERFACE_MODE_RGMII &&
1704 mode <= PHY_INTERFACE_MODE_RGMII_TXID;
1705};
1706
365c1e64 1707/**
4069a572 1708 * phy_interface_mode_is_8023z() - does the PHY interface mode use 802.3z
365c1e64
RK
1709 * negotiation
1710 * @mode: one of &enum phy_interface_t
1711 *
4069a572 1712 * Returns true if the PHY interface mode uses the 16-bit negotiation
365c1e64
RK
1713 * word as defined in 802.3z. (See 802.3-2015 37.2.1 Config_Reg encoding)
1714 */
1715static inline bool phy_interface_mode_is_8023z(phy_interface_t mode)
1716{
1717 return mode == PHY_INTERFACE_MODE_1000BASEX ||
1718 mode == PHY_INTERFACE_MODE_2500BASEX;
1719}
1720
e463d88c
FF
1721/**
1722 * phy_interface_is_rgmii - Convenience function for testing if a PHY interface
1723 * is RGMII (all variants)
1724 * @phydev: the phy_device struct
1725 */
1726static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
1727{
32d0f783 1728 return phy_interface_mode_is_rgmii(phydev->interface);
5a11dd7d
FF
1729};
1730
4069a572 1731/**
5a11dd7d
FF
1732 * phy_is_pseudo_fixed_link - Convenience function for testing if this
1733 * PHY is the CPU port facing side of an Ethernet switch, or similar.
1734 * @phydev: the phy_device struct
1735 */
1736static inline bool phy_is_pseudo_fixed_link(struct phy_device *phydev)
1737{
1738 return phydev->is_pseudo_fixed_link;
e463d88c
FF
1739}
1740
78ffc4ac
RK
1741int phy_save_page(struct phy_device *phydev);
1742int phy_select_page(struct phy_device *phydev, int page);
1743int phy_restore_page(struct phy_device *phydev, int oldpage, int ret);
1744int phy_read_paged(struct phy_device *phydev, int page, u32 regnum);
1745int phy_write_paged(struct phy_device *phydev, int page, u32 regnum, u16 val);
bf22b343
HK
1746int phy_modify_paged_changed(struct phy_device *phydev, int page, u32 regnum,
1747 u16 mask, u16 set);
78ffc4ac
RK
1748int phy_modify_paged(struct phy_device *phydev, int page, u32 regnum,
1749 u16 mask, u16 set);
1750
7d49a32a 1751struct phy_device *phy_device_create(struct mii_bus *bus, int addr, u32 phy_id,
4017b4d3
SS
1752 bool is_c45,
1753 struct phy_c45_device_ids *c45_ids);
114dea60 1754int fwnode_get_phy_id(struct fwnode_handle *fwnode, u32 *phy_id);
0fb16976 1755struct mdio_device *fwnode_mdio_find_device(struct fwnode_handle *fwnode);
425775ed 1756struct phy_device *fwnode_phy_find_device(struct fwnode_handle *phy_fwnode);
4a0faa02 1757struct fwnode_handle *fwnode_get_phy_node(const struct fwnode_handle *fwnode);
ac28b9f8 1758struct phy_device *get_phy_device(struct mii_bus *bus, int addr, bool is_c45);
4dea547f 1759int phy_device_register(struct phy_device *phy);
90eff909 1760void phy_device_free(struct phy_device *phydev);
38737e49 1761void phy_device_remove(struct phy_device *phydev);
8b72b301 1762int phy_get_c45_ids(struct phy_device *phydev);
2f5cb434 1763int phy_init_hw(struct phy_device *phydev);
481b5d93
SH
1764int phy_suspend(struct phy_device *phydev);
1765int phy_resume(struct phy_device *phydev);
9c2c2e62 1766int __phy_resume(struct phy_device *phydev);
0d60fd50 1767int phy_loopback(struct phy_device *phydev, bool enable, int speed);
b2db6f4a
MC
1768int phy_sfp_connect_phy(void *upstream, struct phy_device *phy);
1769void phy_sfp_disconnect_phy(void *upstream, struct phy_device *phy);
298e54fa
RK
1770void phy_sfp_attach(void *upstream, struct sfp_bus *bus);
1771void phy_sfp_detach(void *upstream, struct sfp_bus *bus);
1772int phy_sfp_probe(struct phy_device *phydev,
1773 const struct sfp_upstream_ops *ops);
4017b4d3
SS
1774struct phy_device *phy_attach(struct net_device *dev, const char *bus_id,
1775 phy_interface_t interface);
f8f76db1 1776struct phy_device *phy_find_first(struct mii_bus *bus);
257184d7
AF
1777int phy_attach_direct(struct net_device *dev, struct phy_device *phydev,
1778 u32 flags, phy_interface_t interface);
fa94f6d9 1779int phy_connect_direct(struct net_device *dev, struct phy_device *phydev,
4017b4d3
SS
1780 void (*handler)(struct net_device *),
1781 phy_interface_t interface);
1782struct phy_device *phy_connect(struct net_device *dev, const char *bus_id,
1783 void (*handler)(struct net_device *),
1784 phy_interface_t interface);
e1393456
AF
1785void phy_disconnect(struct phy_device *phydev);
1786void phy_detach(struct phy_device *phydev);
1787void phy_start(struct phy_device *phydev);
1788void phy_stop(struct phy_device *phydev);
014068dc 1789int phy_config_aneg(struct phy_device *phydev);
6a23c555 1790int _phy_start_aneg(struct phy_device *phydev);
e1393456 1791int phy_start_aneg(struct phy_device *phydev);
372788f9 1792int phy_aneg_done(struct phy_device *phydev);
b4c7698d
RKO
1793unsigned int phy_inband_caps(struct phy_device *phydev,
1794 phy_interface_t interface);
5d58a890 1795int phy_config_inband(struct phy_device *phydev, unsigned int modes);
2b9672dd
HK
1796int phy_speed_down(struct phy_device *phydev, bool sync);
1797int phy_speed_up(struct phy_device *phydev);
cf9f6079 1798bool phy_check_valid(int speed, int duplex, unsigned long *features);
e1393456 1799
002ba705 1800int phy_restart_aneg(struct phy_device *phydev);
a9668491 1801int phy_reset_after_clk_enable(struct phy_device *phydev);
00db8189 1802
a68a8138
AL
1803#if IS_ENABLED(CONFIG_PHYLIB)
1804int phy_start_cable_test(struct phy_device *phydev,
1805 struct netlink_ext_ack *extack);
1a644de2 1806int phy_start_cable_test_tdr(struct phy_device *phydev,
f2bc8ad3
AL
1807 struct netlink_ext_ack *extack,
1808 const struct phy_tdr_config *config);
a68a8138
AL
1809#else
1810static inline
1811int phy_start_cable_test(struct phy_device *phydev,
1812 struct netlink_ext_ack *extack)
1813{
1814 NL_SET_ERR_MSG(extack, "Kernel not compiled with PHYLIB support");
1815 return -EOPNOTSUPP;
1816}
1a644de2
AL
1817static inline
1818int phy_start_cable_test_tdr(struct phy_device *phydev,
f2bc8ad3
AL
1819 struct netlink_ext_ack *extack,
1820 const struct phy_tdr_config *config)
1a644de2
AL
1821{
1822 NL_SET_ERR_MSG(extack, "Kernel not compiled with PHYLIB support");
1823 return -EOPNOTSUPP;
1824}
a68a8138
AL
1825#endif
1826
bafbdd52
SS
1827static inline void phy_device_reset(struct phy_device *phydev, int value)
1828{
1829 mdio_device_reset(&phydev->mdio, value);
1830}
1831
72ba48be 1832#define phydev_err(_phydev, format, args...) \
e5a03bfd 1833 dev_err(&_phydev->mdio.dev, format, ##args)
72ba48be 1834
a7936798
RV
1835#define phydev_err_probe(_phydev, err, format, args...) \
1836 dev_err_probe(&_phydev->mdio.dev, err, format, ##args)
1837
c4fabb8b
AL
1838#define phydev_info(_phydev, format, args...) \
1839 dev_info(&_phydev->mdio.dev, format, ##args)
1840
ab2a605f
AL
1841#define phydev_warn(_phydev, format, args...) \
1842 dev_warn(&_phydev->mdio.dev, format, ##args)
1843
72ba48be 1844#define phydev_dbg(_phydev, format, args...) \
2eaa38d9 1845 dev_dbg(&_phydev->mdio.dev, format, ##args)
72ba48be 1846
84eff6d1
AL
1847static inline const char *phydev_name(const struct phy_device *phydev)
1848{
e5a03bfd 1849 return dev_name(&phydev->mdio.dev);
84eff6d1
AL
1850}
1851
bec170e5
HK
1852static inline void phy_lock_mdio_bus(struct phy_device *phydev)
1853{
1854 mutex_lock(&phydev->mdio.bus->mdio_lock);
1855}
1856
1857static inline void phy_unlock_mdio_bus(struct phy_device *phydev)
1858{
1859 mutex_unlock(&phydev->mdio.bus->mdio_lock);
1860}
1861
2220943a
AL
1862void phy_attached_print(struct phy_device *phydev, const char *fmt, ...)
1863 __printf(2, 3);
e27f1787
FF
1864char *phy_attached_info_irq(struct phy_device *phydev)
1865 __malloc;
2220943a 1866void phy_attached_info(struct phy_device *phydev);
5acde34a 1867
d6c45707
CM
1868int genphy_match_phy_device(struct phy_device *phydev,
1869 const struct phy_driver *phydrv);
1870
5acde34a 1871/* Clause 22 PHY */
045925e3 1872int genphy_read_abilities(struct phy_device *phydev);
3fb69bca 1873int genphy_setup_forced(struct phy_device *phydev);
00db8189 1874int genphy_restart_aneg(struct phy_device *phydev);
2a10ab04 1875int genphy_check_and_restart_aneg(struct phy_device *phydev, bool restart);
f4069cd7 1876int __genphy_config_aneg(struct phy_device *phydev, bool changed);
a9fa6e6a 1877int genphy_aneg_done(struct phy_device *phydev);
00db8189 1878int genphy_update_link(struct phy_device *phydev);
8d3dc3ac 1879int genphy_read_lpa(struct phy_device *phydev);
0efc286a 1880int genphy_read_status_fixed(struct phy_device *phydev);
00db8189 1881int genphy_read_status(struct phy_device *phydev);
64807c23 1882int genphy_read_master_slave(struct phy_device *phydev);
0f0ca340
GC
1883int genphy_suspend(struct phy_device *phydev);
1884int genphy_resume(struct phy_device *phydev);
45456e38 1885int genphy_loopback(struct phy_device *phydev, bool enable, int speed);
797ac071 1886int genphy_soft_reset(struct phy_device *phydev);
87de1f05 1887irqreturn_t genphy_handle_interrupt_no_ack(struct phy_device *phydev);
f4069cd7
HK
1888
1889static inline int genphy_config_aneg(struct phy_device *phydev)
1890{
1891 return __genphy_config_aneg(phydev, false);
1892}
1893
4c8e0459
LW
1894static inline int genphy_no_config_intr(struct phy_device *phydev)
1895{
1896 return 0;
1897}
5df7af85
KH
1898int genphy_read_mmd_unsupported(struct phy_device *phdev, int devad,
1899 u16 regnum);
1900int genphy_write_mmd_unsupported(struct phy_device *phdev, int devnum,
1901 u16 regnum, u16 val);
5acde34a 1902
fa6e98ce
HK
1903/* Clause 37 */
1904int genphy_c37_config_aneg(struct phy_device *phydev);
9b1d5e05 1905int genphy_c37_read_status(struct phy_device *phydev, bool *changed);
fa6e98ce 1906
5acde34a
RK
1907/* Clause 45 PHY */
1908int genphy_c45_restart_aneg(struct phy_device *phydev);
1af9f168 1909int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart);
5acde34a 1910int genphy_c45_aneg_done(struct phy_device *phydev);
998a8a83 1911int genphy_c45_read_link(struct phy_device *phydev);
5acde34a
RK
1912int genphy_c45_read_lpa(struct phy_device *phydev);
1913int genphy_c45_read_pma(struct phy_device *phydev);
1914int genphy_c45_pma_setup_forced(struct phy_device *phydev);
90532850 1915int genphy_c45_pma_baset1_setup_master_slave(struct phy_device *phydev);
9a5dc8af 1916int genphy_c45_an_config_aneg(struct phy_device *phydev);
5acde34a 1917int genphy_c45_an_disable_aneg(struct phy_device *phydev);
ea4efe25 1918int genphy_c45_read_mdix(struct phy_device *phydev);
ac3f5533 1919int genphy_c45_pma_read_abilities(struct phy_device *phydev);
0c476157 1920int genphy_c45_pma_read_ext_abilities(struct phy_device *phydev);
eba2e4c2 1921int genphy_c45_pma_baset1_read_abilities(struct phy_device *phydev);
14e47d1f 1922int genphy_c45_read_eee_abilities(struct phy_device *phydev);
b9a366f3 1923int genphy_c45_pma_baset1_read_master_slave(struct phy_device *phydev);
70fa3a96 1924int genphy_c45_read_status(struct phy_device *phydev);
2013ad88 1925int genphy_c45_baset1_read_status(struct phy_device *phydev);
94acaeb5 1926int genphy_c45_config_aneg(struct phy_device *phydev);
45456e38 1927int genphy_c45_loopback(struct phy_device *phydev, bool enable, int speed);
da702f34
RPNO
1928int genphy_c45_pma_resume(struct phy_device *phydev);
1929int genphy_c45_pma_suspend(struct phy_device *phydev);
63c67f52 1930int genphy_c45_fast_retrain(struct phy_device *phydev, bool enable);
49332341
PB
1931int genphy_c45_plca_get_cfg(struct phy_device *phydev,
1932 struct phy_plca_cfg *plca_cfg);
1933int genphy_c45_plca_set_cfg(struct phy_device *phydev,
1934 const struct phy_plca_cfg *plca_cfg);
1935int genphy_c45_plca_get_status(struct phy_device *phydev,
1936 struct phy_plca_status *plca_st);
809265fe 1937int genphy_c45_eee_is_active(struct phy_device *phydev, unsigned long *lp);
022c3f87 1938int genphy_c45_ethtool_get_eee(struct phy_device *phydev,
d80a5233 1939 struct ethtool_keee *data);
022c3f87 1940int genphy_c45_ethtool_set_eee(struct phy_device *phydev,
d80a5233 1941 struct ethtool_keee *data);
b6478b8c 1942int genphy_c45_an_config_eee_aneg(struct phy_device *phydev);
5acde34a 1943
3970ed49
AL
1944/* Generic C45 PHY driver */
1945extern struct phy_driver genphy_c45_driver;
1946
e8a714e0
FF
1947/* The gen10g_* functions are the old Clause 45 stub */
1948int gen10g_config_aneg(struct phy_device *phydev);
e8a714e0 1949
00fde795
HK
1950static inline int phy_read_status(struct phy_device *phydev)
1951{
1952 if (!phydev->drv)
1953 return -EIO;
1954
1955 if (phydev->drv->read_status)
1956 return phydev->drv->read_status(phydev);
1957 else
1958 return genphy_read_status(phydev);
1959}
1960
00db8189 1961void phy_driver_unregister(struct phy_driver *drv);
d5bf9071 1962void phy_drivers_unregister(struct phy_driver *drv, int n);
be01da72
AL
1963int phy_driver_register(struct phy_driver *new_driver, struct module *owner);
1964int phy_drivers_register(struct phy_driver *new_driver, int n,
1965 struct module *owner);
293e9a3d 1966void phy_error(struct phy_device *phydev);
4f9c85a1 1967void phy_state_machine(struct work_struct *work);
293e9a3d 1968void phy_trigger_machine(struct phy_device *phydev);
28b2e0d2 1969void phy_mac_interrupt(struct phy_device *phydev);
29935aeb 1970void phy_start_machine(struct phy_device *phydev);
00db8189 1971void phy_stop_machine(struct phy_device *phydev);
5514174f 1972void phy_ethtool_ksettings_get(struct phy_device *phydev,
1973 struct ethtool_link_ksettings *cmd);
2d55173e
PR
1974int phy_ethtool_ksettings_set(struct phy_device *phydev,
1975 const struct ethtool_link_ksettings *cmd);
4017b4d3 1976int phy_mii_ioctl(struct phy_device *phydev, struct ifreq *ifr, int cmd);
bbbf8430 1977int phy_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
3231e5d2 1978int phy_do_ioctl_running(struct net_device *dev, struct ifreq *ifr, int cmd);
3dd4ef1b 1979int phy_disable_interrupts(struct phy_device *phydev);
434a4315 1980void phy_request_interrupt(struct phy_device *phydev);
07b09289 1981void phy_free_interrupt(struct phy_device *phydev);
e1393456 1982void phy_print_status(struct phy_device *phydev);
0c3e10cb
SA
1983int phy_get_rate_matching(struct phy_device *phydev,
1984 phy_interface_t iface);
73c105ad 1985void phy_set_max_speed(struct phy_device *phydev, u32 max_speed);
41124fa6 1986void phy_remove_link_mode(struct phy_device *phydev, u32 link_mode);
22c0ef6b 1987void phy_advertise_supported(struct phy_device *phydev);
b6469127 1988void phy_advertise_eee_all(struct phy_device *phydev);
c306ad36 1989void phy_support_sym_pause(struct phy_device *phydev);
af8d9bb2 1990void phy_support_asym_pause(struct phy_device *phydev);
49168d19 1991void phy_support_eee(struct phy_device *phydev);
b55498ff 1992void phy_disable_eee(struct phy_device *phydev);
0c122405
AL
1993void phy_set_sym_pause(struct phy_device *phydev, bool rx, bool tx,
1994 bool autoneg);
70814e81 1995void phy_set_asym_pause(struct phy_device *phydev, bool rx, bool tx);
22b7d299
AL
1996bool phy_validate_pause(struct phy_device *phydev,
1997 struct ethtool_pauseparam *pp);
a87ae8a9 1998void phy_get_pause(struct phy_device *phydev, bool *tx_pause, bool *rx_pause);
92252eec
DM
1999
2000s32 phy_get_internal_delay(struct phy_device *phydev, struct device *dev,
2001 const int *delay_values, int size, bool is_rx);
2002
961ee5ae
DF
2003int phy_get_tx_amplitude_gain(struct phy_device *phydev, struct device *dev,
2004 enum ethtool_link_mode_bit_indices linkmode,
2005 u32 *val);
2006
145436ae
DF
2007int phy_get_mac_termination(struct phy_device *phydev, struct device *dev,
2008 u32 *val);
2009
a87ae8a9
RK
2010void phy_resolve_pause(unsigned long *local_adv, unsigned long *partner_adv,
2011 bool *tx_pause, bool *rx_pause);
00db8189 2012
f62220d3 2013int phy_register_fixup_for_id(const char *bus_id,
4017b4d3 2014 int (*run)(struct phy_device *));
f62220d3 2015int phy_register_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask,
4017b4d3 2016 int (*run)(struct phy_device *));
f62220d3 2017
f38e7a32
WH
2018int phy_unregister_fixup(const char *bus_id, u32 phy_uid, u32 phy_uid_mask);
2019int phy_unregister_fixup_for_id(const char *bus_id);
2020int phy_unregister_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask);
2021
a00e0d34 2022int phy_eee_tx_clock_stop_capable(struct phy_device *phydev);
cf337105 2023int phy_eee_rx_clock_stop(struct phy_device *phydev, bool clk_stop_enable);
a59a4d19
GC
2024int phy_init_eee(struct phy_device *phydev, bool clk_stop_enable);
2025int phy_get_eee_err(struct phy_device *phydev);
d80a5233
HK
2026int phy_ethtool_set_eee(struct phy_device *phydev, struct ethtool_keee *data);
2027int phy_ethtool_get_eee(struct phy_device *phydev, struct ethtool_keee *data);
42e836eb 2028int phy_ethtool_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol);
4017b4d3
SS
2029void phy_ethtool_get_wol(struct phy_device *phydev,
2030 struct ethtool_wolinfo *wol);
9d9a77ce
PR
2031int phy_ethtool_get_link_ksettings(struct net_device *ndev,
2032 struct ethtool_link_ksettings *cmd);
2033int phy_ethtool_set_link_ksettings(struct net_device *ndev,
2034 const struct ethtool_link_ksettings *cmd);
e86a8987 2035int phy_ethtool_nway_reset(struct net_device *ndev);
a59a4d19 2036
17809516
FF
2037int phy_ethtool_get_strings(struct phy_device *phydev, u8 *data);
2038int phy_ethtool_get_sset_count(struct phy_device *phydev);
2039int phy_ethtool_get_stats(struct phy_device *phydev,
2040 struct ethtool_stats *stats, u64 *data);
b7a2c1fe
JK
2041
2042void __phy_ethtool_get_phy_stats(struct phy_device *phydev,
2043 struct ethtool_eth_phy_stats *phy_stats,
2044 struct ethtool_phy_stats *phydev_stats);
2045void __phy_ethtool_get_link_ext_stats(struct phy_device *phydev,
2046 struct ethtool_link_ext_stats *link_stats);
2047
a23a1e57
PB
2048int phy_ethtool_get_plca_cfg(struct phy_device *phydev,
2049 struct phy_plca_cfg *plca_cfg);
2050int phy_ethtool_set_plca_cfg(struct phy_device *phydev,
2051 const struct phy_plca_cfg *plca_cfg,
2052 struct netlink_ext_ack *extack);
2053int phy_ethtool_get_plca_status(struct phy_device *phydev,
2054 struct phy_plca_status *plca_st);
9b9a8bfc 2055
60495b66
VO
2056int __phy_hwtstamp_get(struct phy_device *phydev,
2057 struct kernel_hwtstamp_config *config);
2058int __phy_hwtstamp_set(struct phy_device *phydev,
2059 struct kernel_hwtstamp_config *config,
2060 struct netlink_ext_ack *extack);
2061
81800aef 2062extern const struct bus_type mdio_bus_type;
a3e1c0ad 2063extern const struct class mdio_bus_class;
c31accd1 2064
648ea013
FF
2065struct mdio_board_info {
2066 const char *bus_id;
2067 char modalias[MDIO_NAME_SIZE];
2068 int mdio_addr;
2069 const void *platform_data;
2070};
2071
648ea013
FF
2072int mdiobus_register_board_info(const struct mdio_board_info *info,
2073 unsigned int n);
648ea013 2074
c31accd1 2075/**
39097ab6 2076 * phy_module_driver() - Helper macro for registering PHY drivers
c31accd1 2077 * @__phy_drivers: array of PHY drivers to register
39097ab6 2078 * @__count: Numbers of members in array
c31accd1
JH
2079 *
2080 * Helper macro for PHY drivers which do not do anything special in module
2081 * init/exit. Each module may only use this macro once, and calling it
2082 * replaces module_init() and module_exit().
2083 */
2084#define phy_module_driver(__phy_drivers, __count) \
2085static int __init phy_module_init(void) \
2086{ \
be01da72 2087 return phy_drivers_register(__phy_drivers, __count, THIS_MODULE); \
c31accd1
JH
2088} \
2089module_init(phy_module_init); \
2090static void __exit phy_module_exit(void) \
2091{ \
2092 phy_drivers_unregister(__phy_drivers, __count); \
2093} \
2094module_exit(phy_module_exit)
2095
2096#define module_phy_driver(__phy_drivers) \
2097 phy_module_driver(__phy_drivers, ARRAY_SIZE(__phy_drivers))
2098
5db5ea99
FF
2099bool phy_driver_is_genphy(struct phy_device *phydev);
2100bool phy_driver_is_genphy_10g(struct phy_device *phydev);
2101
00db8189 2102#endif /* __PHY_H */